Searched refs:IP (Results 1 - 9 of 9) sorted by relevance

/art/compiler/utils/arm/
H A Dassembler_arm32.cc1415 CHECK(rn != IP);
1417 mvn(IP, shifter_op, cond, kCcKeep);
1418 add(rd, rn, ShifterOperand(IP), cond, set_cc);
1420 mvn(IP, shifter_op, cond, kCcKeep);
1421 sub(rd, rn, ShifterOperand(IP), cond, set_cc);
1423 movw(IP, Low16Bits(value), cond);
1426 movt(IP, value_high, cond);
1428 add(rd, rn, ShifterOperand(IP), cond, set_cc);
1440 movw(IP, Low16Bits(value), cond);
1443 movt(IP, value_hig
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H A Dassembler_thumb2.cc2274 int32_t mov_encoding = MovModImmEncoding32(IP, offset & ~0x3ff);
2275 int16_t add_pc_encoding = AddRdnRmEncoding16(IP, PC);
2276 int32_t ldr_encoding = LoadWideOrFpEncoding(IP, offset & 0x3ff); // DCHECKs type_.
2286 int32_t movw_encoding = MovwEncoding32(IP, offset & 0xffff);
2287 int32_t movt_encoding = MovtEncoding32(IP, offset & ~0xffff);
2288 int16_t add_pc_encoding = AddRdnRmEncoding16(IP, PC);
2289 int32_t ldr_encoding = LoadWideOrFpEncoding(IP, 0); // DCHECKs type_.
3509 CHECK(rn != IP);
3510 // If rd != rn, use rd as temp. This alows 16-bit ADD/SUB in more situations than using IP.
3511 Register temp = (rd != rn) ? rd : IP;
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H A Dassembler_thumb2_test.cc288 __ StoreToOffset(type, arm::IP, arm::SP, offset);
289 __ StoreToOffset(type, arm::IP, arm::R5, offset);
304 __ StoreToOffset(type, arm::IP, arm::SP, offset);
305 __ StoreToOffset(type, arm::IP, arm::R5, offset);
329 // We cannot use IP (i.e. R12) as first source register, as it would
335 // So we use (R11, IP) (e.g. (R11, R12)) as source registers in the
354 // regarding the use of (R11, IP) (e.g. (R11, R12)) as source
H A Dassembler_arm.h724 // Add signed constant value to rd. May clobber IP.
736 // Load and Store. May clobber IP.
748 LoadImmediate(IP, int_value, cond);
749 vmovsr(sd, IP, cond);
/art/runtime/arch/arm/
H A Dregisters_arm.h45 IP = 12, enumerator in enum:art::arm::Register
/art/compiler/optimizing/
H A Dcode_generator_arm.cc840 blocked_core_registers_[IP] = true;
909 __ AddConstant(IP, SP, -static_cast<int32_t>(GetStackOverflowReservedBytes(kArm)));
910 __ LoadFromOffset(kLoadWord, IP, IP, 0);
1095 __ LoadFromOffset(kLoadWord, IP, SP, source.GetStackIndex());
1096 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex());
2667 // IP <- in1.lo * in2.hi
2668 __ mul(IP, in1_lo, in2_hi);
2670 __ mla(out_hi, in1_hi, in2_lo, IP);
2672 __ umull(out_lo, IP, in1_l
4432 __ LoadDFromOffset(FromLowSToD(out), IP, data_offset); local
4721 __ StoreDToOffset(FromLowSToD(value.AsFpuRegisterPairLow<SRegister>()), IP, data_offset); local
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H A Dintrinsics_arm.cc551 __ add(IP, base, ShifterOperand(offset));
554 __ ldrexd(trg_lo, trg_hi, IP);
556 __ ldrd(trg_lo, Address(IP));
710 __ add(IP, base, ShifterOperand(offset));
713 __ ldrexd(temp_lo, temp_hi, IP);
714 __ strexd(temp_lo, value_lo, value_hi, IP);
718 __ add(IP, base, ShifterOperand(offset));
719 __ strd(value_lo, Address(IP));
1587 __ ldr(IP, Address(temp1, element_size, Address::PostIndex));
1588 __ str(IP, Addres
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/art/compiler/jni/quick/arm/
H A Dcalling_convention_arm.cc48 return ArmManagedRegister::FromCoreRegister(IP); // R12
52 return ArmManagedRegister::FromCoreRegister(IP); // R12
/art/compiler/trampolines/
H A Dtrampoline_compiler.cc61 __ LoadFromOffset(kLoadWord, IP, R0, JNIEnvExt::SelfOffset(4).Int32Value());
62 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value());

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