Searched refs:IsRegister (Results 1 - 25 of 30) sorted by relevance

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/art/compiler/optimizing/
H A Dintrinsics_utils.h68 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
H A Dlocations.h138 bool IsRegister() const { function in class:art::Location
155 return IsRegister() || IsFpuRegister() || IsRegisterPair() || IsFpuRegisterPair();
159 DCHECK(IsRegister() || IsFpuRegister());
175 DCHECK(IsRegister());
415 if (loc.IsRegister()) {
424 if (loc.IsRegister()) {
582 return input.IsRegister()
H A Dlocations.cc87 if (location.IsRegister() || location.IsFpuRegister()) {
H A Dcommon_arm64.h56 DCHECK(location.IsRegister()) << location;
61 DCHECK(location.IsRegister()) << location;
133 if (location.IsRegister()) {
H A Dcode_generator_x86_64.cc255 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
598 DCHECK(index_.IsRegister());
799 if (current_method.IsRegister()) {
1127 if (destination.IsRegister()) {
1129 if (source.IsRegister()) {
1148 if (source.IsRegister()) {
1167 if (source.IsRegister()) {
1184 if (source.IsRegister()) {
1209 DCHECK(location.IsRegister());
1219 if (location.IsRegister()) {
[all...]
H A Dcode_generator_x86.cc267 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
987 if (destination.IsRegister()) {
988 if (source.IsRegister()) {
997 if (source.IsRegister()) {
1007 if (source.IsRegister()) {
1099 DCHECK(location.IsRegister());
1115 if (location.IsRegister()) {
1407 if (lhs.IsRegister()) {
1434 if (rhs.IsRegister()) {
1601 if (true_loc.IsRegister()) {
[all...]
H A Dcode_generator_mips64.cc201 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
644 if (destination.IsRegister() || destination.IsFpuRegister()) {
652 dst_type = destination.IsRegister() ? Primitive::kPrimInt : Primitive::kPrimFloat;
658 dst_type = destination.IsRegister() ? Primitive::kPrimLong : Primitive::kPrimDouble;
662 (destination.IsRegister() && !Primitive::IsFloatingPointType(dst_type)));
704 } else if (source.IsRegister()) {
705 if (destination.IsRegister()) {
726 DCHECK(destination.IsRegister());
736 if (source.IsRegister() || source.IsFpuRegister()) {
738 if (source.IsRegister()) {
[all...]
H A Dcode_generator_arm.cc223 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
1071 if (destination.IsRegister()) {
1072 if (source.IsRegister()) {
1080 if (source.IsRegister()) {
1089 if (source.IsRegister()) {
1168 DCHECK(location.IsRegister());
1179 if (location.IsRegister()) {
1422 DCHECK(cond_val.IsRegister());
1442 DCHECK(locations->InAt(0).IsRegister());
1445 if (right.IsRegister()) {
[all...]
H A Dregister_allocator.cc136 DCHECK(location.IsRegister() || location.IsFpuRegister());
137 LiveInterval* interval = location.IsRegister()
140 Primitive::Type type = location.IsRegister()
145 if (location.IsRegister()) {
237 if (temp.IsRegister() || temp.IsFpuRegister()) {
310 if (input.IsRegister() || input.IsFpuRegister()) {
365 if (first.IsRegister() || first.IsFpuRegister()) {
375 } else if (output.IsRegister() || output.IsFpuRegister()) {
1377 return destination.IsRegister()
H A Dcode_generator_mips.cc246 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
538 if (loc1.IsRegister() && loc2.IsRegister()) {
558 } else if ((loc1.IsRegister() && loc2.IsFpuRegister()) ||
559 (loc1.IsFpuRegister() && loc2.IsRegister())) {
564 Register r2 = loc1.IsRegister() ? loc1.AsRegister<Register>()
604 } else if ((loc1.IsRegister() && loc2.IsStackSlot()) ||
605 (loc1.IsStackSlot() && loc2.IsRegister())) {
606 Register reg = loc1.IsRegister() ? loc1.AsRegister<Register>()
828 if (destination.IsRegister()) {
[all...]
H A Dcode_generator_arm64.cc307 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
983 if (loc.IsRegister()) {
1064 DCHECK(location.IsRegister());
1069 if (location.IsRegister()) {
1196 if (destination.IsRegister() || destination.IsFpuRegister()) {
1204 dst_type = destination.IsRegister() ? Primitive::kPrimInt : Primitive::kPrimFloat;
1210 dst_type = destination.IsRegister() ? Primitive::kPrimLong : Primitive::kPrimDouble;
1214 (destination.IsRegister() && !Primitive::IsFloatingPointType(dst_type)));
1222 } else if (source.IsRegister()) {
1223 if (destination.IsRegister()) {
[all...]
H A Dssa_liveness_analysis.h938 && (locations->InAt(0).IsRegister()
949 } else if (location.IsRegister() || location.IsRegisterPair()) {
H A Dintrinsics_x86.cc281 DCHECK(locations->InAt(1).IsRegister());
470 DCHECK(locations->InAt(2).IsRegister());
706 DCHECK(out.IsRegister());
1669 DCHECK(srcBegin.IsRegister());
2399 if (src.IsRegister()) {
2469 if (src.IsRegister()) {
2574 if (src.IsRegister()) {
H A Dintrinsics_x86_64.cc526 DCHECK(out.IsRegister());
1768 DCHECK(srcBegin.IsRegister());
2419 if (src.IsRegister()) {
2495 if (src.IsRegister()) {
2523 if (src.IsRegister()) {
2610 if (src.IsRegister()) {
2684 if (src.IsRegister()) {
H A Dparallel_move_test.cc43 } else if (location.IsRegister()) {
H A Dssa_liveness_analysis.cc520 return other.IsRegister();
H A Dcode_generator.cc64 } else if (location.IsRegister() ||
509 if (location.IsRegister()) {
H A Dgraph_visualizer.cc290 if (location.IsRegister()) {
H A Dintrinsics_mips64.cc113 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
/art/disassembler/
H A Ddisassembler_arm64.cc45 if (reg.IsRegister() && reg.Is64Bits()) {
/art/compiler/utils/arm/
H A Dassembler_thumb2.cc1222 if (so.IsRegister() && IsHighRegister(so.GetRegister()) && !can_contain_high_register) {
1243 if (so.IsRegister() && rd != rn) {
1282 DCHECK(so.IsRegister());
1412 } else if (so.IsRegister()) {
1445 if (opcode == MOV && so.IsRegister() && so.IsShift()) {
1482 CHECK(!(so.IsRegister() && so.IsShift() && so.GetSecondRegister() != kNoRegister))
1644 if (so.IsRegister()) {
1716 if (so.IsRegister()) {
H A Dassembler_arm32_test.cc274 } else if (sop.IsRegister()) {
H A Dassembler_arm.h169 bool IsRegister() const { function in class:art::arm::ShifterOperand
/art/compiler/utils/x86/
H A Dassembler_x86.h85 bool IsRegister(Register reg) const { function in class:art::x86::Operand
/art/compiler/utils/x86_64/
H A Dassembler_x86_64.h97 bool IsRegister(CpuRegister reg) const { function in class:art::x86_64::Operand

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