| /art/compiler/utils/ |
| H A D | assembler_thumb_test.cc | 210 __ movs(R0, ShifterOperand(R1));
211 __ mov(R0, ShifterOperand(R1));
214 __ mov(R0, ShifterOperand(1));
223 __ mov(R0, ShifterOperand(R1));
230 __ mov(R0, ShifterOperand(R1));
231 __ adds(R0, R1, ShifterOperand(R2));
232 __ add(R0, R1, ShifterOperand(0));
239 __ mvn(R0, ShifterOperand(R1), AL, kCcKeep);
240 __ add(R0, R1, ShifterOperand(R2), AL, kCcKeep);
241 __ sub(R0, R
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| /art/compiler/utils/arm/ |
| H A D | assembler_thumb2_test.cc | 49 new arm::Register(arm::R0),
103 __ sbfx(arm::R0, arm::R1, 0, 1);
104 __ sbfx(arm::R0, arm::R1, 0, 8);
105 __ sbfx(arm::R0, arm::R1, 0, 16);
106 __ sbfx(arm::R0, arm::R1, 0, 32);
108 __ sbfx(arm::R0, arm::R1, 8, 1);
109 __ sbfx(arm::R0, arm::R1, 8, 8);
110 __ sbfx(arm::R0, arm::R1, 8, 16);
111 __ sbfx(arm::R0, arm::R1, 8, 24);
113 __ sbfx(arm::R0, ar
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| H A D | managed_register_arm_test.cc | 31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0);
37 EXPECT_EQ(R0, reg.AsCoreRegister());
235 EXPECT_EQ(R0, reg.AsRegisterPairLow());
237 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R0)));
292 EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromCoreRegister(R0)));
298 ArmManagedRegister reg_R0 = ArmManagedRegister::FromCoreRegister(R0);
300 EXPECT_TRUE(reg_R0.Equals(ArmManagedRegister::FromCoreRegister(R0)));
308 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromCoreRegister(R0)));
318 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromCoreRegister(R0)));
328 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromCoreRegister(R0)));
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| H A D | assembler_arm32_test.cc | 70 new arm::Register(arm::R0),
83 new arm::Register(arm::R0),
145 shifter_operands_.push_back(arm::ShifterOperand(arm::R0));
160 shifter_operands_.push_back(arm::ShifterOperand(arm::R0));
863 GetAssembler()->ldrexd(arm::R0, arm::R1, arm::R0);
864 GetAssembler()->ldrexd(arm::R0, arm::R1, arm::R1);
865 GetAssembler()->ldrexd(arm::R0, arm::R1, arm::R2);
875 GetAssembler()->strexd(arm::R9, arm::R0, arm::R1, arm::R0);
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| H A D | assembler_arm32.cc | 113 EmitType01(cond, so.type(), TST, kCcSet, rn, R0, so);
119 EmitType01(cond, so.type(), TEQ, kCcSet, rn, R0, so);
124 EmitType01(cond, so.type(), CMP, kCcSet, rn, R0, so);
129 EmitType01(cond, so.type(), CMN, kCcSet, rn, R0, so);
150 EmitType01(cond, so.type(), MOV, set_cc, R0, rd, so);
162 EmitType01(cond, so.type(), MVN, set_cc, R0, rd, so);
168 EmitMulOp(cond, 0, R0, rd, rn, rm);
559 EmitType01(AL, 1, TST, kCcSet, PC, R0, ShifterOperand(0));
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| H A D | assembler_arm.cc | 41 if (rhs >= R0 && rhs <= PC) {
394 CHECK_EQ(R0, method_reg.AsArm().AsCoreRegister());
421 StoreToOffset(kStoreWord, R0, SP, 0);
864 // Don't care about preserving R0 as this call won't return.
865 __ mov(R0, ShifterOperand(scratch_.AsCoreRegister()));
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| H A D | assembler_thumb2.cc | 592 EmitDataProcessing(cond, TST, kCcSet, rn, R0, so);
598 EmitDataProcessing(cond, TEQ, kCcSet, rn, R0, so);
603 EmitDataProcessing(cond, CMP, kCcSet, rn, R0, so);
608 EmitDataProcessing(cond, CMN, kCcSet, rn, R0, so);
626 EmitDataProcessing(cond, MOV, set_cc, R0, rd, so);
638 EmitDataProcessing(cond, MVN, set_cc, R0, rd, so);
1154 EmitDataProcessing(AL, TST, kCcSet, PC, R0, ShifterOperand(0));
1680 rn = R0;
1681 rd = R0;
1694 rn = R0;
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| H A D | assembler_arm.h | 271 Address(Register rn, int32_t offset = 0, Mode am = Offset) : rn_(rn), rm_(R0),
289 rn_(PC), rm_(R0), offset_(offset),
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| /art/runtime/arch/arm/ |
| H A D | registers_arm.cc | 29 if (rhs >= R0 && rhs <= PC) {
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| H A D | registers_arm.h | 27 R0 = 0, enumerator in enum:art::arm::Register
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| H A D | context_arm.cc | 33 gprs_[R0] = &arg0_;
76 gprs_[R0] = const_cast<uint32_t*>(&gZero);
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| H A D | context_arm.h | 49 SetGPR(R0, new_arg0_value);
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| /art/compiler/jni/quick/arm/ |
| H A D | calling_convention_arm.cc | 27 R0, R1, R2, R3
64 return ArmManagedRegister::FromCoreRegister(R0);
77 return ArmManagedRegister::FromCoreRegister(R0);
90 return ArmManagedRegister::FromCoreRegister(R0);
95 return ArmManagedRegister::FromCoreRegister(R0);
101 return ArmManagedRegister::FromCoreRegister(R0);
144 uint32_t gpr_index = 1; // R0 ~ R3. Reserve r0 for ArtMethod*.
296 R0, R1, R2, R3
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| /art/compiler/optimizing/ |
| H A D | optimizing_cfi_test.cc | 177 __ CompareAndBranchIfZero(arm::R0, &target);
180 __ ldr(arm::R0, arm::Address(arm::R0));
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| H A D | code_generator_arm.h | 43 static constexpr Register kArtMethodRegister = R0;
45 static constexpr Register kRuntimeParameterCoreRegisters[] = { R0, R1, R2, R3 };
108 return Location::RegisterLocation(R0);
112 ? Location::RegisterPairLocation(R0, R1)
113 : Location::RegisterLocation(R0);
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| H A D | intrinsics_arm.cc | 995 locations->SetOut(Location::RegisterLocation(R0));
1025 // Using instruction cbz requires a low register, so explicitly set a temp to be R0.
1026 locations->AddTemp(Location::RegisterLocation(R0));
1171 locations->SetOut(Location::RegisterLocation(R0));
1192 locations->SetOut(Location::RegisterLocation(R0));
1212 locations->SetOut(Location::RegisterLocation(R0));
1241 locations->SetOut(Location::RegisterLocation(R0));
1266 locations->SetOut(Location::RegisterLocation(R0));
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| H A D | code_generator_arm.cc | 48 static constexpr Register kMethodRegisterArgument = R0;
224 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0));
267 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0));
316 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0));
444 arm_codegen->Move32(out_, Location::RegisterLocation(R0));
595 arm_codegen->Move32(out_, Location::RegisterLocation(R0));
661 arm_codegen->Move32(out_, Location::RegisterLocation(R0));
1041 return Location::RegisterLocation(R0);
1049 return Location::RegisterPairLocation(R0, R1);
2094 locations->SetOut(Location::RegisterPairLocation(R0, R
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| /art/compiler/linker/arm/ |
| H A D | relative_patcher_thumb2.cc | 86 arm::kLoadWord, arm::PC, arm::R0,
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| /art/compiler/trampolines/ |
| H A D | trampoline_compiler.cc | 57 case kInterpreterAbi: // Thread* is first argument (R0) in interpreter ABI.
58 __ LoadFromOffset(kLoadWord, PC, R0, offset.Int32Value());
60 case kJniAbi: // Load via Thread* held in JNIEnv* in first argument (R0).
61 __ LoadFromOffset(kLoadWord, IP, R0, JNIEnvExt::SelfOffset(4).Int32Value());
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