Searched refs:base (Results 1 - 25 of 87) sorted by relevance

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/art/test/065-mismatched-implements/src/
H A DIndirect.java25 Base base = new Base();
/art/test/066-mismatched-super/src/
H A DIndirect.java25 Base base = new Base();
/art/compiler/optimizing/
H A Ddex_cache_array_fixups_arm.cc19 #include "base/arena_containers.h"
26 * Finds instructions that need the dex cache arrays base as an input.
38 // Bring the base closer to the first use (previously, it was in the
40 // while avoiding recalculation of the base in a loop.
41 HArmDexCacheArraysBase* base = entry.second; local
42 base->MoveBeforeFirstUserAndOutOfLoops();
49 // we need to add the dex cache arrays base as the special input.
51 // Initialize base for target dex file if needed.
53 HArmDexCacheArraysBase* base = GetOrCreateDexCacheArrayBase(dex_file); variable
54 // Update the element offset in base
68 HArmDexCacheArraysBase* base = GetOrCreateDexCacheArrayBase(*target_method.dex_file); variable
88 HArmDexCacheArraysBase* base = new (GetGraph()->GetArena()) HArmDexCacheArraysBase(dex_file); local
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H A Dcommon_arm64.h149 static inline vixl::MemOperand HeapOperand(const vixl::Register& base, size_t offset = 0) { argument
151 DCHECK(base.IsW());
152 return vixl::MemOperand(base.X(), offset);
155 static inline vixl::MemOperand HeapOperand(const vixl::Register& base, argument
160 DCHECK(base.IsW());
161 return vixl::MemOperand(base.X(), regoffset, shift, shift_amount);
164 static inline vixl::MemOperand HeapOperand(const vixl::Register& base, Offset offset) { argument
165 return HeapOperand(base, offset.SizeValue());
/art/test/564-checker-negbitwise/src/
H A DMain.java79 public static int $opt$noinline$notAnd(int base, int mask) { argument
81 return base & ~mask;
129 public static long $opt$noinline$notOr(long base, long mask) { argument
131 return base | ~mask;
176 public static int $opt$noinline$notXor(int base, int mask) { argument
178 return base ^ ~mask;
268 public static int $opt$noinline$notAndMultipleUses(int base, int mask) { argument
271 return (tmp & 0x1) + (base & tmp);
/art/runtime/arch/mips/
H A Dasm_support_mips.S74 from unaligned (mod-4-aligned) mem location disp(base) */
75 .macro LDu feven,fodd,disp,base,temp
76 l.s \feven, \disp(\base)
77 lw \temp, \disp+4(\base)
82 to unaligned (mod-4-aligned) mem location disp(base) */
83 .macro SDu feven,fodd,disp,base,temp
85 s.s \feven, \disp(\base)
86 sw \temp, \disp+4(\base)
101 .macro LDu feven,fodd,disp,base,temp
102 l.s \feven, \disp(\base)
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/art/compiler/utils/
H A Dassembler_test.h157 std::string base = fmt; local
161 while ((reg1_index = base.find(REG1_TOKEN)) != std::string::npos) {
162 base.replace(reg1_index, ConstexprStrLen(REG1_TOKEN), reg1_string);
167 while ((reg2_index = base.find(REG2_TOKEN)) != std::string::npos) {
168 base.replace(reg2_index, ConstexprStrLen(REG2_TOKEN), reg2_string);
171 size_t imm_index = base.find(IMM_TOKEN);
176 base.replace(imm_index, ConstexprStrLen(IMM_TOKEN), imm_string);
182 str += base;
209 std::string base = fmt; local
213 while ((reg1_index = base
256 std::string base = fmt; local
403 std::string base = fmt; local
630 std::string base = fmt; local
661 std::string base = fmt; local
700 std::string base = fmt; local
739 std::string base = fmt; local
788 std::string base = fmt; local
882 std::string base = fmt; local
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/art/runtime/
H A Dimage-inl.h50 uint8_t* base,
54 ImTable* imt = reinterpret_cast<ImTable*>(base + section.Offset() + pos);
68 uint8_t* base,
72 auto* table = reinterpret_cast<ImtConflictTable*>(base + section.Offset() + pos);
49 VisitPackedImTables(const Visitor& visitor, uint8_t* base, size_t pointer_size) const argument
67 VisitPackedImtConflictTables(const Visitor& visitor, uint8_t* base, size_t pointer_size) const argument
H A Dimage.cc19 #include "base/bit_utils.h"
150 void ImageHeader::VisitPackedArtFields(ArtFieldVisitor* visitor, uint8_t* base) const {
153 auto* array = reinterpret_cast<LengthPrefixedArray<ArtField>*>(base + fields.Offset() + pos);
162 uint8_t* base,
168 auto* array = reinterpret_cast<LengthPrefixedArray<ArtMethod>*>(base + methods.Offset() + pos);
176 auto* method = reinterpret_cast<ArtMethod*>(base + runtime_methods.Offset() + pos);
161 VisitPackedArtMethods(ArtMethodVisitor* visitor, uint8_t* base, size_t pointer_size) const argument
H A DAndroid.mk26 base/allocator.cc \
27 base/arena_allocator.cc \
28 base/arena_bit_vector.cc \
29 base/bit_vector.cc \
30 base/file_magic.cc \
31 base/hex_dump.cc \
32 base/logging.cc \
33 base/mutex.cc \
34 base/scoped_arena_allocator.cc \
35 base/scoped_floc
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H A Dimage.h274 // Visit ArtMethods in the section starting at base. Includes runtime methods.
275 // TODO: Delete base parameter if it is always equal to GetImageBegin.
276 void VisitPackedArtMethods(ArtMethodVisitor* visitor, uint8_t* base, size_t pointer_size) const;
278 // Visit ArtMethods in the section starting at base.
279 // TODO: Delete base parameter if it is always equal to GetImageBegin.
280 void VisitPackedArtFields(ArtFieldVisitor* visitor, uint8_t* base) const;
284 uint8_t* base,
289 uint8_t* base,
299 // Required base address for mapping the image.
/art/test/971-iface-super/util-src/
H A Dgenerate_java.py21 import generate_smali as base namespace
82 if isinstance(f, base.TestInterface):
83 JavaConverter(f.get_specific_version(base.InterfaceType.default)).dump(self.temp_dir)
89 ifaces = set(i for i in self.sources if isinstance(i, base.TestInterface))
91 converters = (lambda a: JavaConverter(a.get_specific_version(base.InterfaceType.default)),
92 lambda a: JavaConverter(a.get_specific_version(base.InterfaceType.empty)))
129 mainclass, all_files = base.create_all_test_files()
/art/compiler/utils/arm64/
H A Dassembler_arm64.cc18 #include "base/logging.h"
98 XRegister base, int32_t offset) {
101 ___ Strb(reg_w(source), MEM_OP(reg_x(base), offset));
104 ___ Strh(reg_w(source), MEM_OP(reg_x(base), offset));
107 ___ Str(reg_w(source), MEM_OP(reg_x(base), offset));
114 void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { argument
116 ___ Str(reg_x(source), MEM_OP(reg_x(base), offset));
119 void Arm64Assembler::StoreSToOffset(SRegister source, XRegister base, int32_t offset) { argument
120 ___ Str(reg_s(source), MEM_OP(reg_x(base), offset));
123 void Arm64Assembler::StoreDToOffset(DRegister source, XRegister base, int32_ argument
97 StoreWToOffset(StoreOperandType type, WRegister source, XRegister base, int32_t offset) argument
220 LoadWFromOffset(LoadOperandType type, WRegister dest, XRegister base, int32_t offset) argument
245 LoadFromOffset(XRegister dest, XRegister base, int32_t offset) argument
251 LoadSFromOffset(SRegister dest, XRegister base, int32_t offset) argument
256 LoadDFromOffset(DRegister dest, XRegister base, int32_t offset) argument
261 Load(Arm64ManagedRegister dest, XRegister base, int32_t offset, size_t size) argument
301 Arm64ManagedRegister base = m_base.AsArm64(); local
313 Arm64ManagedRegister base = m_base.AsArm64(); local
404 Arm64ManagedRegister base = src_base.AsArm64(); local
423 Arm64ManagedRegister base = m_dest_base.AsArm64(); local
516 Arm64ManagedRegister base = m_base.AsArm64(); local
525 Arm64ManagedRegister base = m_base.AsArm64(); local
536 Call(FrameOffset base, Offset offs, ManagedRegister m_scratch) argument
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H A Dassembler_arm64.h24 #include "base/arena_containers.h"
25 #include "base/logging.h"
140 void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs,
142 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
195 // Call to address held at [base+offset].
196 void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
197 void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
258 XRegister base, int32_t offset);
259 void StoreToOffset(XRegister source, XRegister base, int32_t offset);
260 void StoreSToOffset(SRegister source, XRegister base, int32_
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/art/test/106-exceptions2/src/
H A DMain.java134 Main base = new Main();
138 base.ifoo = x;
139 return base.noThrow(a,b,c);
143 Main base = new Main();
150 base.ifoo = x;
151 return base.checkThrow(a,b,c,d,e,f);
/art/test/968-default-partial-compile-generated/util-src/
H A Dgenerate_java.py21 import generate_smali as base namespace
82 if isinstance(f, base.TestInterface):
83 JavaConverter(f.get_specific_version(base.InterfaceType.default)).dump(self.temp_dir)
89 ifaces = set(i for i in self.sources if isinstance(i, base.TestInterface))
102 out = JavaConverter(overridden.get_specific_version(base.InterfaceType.empty))
125 mainclass, all_files = base.create_all_test_files()
/art/test/970-iface-super-resolution-generated/util-src/
H A Dgenerate_java.py21 import generate_smali as base namespace
63 mainclass, all_files = base.create_all_test_files()
72 if isinstance(f, base.TestInterface):
/art/test/449-checker-bce/src/
H A DMain.java350 static void constantIndexing7(int[] array, int base) { argument
351 // With constant offsets to symbolic base.
352 array[base] = 10;
353 array[base + 1] = 20;
354 array[base + 2] = 30;
355 array[base + 3] = 40;
380 static void constantIndexing8(int[] array, int base) { argument
381 // With constant offsets "both ways" to symbolic base.
382 array[base - 1] = 100;
383 array[base]
411 constantIndexing9(int[] array, int base) argument
444 constantIndexing10(int[] array, int base) argument
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/art/test/003-omnibus-opcodes/src/
H A DMethodCall.java56 MethodCallBase base = inst;
57 base.tryThing();
/art/runtime/arch/x86/
H A Dthread_x86.cc23 #include "base/macros.h"
47 const uintptr_t base = reinterpret_cast<uintptr_t>(this); local
65 entry.base0 = (base & 0x0000ffff);
66 entry.base1 = (base & 0x00ff0000) >> 16;
67 entry.base2 = (base & 0xff000000) >> 24;
105 gdt_entry.base_addr = base;
/art/test/072-precise-gc/src/
H A DMain.java61 static String generateString(String base, int num) { argument
62 return base + num;
/art/compiler/utils/mips/
H A Dassembler_mips.cc19 #include "base/bit_utils.h"
20 #include "base/casts.h"
488 void MipsAssembler::LlR2(Register rt, Register base, int16_t imm16) { argument
490 EmitI(0x30, base, rt, imm16);
493 void MipsAssembler::ScR2(Register rt, Register base, int16_t imm16) { argument
495 EmitI(0x38, base, rt, imm16);
498 void MipsAssembler::LlR6(Register rt, Register base, int16_t imm9) { argument
501 EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x36);
504 void MipsAssembler::ScR6(Register rt, Register base, int16_t imm9) { argument
507 EmitI(0x1f, base, r
1384 StoreConst32ToOffset(int32_t value, Register base, int32_t offset, Register temp) argument
1403 StoreConst64ToOffset(int64_t value, Register base, int32_t offset, Register temp) argument
2265 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset) argument
2308 LoadSFromOffset(FRegister reg, Register base, int32_t offset) argument
2319 LoadDFromOffset(FRegister reg, Register base, int32_t offset) argument
2366 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset) argument
2398 StoreSToOffset(FRegister reg, Register base, int32_t offset) argument
2409 StoreDToOffset(FRegister reg, Register base, int32_t offset) argument
2620 LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, bool unpoison_reference) argument
2631 LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) argument
2855 MipsManagedRegister base = mbase.AsMips(); local
2866 Call(FrameOffset base, Offset offset, ManagedRegister mscratch) argument
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/art/compiler/
H A Dcfi_test.h63 const uint8_t* base = actual_asm.data() + (isa == kThumb2 ? 1 : 0); local
64 disasm->Dump(stream, base, base + actual_asm.size());
/art/runtime/gc/space/
H A Ddlmalloc_space.h43 // base address is not guaranteed to be granted, if it is required,
152 void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size,
154 return CreateMspace(base, morecore_start, initial_size);
156 static void* CreateMspace(void* base, size_t morecore_start, size_t initial_size);
/art/compiler/utils/arm/
H A Dassembler_arm32.cc19 #include "base/bit_utils.h"
20 #include "base/logging.h"
323 Register base,
326 EmitMultiMemOp(cond, am, true, base, regs);
331 Register base,
334 EmitMultiMemOp(cond, am, false, base, regs);
660 Register base,
662 CHECK_NE(base, kNoRegister);
668 (static_cast<int32_t>(base) << kRnShift) |
1469 Register base,
322 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument
330 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument
657 EmitMultiMemOp(Condition cond, BlockAddressMode am, bool load, Register base, RegList regs) argument
1467 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument
1508 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument
1526 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument
1544 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument
1580 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument
1598 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument
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