Searched refs:DstReg (Results 1 - 25 of 122) sorted by relevance

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/external/mesa3d/src/mesa/program/
H A Dprogramopt.c91 newInst[i].DstReg.File = PROGRAM_OUTPUT;
92 newInst[i].DstReg.Index = VERT_RESULT_HPOS;
93 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i);
163 newInst[0].DstReg.File = PROGRAM_TEMPORARY;
164 newInst[0].DstReg.Index = hposTemp;
165 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
175 newInst[i].DstReg.File = PROGRAM_TEMPORARY;
176 newInst[i].DstReg.Index = hposTemp;
177 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW;
190 newInst[3].DstReg
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H A Dprog_optimize.c88 channel_mask = inst->DstReg.WriteMask & dst_mask;
134 const GLuint mask = mov->DstReg.WriteMask;
234 if (inst->DstReg.File == file) {
235 const GLuint index = inst->DstReg.Index;
237 inst->DstReg.Index = map[index];
298 if (inst->DstReg.File == PROGRAM_TEMPORARY) {
299 const GLuint index = inst->DstReg.Index;
302 if (inst->DstReg.RelAddr) {
326 if (numDst != 0 && inst->DstReg.File == PROGRAM_TEMPORARY) {
327 GLint chan, index = inst->DstReg
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H A Dprog_instruction.c53 inst[i].DstReg.File = PROGRAM_UNDEFINED;
54 inst[i].DstReg.WriteMask = WRITEMASK_XYZW;
55 inst[i].DstReg.CondMask = COND_TR;
56 inst[i].DstReg.CondSwizzle = SWIZZLE_NOOP;
307 if (inst->DstReg.WriteMask == WRITEMASK_X ||
308 inst->DstReg.WriteMask == WRITEMASK_Y ||
309 inst->DstReg.WriteMask == WRITEMASK_Z ||
310 inst->DstReg.WriteMask == WRITEMASK_W ||
311 inst->DstReg.WriteMask == 0x0) {
318 if (inst->SrcReg[i].File == inst->DstReg
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/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program_tex.c68 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
69 inst_mov->U.I.DstReg.Index = temp;
90 inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY;
91 inst_rcp->U.I.DstReg.Index = temp;
92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY;
102 inst_mul->U.I.DstReg.Index = temp;
165 struct rc_dst_register output_reg = inst->U.I.DstReg;
171 inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
172 inst->U.I.DstReg
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H A Dr3xx_vertprog.c194 t_dst_index(vp, &vpi->DstReg),
195 t_dst_mask(vpi->DstReg.WriteMask),
196 t_dst_class(vpi->DstReg.File));
210 t_dst_index(vp, &vpi->DstReg),
211 t_dst_mask(vpi->DstReg.WriteMask),
212 t_dst_class(vpi->DstReg.File));
226 t_dst_index(vp, &vpi->DstReg),
227 t_dst_mask(vpi->DstReg.WriteMask),
228 t_dst_class(vpi->DstReg.File));
243 t_dst_index(vp, &vpi->DstReg),
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H A Dradeon_compiler.c128 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT)
129 c->Program.OutputsWritten |= 1 << inst->U.I.DstReg.Index;
180 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) {
181 inst->U.I.DstReg.Index = new_output;
182 inst->U.I.DstReg.WriteMask &= writemask;
203 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) {
204 inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
205 inst->U.I.DstReg
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H A Dradeon_pair_translate.c90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0;
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0;
275 inst->DstReg.WriteMask);
284 if (inst->DstReg.File == RC_FILE_OUTPUT) {
285 if (inst->DstReg.Index == c->OutputDepth) {
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
289 if (inst->DstReg.Index == c->OutputColor[i]) {
293 inst->DstReg.WriteMask & RC_MASK_XYZ;
295 GET_BIT(inst->DstReg.WriteMask, 3);
302 pair->RGB.DestIndex = inst->DstReg
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H A Dradeon_program_alu.c45 struct rc_dst_register DstReg, struct rc_src_register SrcReg)
54 fpi->U.I.DstReg = DstReg;
62 struct rc_dst_register DstReg,
72 fpi->U.I.DstReg = DstReg;
81 struct rc_dst_register DstReg,
92 fpi->U.I.DstReg = DstReg;
204 if (inst->U.I.DstReg
42 emit1( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg) argument
59 emit2( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) argument
78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument
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H A Dradeon_emulate_branches.c76 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
77 inst_mov->U.I.DstReg.Index = rc_find_free_temporary(s->C);
78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X;
82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index;
166 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
167 inst_mov->U.I.DstReg.Index = proxies->Temporary[index].Index;
168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW;
185 inst_cmp->U.I.DstReg.File = file;
186 inst_cmp->U.I.DstReg.Index = index;
187 inst_cmp->U.I.DstReg
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H A Dradeon_vert_fc.c106 build_pred_dst(&new_inst->U.I.DstReg, fc_state);
126 build_pred_dst(&new_inst->U.I.DstReg, fc_state);
140 inst->U.I.DstReg.Pred = RC_PRED_INV;
146 inst->U.I.DstReg.Pred = RC_PRED_SET;
149 build_pred_dst(&inst->U.I.DstReg, fc_state);
160 build_pred_dst(&new_inst->U.I.DstReg, fc_state);
189 inst->U.I.DstReg.Pred = RC_PRED_SET;
205 build_pred_dst(&inst->U.I.DstReg, fc_state);
248 build_pred_dst(&inst->U.I.DstReg, &fc_state);
260 build_pred_dst(&inst->U.I.DstReg,
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H A Dr3xx_fragprog.c61 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth)
64 if (inst->DstReg.WriteMask & RC_MASK_Z) {
65 inst->DstReg.WriteMask = RC_MASK_W;
67 inst->DstReg.WriteMask = 0;
/external/llvm/lib/CodeGen/
H A DRegisterCoalescer.h33 unsigned DstReg; member in class:llvm::CoalescerPair
38 /// The sub-register index of the old DstReg in the new coalesced register.
50 /// True when DstReg and SrcReg are reversed from the original
54 /// The register class of the coalesced register, or NULL if DstReg
56 /// SrcReg and DstReg.
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
75 /// Swap SrcReg and DstReg. Return false if swapping is impossible
76 /// because DstReg is a physical register, or SubIdx is set.
83 /// Return true if DstReg i
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H A DOptimizePHIs.cpp92 unsigned DstReg = MI->getOperand(0).getReg(); local
105 if (SrcReg == DstReg)
135 unsigned DstReg = MI->getOperand(0).getReg(); local
136 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp96 unsigned DstReg = MI.getOperand(0).getReg(); local
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0);
125 unsigned DstBase = TRI.getHWRegIndex(DstReg);
126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
H A DSIInstrInfo.h45 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
H A DSIInstrInfo.cpp52 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, argument
56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
/external/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp126 unsigned DstReg; local
129 DstReg = MI.getOperand(Chan).getReg();
131 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
155 unsigned DstReg; local
158 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
160 DstReg = MI.getOperand(Chan-2).getReg();
163 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
183 unsigned DstReg = MI.getOperand(0).getReg(); local
187 TRI.getSubReg(DstReg, TR
202 unsigned DstReg = MI.getOperand(0).getReg(); local
272 unsigned DstReg = MI.getOperand( local
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H A DSIFixSGPRCopies.cpp132 unsigned DstReg = Copy.getOperand(0).getReg(); local
144 TargetRegisterInfo::isVirtualRegister(DstReg) ?
145 MRI.getRegClass(DstReg) :
146 TRI.getPhysRegClass(DstReg);
182 unsigned DstReg = MI.getOperand(0).getReg(); local
183 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
186 if (!MRI.hasOneUse(DstReg))
189 MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
204 MRI.setRegClass(DstReg, DstRC);
/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp141 unsigned DstReg = Dst.getReg(); local
144 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
149 PeepholeMap[DstReg] = SrcReg;
163 unsigned DstReg = Dst.getReg(); local
165 PeepholeMap[DstReg] = SrcReg;
180 unsigned DstReg = Dst.getReg(); local
182 PeepholeDoubleRegsMap[DstReg] =
192 unsigned DstReg = Dst.getReg(); local
195 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
200 PeepholeMap[DstReg]
215 unsigned DstReg = Dst.getReg(); local
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; local
192 DstReg = MCI.getOperand(0).getReg();
196 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
210 DstReg = MCI.getOperand(0).getReg();
212 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
231 DstReg = MCI.getOperand(0).getReg();
233 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
241 DstReg = MCI.getOperand(0).getReg();
243 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
251 DstReg
538 unsigned DstReg, SrcReg; local
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H A DHexagonMCCompound.cpp84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
100 DstReg = MI.getOperand(0).getReg();
103 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
114 DstReg = MI.getOperand(0).getReg();
116 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
126 DstReg = MI.getOperand(0).getReg();
128 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
136 DstReg
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/external/mesa3d/src/mesa/state_tracker/
H A Dst_atom_pixeltransfer.c163 inst[ic].DstReg.File = PROGRAM_TEMPORARY;
164 inst[ic].DstReg.Index = colorTemp;
187 inst[ic].DstReg.File = PROGRAM_TEMPORARY;
188 inst[ic].DstReg.Index = colorTemp;
216 inst[ic].DstReg.File = PROGRAM_TEMPORARY;
217 inst[ic].DstReg.Index = temp;
218 inst[ic].DstReg.WriteMask = WRITEMASK_XY; /* write R,G */
228 inst[ic].DstReg.File = PROGRAM_TEMPORARY;
229 inst[ic].DstReg.Index = temp;
230 inst[ic].DstReg
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/external/mesa3d/src/gallium/drivers/r300/compiler/tests/
H A Drc_test_helpers.c241 inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
243 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
251 inst->U.I.DstReg.Index = strtol(tokens.Index.String, NULL, 10);
260 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
270 inst->U.I.DstReg.WriteMask |= RC_MASK_X;
273 inst->U.I.DstReg.WriteMask |= RC_MASK_Y;
276 inst->U.I.DstReg.WriteMask |= RC_MASK_Z;
279 inst->U.I.DstReg.WriteMask |= RC_MASK_W;
288 inst->U.I.DstReg.File,
289 inst->U.I.DstReg
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/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp143 unsigned DstReg = MI.getOperand(0).getReg(); local
145 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
146 .addReg(DstReg).addImm(-Offset);
148 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
149 .addReg(DstReg).addImm(Offset);
/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp117 const unsigned DstReg = MI.getOperand(0).getReg(); local
121 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
122 .addReg(DstReg)
182 const unsigned DstReg = MI.getOperand(0).getReg();
198 .addReg(DstReg,
200 .addReg(DstReg)
223 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
224 .addReg(DstReg)
365 const unsigned DstReg = MI.getOperand(0).getReg();
372 .addReg(DstReg,
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