Searched refs:LiveRegs (Results 1 - 10 of 10) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h45 SparseSet<unsigned> LiveRegs; member in class:llvm::LivePhysRegs
51 LivePhysRegs() : TRI(nullptr), LiveRegs() {}
56 LiveRegs.setUniverse(TRI->getNumRegs());
63 LiveRegs.clear();
64 LiveRegs.setUniverse(TRI->getNumRegs());
68 void clear() { LiveRegs.clear(); }
71 bool empty() const { return LiveRegs.empty(); }
79 LiveRegs.insert(*SubRegs);
89 LiveRegs.erase(*SubRegs);
92 LiveRegs
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H A DScheduleDAGInstrs.h166 BitVector LiveRegs; member in class:llvm::ScheduleDAGInstrs
H A DRegisterPressure.h294 LiveRegSet LiveRegs;
/external/llvm/lib/CodeGen/
H A DExecutionDepsFix.cpp142 LiveReg *LiveRegs;
188 // LiveRegs manipulations.
266 /// Set LiveRegs[rx] = dv, updating reference counts.
269 assert(LiveRegs && "Must enter basic block first.");
271 if (LiveRegs[rx].Value == dv)
273 if (LiveRegs[rx].Value)
274 release(LiveRegs[rx].Value);
275 LiveRegs[rx].Value = retain(dv);
281 assert(LiveRegs && "Must enter basic block first.");
282 if (!LiveRegs[r
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H A DStackMapLivenessAnalysis.cpp53 LivePhysRegs LiveRegs; member in class:__anon12292::StackMapLiveness
124 LiveRegs.init(TRI);
125 LiveRegs.addLiveOuts(&MBB);
136 DEBUG(dbgs() << " " << LiveRegs << " " << *I);
137 LiveRegs.stepBackward(*I);
159 for (auto Reg : LiveRegs)
H A DLivePhysRegs.cpp31 SparseSet<unsigned>::iterator LRI = LiveRegs.begin();
32 while (LRI != LiveRegs.end()) {
36 LRI = LiveRegs.erase(LRI);
129 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
130 static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) { argument
132 LiveRegs.addReg(LI.PhysReg);
135 /// Add pristine registers to the given \p LiveRegs. This function removes
137 static void addPristines(LivePhysRegs &LiveRegs, const MachineFunction &MF, argument
144 LiveRegs.addReg(*CSR);
146 LiveRegs
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H A DRegisterPressure.cpp193 LiveRegs.clear();
226 LiveRegs.init(*MRI);
265 P.LiveInRegs.reserve(LiveRegs.size());
266 LiveRegs.appendTo(P.LiveInRegs);
277 P.LiveOutRegs.reserve(LiveRegs.size());
278 LiveRegs.appendTo(P.LiveOutRegs);
284 assert(LiveRegs.size() == 0 && "no region boundary");
486 if (LiveRegs.insert(Reg))
493 assert(!LiveRegs.contains(Reg) && "avoid bumping max pressure twice");
504 assert(!LiveRegs
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H A DScheduleDAGInstrs.cpp1161 LiveRegs.reset();
1170 LiveRegs.set(*SubRegs);
1224 if (LiveRegs.test(MO.getReg())) {
1238 if (LiveRegs.test(*SubRegs)) {
1255 LiveRegs.resize(TRI->getNumRegs());
1274 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1285 LiveRegs.reset(*SubRegs);
1303 if (LiveRegs.test(*SubRegs)) {
1312 kill = !LiveRegs.test(Reg);
1341 LiveRegs
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/external/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp49 LivePhysRegs LiveRegs; member in class:__anon12754::SystemZShortenInst
84 if (LiveRegs.contains(OtherReg))
140 if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
179 LiveRegs.clear();
180 LiveRegs.addLiveOuts(&MBB);
260 LiveRegs.stepBackward(MI);
270 LiveRegs.init(TRI);
/external/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp84 LivePhysRegs LiveRegs; member in struct:__anon12524::ARMLoadStoreOpt
542 if (!LiveRegs.contains(Reg))
554 LiveRegs.init(TRI);
555 LiveRegs.addLiveOuts(&MBB, true);
562 LiveRegs.stepBackward(*LiveRegPos);
645 LiveRegs.addReg(R.first);

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