Searched refs:Reg0 (Results 1 - 13 of 13) sorted by relevance

/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp248 unsigned Reg0 = Op0.getReg(); local
249 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
253 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
255 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h599 uint16_t Reg0; member in class:llvm::MCRegUnitRootIterator
602 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
605 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
611 return Reg0;
616 return Reg0;
622 Reg0 = Reg1;
/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1857 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
1869 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1877 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1880 Ops.push_back(Reg0);
1893 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1906 Ops.push_back(Reg0);
1910 Ops.push_back(Reg0);
1984 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2020 // FIXME: VST1/VST2 fixed increment doesn't need Reg0
2148 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2244 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2347 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2582 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2599 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
3834 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); local
[all...]
H A DThumb2SizeReduction.cpp658 unsigned Reg0 = MI->getOperand(0).getReg(); local
664 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
667 if (Reg0 != Reg2) {
670 if (Reg1 != Reg0)
677 } else if (Reg0 != Reg1) {
682 MI->getOperand(CommOpIdx2).getReg() != Reg0)
689 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
H A DARMAsmPrinter.cpp301 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); local
302 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp226 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); local
249 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
264 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
/external/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp139 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; local
153 if (HasDef && Reg0 == Reg1 &&
156 Reg0 = Reg2;
158 } else if (HasDef && Reg0 == Reg2 &&
161 Reg0 = Reg1;
172 MI->getOperand(0).setReg(Reg0);
H A DRegisterCoalescer.cpp1891 unsigned Reg0; local
1892 std::tie(Orig0, Reg0) = followCopyChain(Value0);
1904 return Orig0->def == Orig1->def && Reg0 == Reg1;
/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp440 unsigned Reg0 = local
446 std::swap(Reg0, Reg1);
449 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
458 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); local
462 std::swap(Reg0, Reg1);
465 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp1459 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1462 printRegName(O, Reg0);
1472 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1475 printRegName(O, Reg0);
1527 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1530 printRegName(O, Reg0);
1574 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1577 printRegName(O, Reg0);
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1438 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, argument
1442 tmpInst.addOperand(MCOperand::createReg(Reg0));
1448 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, argument
1450 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, Instructions);
1453 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, argument
1455 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, Instructions);
1468 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, argument
1472 tmpInst.addOperand(MCOperand::createReg(Reg0));
1477 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, argument
1481 tmpInst.addOperand(MCOperand::createReg(Reg0));
1488 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument
1494 emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp348 unsigned Reg0 = MI->getOperand(0).getReg(); local
358 if (Reg0 == Reg1) {
378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); local
381 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp5656 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; local
5666 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5667 (HasDef && Reg0 == Reg2 && Tied2))
6498 // Scale should be 1, Index should be Reg0.

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