Searched refs:RegUnit (Results 1 - 10 of 10) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h139 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
H A DMachineRegisterInfo.h546 /// virtual register. If RegUnit is physical, it must be a register unit (from
548 PSetIterator getPressureSets(unsigned RegUnit) const;
960 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { argument
962 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
963 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
968 PSet = TRI->getRegUnitPressureSets(RegUnit);
969 Weight = TRI->getRegUnitWeight(RegUnit);
989 getPressureSets(unsigned RegUnit) const {
990 return PSetIterator(RegUnit, this);
H A DRegisterPressure.h138 void addPressureChange(unsigned RegUnit, bool IsDec,
/external/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp172 unsigned RegUnit) {
173 LiveIntervalUnion::Query &Q = Queries[RegUnit];
174 Q.init(UserTag, &VirtReg, &Matrix[RegUnit]);
171 query(LiveInterval &VirtReg, unsigned RegUnit) argument
H A DRegisterPressure.cpp95 for (unsigned RegUnit : RegUnits) {
96 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
109 for (unsigned RegUnit : RegUnits)
110 decreaseSetPressure(CurrSetPressure, MRI->getPressureSets(RegUnit));
311 static bool containsReg(ArrayRef<unsigned> RegUnits, unsigned RegUnit) { argument
312 return std::find(RegUnits.begin(), RegUnits.end(), RegUnit) != RegUnits.end();
436 void PressureDiff::addPressureChange(unsigned RegUnit, bool IsDec, argument
438 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
H A DMachineTraceMetrics.cpp677 unsigned RegUnit;
682 unsigned getSparseSetIndex() const { return RegUnit; }
684 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {}
1116 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle));
1117 DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI)
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h435 struct RegUnit { struct in namespace:llvm
436 // Weight assigned to this RegUnit for estimating register pressure.
441 // Each native RegUnit corresponds to one or two root registers. The full
450 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { function in struct:llvm::RegUnit
499 SmallVector<RegUnit, 8> RegUnits;
513 // class's units and any inferred RegUnit supersets.
646 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
647 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
H A DRegisterInfoEmitter.cpp208 << "getRegUnitWeight(unsigned RegUnit) const {\n"
209 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
215 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
216 assert(RU.Weight < 256 && "RegUnit too heavy");
220 << " return RUWeightTable[RegUnit];\n";
305 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
306 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
316 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
1088 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
1096 << "unsigned RegUnit) cons
[all...]
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h573 /// Returns a (RegUnit, LaneMask) pair.
603 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { argument
604 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
605 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
606 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h413 /// Returns true if Reg contains RegUnit.
414 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
416 if (*Units == RegUnit)
685 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
705 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;

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