Searched refs:masked (Results 1 - 18 of 18) sorted by relevance

/external/jetty/src/java/org/eclipse/jetty/websocket/
H A DWebSocketParserD06.java78 * @param masked whether masking should be handled
80 public WebSocketParserD06(WebSocketBuffers buffers, EndPoint endp, FrameHandler handler, boolean masked) argument
85 _masked=masked;
/external/libvncserver/test/
H A Dcursortest.c257 rfbBool masked=(c->mask[(i/8)+maskStride*j]<<(i&7))&0x80; local
258 c->alphaSource[i+c->width*j]=(masked?(mode==1?value:0xff-value):0);
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_swizzle.c402 LLVMValueRef masked; local
408 masked = LLVMBuildAnd(builder, a,
411 shifted = LLVMBuildShl(builder, masked,
414 shifted = LLVMBuildLShr(builder, masked,
417 shifted = masked;
H A Dlp_bld_format_aos.c154 LLVMValueRef shifted, casted, scaled, masked; local
227 * into masked = {B, G, R, A}
230 masked = LLVMBuildAnd(builder, shifted, LLVMConstVector(masks, 4), "");
235 casted = LLVMBuildSIToFP(builder, masked, LLVMVectorType(LLVMFloatTypeInContext(gallivm->context), 4), "");
237 casted = LLVMBuildUIToFP(builder, masked, LLVMVectorType(LLVMFloatTypeInContext(gallivm->context), 4), "");
/external/webrtc/webrtc/base/
H A Dipaddress.cc350 in_addr masked; local
351 masked.s_addr = HostToNetwork32(host_order_ip & mask);
352 return IPAddress(masked);
/external/deqp/modules/gles2/functional/
H A Des2fDepthStencilClearTests.cpp121 DepthStencilClearCase (Context& context, const char* name, const char* description, int numIters, int numClears, bool depth, bool stencil, bool scissor, bool masked);
145 DepthStencilClearCase::DepthStencilClearCase (Context& context, const char* name, const char* description, int numIters, int numClears, bool depth, bool stencil, bool scissor, bool masked) argument
150 , m_masked (masked)
503 // iters clears depth stencil scissor masked
/external/deqp/modules/gles3/functional/
H A Des3fDepthStencilClearTests.cpp121 DepthStencilClearCase (Context& context, const char* name, const char* description, int numIters, int numClears, bool depth, bool stencil, bool scissor, bool masked);
145 DepthStencilClearCase::DepthStencilClearCase (Context& context, const char* name, const char* description, int numIters, int numClears, bool depth, bool stencil, bool scissor, bool masked) argument
150 , m_masked (masked)
506 // iters clears depth stencil scissor masked
/external/llvm/test/MC/Mips/
H A Dnacl-mask.s98 # are not masked.
160 # are not masked.
/external/kernel-headers/original/uapi/asm-x86/asm/
H A Dkvm.h310 __u8 masked; member in struct:kvm_vcpu_events::__anon7787
/external/elfutils/libcpu/
H A Di386_disasm.c427 uint_fast8_t masked = *codep++ & *curr++; local
428 if (masked != *curr++)
/external/nanohttpd/websocket/src/main/java/fi/iki/elonen/
H A DNanoWSD.java609 boolean masked = (b & 0x80) != 0;
640 if (masked) {
687 sb.append(", ").append(isMasked() ? "masked" : "unmasked");
/external/webrtc/webrtc/examples/androidapp/third_party/autobanh/
H A Dautobanh.jarMETA-INF/MANIFEST.MF de/tavendo/autobahn/ByteBufferInputStream.class ByteBufferInputStream.java package de.tavendo ...
/external/v8/src/compiler/
H A Dwasm-compiler.cc973 int32_t masked = (match.Value() & kMask32); local
974 if (match.Value() != masked) node = jsgraph()->Int32Constant(masked);
989 int64_t masked = (match.Value() & kMask64); local
990 if (match.Value() != masked) node = jsgraph()->Int64Constant(masked);
/external/chromium-trace/catapult/telemetry/third_party/web-page-replay/third_party/ipaddr/
H A Dipaddr_test.py53 self.assertEqual(addr1_masked, addr1.masked())
57 self.assertEqual(addr2_masked, addr2.masked())
H A Dipaddr.py951 def masked(self): member in class:_BaseNet
952 """Return the network object with the host bits masked out."""
/external/wpa_supplicant_8/wpa_supplicant/
H A Dconfig.c264 u8 abort_on_error, u8 masked)
278 if (hwaddr_masked_aton(pos, addr, &addr[ETH_ALEN], masked)) {
261 wpa_config_parse_addr_list(const struct parse_data *data, int line, const char *value, u8 **list, size_t *num, char *name, u8 abort_on_error, u8 masked) argument
/external/valgrind/VEX/priv/
H A Dguest_arm_toIR.c976 masked out. If the resulting value is zero then the GE flag is
988 IRTemp masked = newTemp(Ity_I32); local
989 assign(masked, binop(Iop_Shr32, e, mkU8(lowbits_to_ignore)));
992 case 0: putMiscReg32(OFFB_GEFLAG0, mkexpr(masked), condT); break;
993 case 1: putMiscReg32(OFFB_GEFLAG1, mkexpr(masked), condT); break;
994 case 2: putMiscReg32(OFFB_GEFLAG2, mkexpr(masked), condT); break;
995 case 3: putMiscReg32(OFFB_GEFLAG3, mkexpr(masked), condT); break;
12781 has the top 4 bits masked out. Caller is responsible for
12782 determining whether the masked-out bits are valid for a CP10/11
H A Dguest_amd64_toIR.c3640 Therefore the shift amount is masked with 63 for 64-bit shifts
3825 masked in this way. */
7847 /* Calculate the masked shift amount (tmpSH), the masked subshift
8054 t_bitno1 is the bit number, suitably masked in the case of a
14990 /* 0F F7 = MASKMOVQ -- 8x8 masked store */
18783 OR into a suitably masked-out v128.*/
18813 OR into a suitably masked-out v128.*/
27714 /* Masked load or masked store. */
29925 IRExpr* masked = binop(mkSizedOp(ty,Iop_And8), local
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