Searched refs:reg1 (Results 1 - 25 of 73) sorted by relevance

123

/external/libavc/common/armv8/
H A Dih264_neon_macros.s36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
/external/libmpeg2/common/armv8/
H A Dimpeg2_neon_macros.s53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
/external/llvm/test/MC/MachO/
H A Dbad-macro.s5 .macro test_macro reg1, reg2
/external/libvpx/libvpx/vpx_dsp/mips/
H A Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7);
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1);
75 reg2 = reg1 + reg5;
76 reg1
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
359 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
439 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
[all...]
H A Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
40 DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15);
43 reg9 = reg1 - loc2;
44 reg1 = reg1 + loc2;
57 loc1 = reg1
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
[all...]
H A Dtxfm_macros_msa.h16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) { \
23 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
24 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
/external/libunwind/src/ptrace/
H A D_UPT_access_mem.c63 long reg1, reg2;
64 reg1 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) addr, 0);
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1;
/external/webrtc/webrtc/system_wrappers/include/
H A Dasm_defines.h59 .macro streqh reg1, reg2, num
60 strheq \reg1, \reg2, \num variable
/external/boringssl/src/crypto/perlasm/
H A Dx86masm.pl39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
42 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
61 $ret .= "+$reg1" if ($reg1 ne "");
64 { $ret .= "$reg1"; }
H A Dx86nasm.pl36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
39 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
62 $ret .= "+$reg1" if ($reg1 ne "");
65 { $ret .= "$reg1"; }
H A Dx86gas.pl70 { my($addr,$reg1,$reg2,$idx)=@_;
73 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
79 $reg1 = "%$reg1" if ($reg1);
86 $ret .= "($reg1,$reg2,$idx)";
88 elsif ($reg1)
89 { $ret .= "($reg1)"; }
/external/v8/src/compiler/mips64/
H A Dcode-generator-mips64.cc903 Register reg1 = kScratchReg; local
914 __ li(reg1, 0x1F);
915 __ Subu(i.OutputRegister(), reg1, reg2);
923 Register reg1 = kScratchReg; local
934 __ li(reg1, 0x3F);
935 __ Subu(i.OutputRegister(), reg1, reg2);
943 Register reg1 = kScratchReg; local
953 __ dsrl(reg1, i.InputRegister(0), 1);
955 __ And(reg1, reg1, a
987 Register reg1 = kScratchReg; local
[all...]
/external/mesa3d/src/mesa/program/
H A Dregister_allocate.c189 struct ra_reg *reg1 = &regs->regs[r1]; local
191 if (reg1->conflict_list_size == reg1->num_conflicts) {
192 reg1->conflict_list_size *= 2;
193 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list,
194 unsigned int, reg1->conflict_list_size);
196 reg1->conflict_list[reg1->num_conflicts++] = r2;
197 reg1
[all...]
/external/v8/test/unittests/interpreter/
H A Dbytecode-register-allocator-unittest.cc157 int reg1 = allocator()->BorrowTemporaryRegisterNotInRange(3, 10); local
158 CHECK_EQ(reg1, 2);
162 allocator()->ReturnTemporaryRegister(reg1);
202 Register reg1 = allocator.NextConsecutiveRegister(); local
207 CHECK(Register::AreContiguous(reg0, reg1, reg2, reg3));
/external/skia/gm/
H A Dimageblurtiled.cpp78 static GMRegistry reg1(MyFactory1);
H A Dcomplexclip_blur_tiled.cpp74 static GMRegistry reg1(MyFactory1);
/external/v8/src/compiler/mips/
H A Dcode-generator-mips.cc847 Register reg1 = kScratchReg; local
858 __ li(reg1, 0x1F);
859 __ Subu(i.OutputRegister(), reg1, reg2);
867 Register reg1 = kScratchReg; local
877 __ srl(reg1, i.InputRegister(0), 1);
879 __ And(reg1, reg1, at);
880 __ addu(reg1, reg1, reg2);
884 __ srl(reg2, reg1,
[all...]
/external/aac/libFDK/src/
H A Dfixpoint_math.cpp430 FIXP_DBL reg1, reg2, regtmp ; local
445 reg1 = invSqrtTab[ (INT)(val>>(DFRACT_BITS-1-(SQRT_BITS+1))) & SQRT_BITS_MASK ];
448 regtmp= fPow2Div2(reg1); /* a = Q^2 */
450 reg1 += (fMultDiv2(regtmp, reg1)<<4); /* Q = Q + Q*b */
455 reg1 = fMultDiv2(reg1, reg2) << 2;
460 return(reg1);
/external/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp150 bool haveSameParity(unsigned reg1, unsigned reg2) { argument
151 assert(isFPReg(reg1) && "Expecting an FP register for reg1");
154 return isOdd(reg1) == isOdd(reg2);
/external/v8/test/cctest/
H A Dtest-utils-arm64.cc148 const Register& reg1) {
149 CHECK(reg0.Is64Bits() && reg1.Is64Bits());
151 int64_t result = core->xreg(reg1.code());
146 Equal64(const Register& reg0, const RegisterDump* core, const Register& reg1) argument
H A Dtest-utils-arm64.h190 const Register& reg1);
/external/vixl/test/
H A Dtest-utils-a64.cc180 const Register& reg1) {
181 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits());
183 int64_t result = core->xreg(reg1.code());
178 Equal64(const Register& reg0, const RegisterDump* core, const Register& reg1) argument
H A Dtest-utils-a64.h210 const Register& reg1);
/external/libvpx/libvpx/vpx_dsp/arm/
H A Didct32x32_add_neon.asm72 ; reg1 = output[first_offset]
78 LOAD_FROM_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
81 vld1.s16 {$reg1}, [r1]
84 ; (used) two registers ($reg1, $reg2)
88 ; output[first_offset] = reg1
94 STORE_IN_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
97 vst1.16 {$reg1}, [r1]
241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
276 vqrshrn.s32 $reg1, q8, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1,
[all...]
/external/v8/src/full-codegen/
H A Dfull-codegen.h405 void PushOperands(Register reg1, Register reg2);
406 void PushOperands(Register reg1, Register reg2, Register reg3);
407 void PushOperands(Register reg1, Register reg2, Register reg3, Register reg4);
408 void PopOperands(Register reg1, Register reg2);

Completed in 980 milliseconds

123