Searched refs:rn (Results 1 - 25 of 79) sorted by relevance

1234

/external/clang/test/CodeGen/
H A Darm-asm-variable.c27 register unsigned int rn asm("r14");
31 asm volatile ("sub %1, %1, #32" : "=r"(d) : "r"(rn));
/external/mesa3d/src/mapi/glapi/gen/
H A Dnext_available_offset.sh36 sort -rn |\
/external/valgrind/none/tests/arm/
H A Dv6media.stdout.exp2 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3 mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
4 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
5 mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
6 mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
7 mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
12 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn
[all...]
H A Dv6intARM.stdout.exp25 adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
26 adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x00000000
27 adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000
28 adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000
29 adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x80000000 N
30 adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, carryin 0, cpsr 0x60000000 ZC
31 adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x90000000 N V
32 adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, carryin 0, cpsr 0x30000000 CV
33 adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, carryin 0, cpsr 0x80000000 N
35 adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn
[all...]
H A Dv6intThumb.stdout.exp2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
11 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn
[all...]
/external/v8/src/arm64/
H A Dmacro-assembler-arm64-inl.h47 const Register& rn,
51 LogicalMacro(rd, rn, operand, AND);
56 const Register& rn,
60 LogicalMacro(rd, rn, operand, ANDS);
64 void MacroAssembler::Tst(const Register& rn, argument
67 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS); local
72 const Register& rn,
76 LogicalMacro(rd, rn, operand, BIC);
81 const Register& rn,
46 And(const Register& rd, const Register& rn, const Operand& operand) argument
55 Ands(const Register& rd, const Register& rn, const Operand& operand) argument
71 Bic(const Register& rd, const Register& rn, const Operand& operand) argument
80 Bics(const Register& rd, const Register& rn, const Operand& operand) argument
89 Orr(const Register& rd, const Register& rn, const Operand& operand) argument
98 Orn(const Register& rd, const Register& rn, const Operand& operand) argument
107 Eor(const Register& rd, const Register& rn, const Operand& operand) argument
116 Eon(const Register& rd, const Register& rn, const Operand& operand) argument
125 Ccmp(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
138 Ccmn(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
151 Add(const Register& rd, const Register& rn, const Operand& operand) argument
163 Adds(const Register& rd, const Register& rn, const Operand& operand) argument
176 Sub(const Register& rd, const Register& rn, const Operand& operand) argument
189 Subs(const Register& rd, const Register& rn, const Operand& operand) argument
202 Cmn(const Register& rn, const Operand& operand) argument
204 Adds(AppropriateZeroRegFor(rn), rn, operand); local
208 Cmp(const Register& rn, const Operand& operand) argument
210 Subs(AppropriateZeroRegFor(rn), rn, operand); local
233 Adc(const Register& rd, const Register& rn, const Operand& operand) argument
242 Adcs(const Register& rd, const Register& rn, const Operand& operand) argument
251 Sbc(const Register& rd, const Register& rn, const Operand& operand) argument
260 Sbcs(const Register& rd, const Register& rn, const Operand& operand) argument
329 Asr(const Register& rd, const Register& rn, unsigned shift) argument
338 Asr(const Register& rd, const Register& rn, const Register& rm) argument
359 Bfi(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
369 Bfxil(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
411 Cinc(const Register& rd, const Register& rn, Condition cond) argument
421 Cinv(const Register& rd, const Register& rn, Condition cond) argument
431 Cls(const Register& rd, const Register& rn) argument
438 Clz(const Register& rd, const Register& rn) argument
445 Cneg(const Register& rd, const Register& rn, Condition cond) argument
468 CmovX(const Register& rd, const Register& rn, Condition cond) argument
497 Csinc(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
508 Csinv(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
519 Csneg(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
548 Extr(const Register& rd, const Register& rn, const Register& rm, unsigned lsb) argument
732 Fmov(FPRegister fd, Register rn) argument
901 Lsl(const Register& rd, const Register& rn, unsigned shift) argument
910 Lsl(const Register& rd, const Register& rn, const Register& rm) argument
919 Lsr(const Register& rd, const Register& rn, unsigned shift) argument
928 Lsr(const Register& rd, const Register& rn, const Register& rm) argument
937 Madd(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
947 Mneg(const Register& rd, const Register& rn, const Register& rm) argument
956 Mov(const Register& rd, const Register& rn) argument
988 Msub(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
998 Mul(const Register& rd, const Register& rn, const Register& rm) argument
1007 Rbit(const Register& rd, const Register& rn) argument
1022 Rev(const Register& rd, const Register& rn) argument
1029 Rev16(const Register& rd, const Register& rn) argument
1036 Rev32(const Register& rd, const Register& rn) argument
1052 Ror(const Register& rd, const Register& rn, const Register& rm) argument
1061 Sbfiz(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
1071 Sbfx(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
1081 Scvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
1089 Sdiv(const Register& rd, const Register& rn, const Register& rm) argument
1098 Smaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1108 Smsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1118 Smull(const Register& rd, const Register& rn, const Register& rm) argument
1127 Smulh(const Register& rd, const Register& rn, const Register& rm) argument
1136 Umull(const Register& rd, const Register& rn, const Register& rm) argument
1144 Sxtb(const Register& rd, const Register& rn) argument
1151 Sxth(const Register& rd, const Register& rn) argument
1158 Sxtw(const Register& rd, const Register& rn) argument
1165 Ubfiz(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
1175 Ubfx(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
1185 Ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
1193 Udiv(const Register& rd, const Register& rn, const Register& rm) argument
1202 Umaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1212 Umsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1222 Uxtb(const Register& rd, const Register& rn) argument
1229 Uxth(const Register& rd, const Register& rn) argument
1236 Uxtw(const Register& rd, const Register& rn) argument
[all...]
H A Dassembler-arm64.cc1091 const Register& rn,
1093 AddSub(rd, rn, operand, LeaveFlags, ADD);
1098 const Register& rn,
1100 AddSub(rd, rn, operand, SetFlags, ADD);
1104 void Assembler::cmn(const Register& rn, argument
1106 Register zr = AppropriateZeroRegFor(rn);
1107 adds(zr, rn, operand);
1112 const Register& rn,
1114 AddSub(rd, rn, operand, LeaveFlags, SUB);
1119 const Register& rn,
1090 add(const Register& rd, const Register& rn, const Operand& operand) argument
1097 adds(const Register& rd, const Register& rn, const Operand& operand) argument
1111 sub(const Register& rd, const Register& rn, const Operand& operand) argument
1118 subs(const Register& rd, const Register& rn, const Operand& operand) argument
1125 cmp(const Register& rn, const Operand& operand) argument
1143 adc(const Register& rd, const Register& rn, const Operand& operand) argument
1150 adcs(const Register& rd, const Register& rn, const Operand& operand) argument
1157 sbc(const Register& rd, const Register& rn, const Operand& operand) argument
1164 sbcs(const Register& rd, const Register& rn, const Operand& operand) argument
1184 and_(const Register& rd, const Register& rn, const Operand& operand) argument
1191 ands(const Register& rd, const Register& rn, const Operand& operand) argument
1198 tst(const Register& rn, const Operand& operand) argument
1200 ands(AppropriateZeroRegFor(rn), rn, operand); local
1204 bic(const Register& rd, const Register& rn, const Operand& operand) argument
1211 bics(const Register& rd, const Register& rn, const Operand& operand) argument
1218 orr(const Register& rd, const Register& rn, const Operand& operand) argument
1225 orn(const Register& rd, const Register& rn, const Operand& operand) argument
1232 eor(const Register& rd, const Register& rn, const Operand& operand) argument
1239 eon(const Register& rd, const Register& rn, const Operand& operand) argument
1246 lslv(const Register& rd, const Register& rn, const Register& rm) argument
1255 lsrv(const Register& rd, const Register& rn, const Register& rm) argument
1264 asrv(const Register& rd, const Register& rn, const Register& rm) argument
1273 rorv(const Register& rd, const Register& rn, const Register& rm) argument
1283 bfm(const Register& rd, const Register& rn, int immr, int imms) argument
1294 sbfm(const Register& rd, const Register& rn, int immr, int imms) argument
1305 ubfm(const Register& rd, const Register& rn, int immr, int imms) argument
1316 extr(const Register& rd, const Register& rn, const Register& rm, int lsb) argument
1326 csel(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
1334 csinc(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
1342 csinv(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
1350 csneg(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
1372 cinc(const Register &rd, const Register &rn, Condition cond) argument
1378 cinv(const Register &rd, const Register &rn, Condition cond) argument
1384 cneg(const Register &rd, const Register &rn, Condition cond) argument
1390 ConditionalSelect(const Register& rd, const Register& rn, const Register& rm, Condition cond, ConditionalSelectOp op) argument
1401 ccmn(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
1409 ccmp(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
1417 DataProcessing3Source(const Register& rd, const Register& rn, const Register& rm, const Register& ra, DataProcessing3SourceOp op) argument
1426 mul(const Register& rd, const Register& rn, const Register& rm) argument
1435 madd(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1444 mneg(const Register& rd, const Register& rn, const Register& rm) argument
1453 msub(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1462 smaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1472 smsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1482 umaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1492 umsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1502 smull(const Register& rd, const Register& rn, const Register& rm) argument
1511 smulh(const Register& rd, const Register& rn, const Register& rm) argument
1519 sdiv(const Register& rd, const Register& rn, const Register& rm) argument
1528 udiv(const Register& rd, const Register& rn, const Register& rm) argument
1537 rbit(const Register& rd, const Register& rn) argument
1543 rev16(const Register& rd, const Register& rn) argument
1549 rev32(const Register& rd, const Register& rn) argument
1556 rev(const Register& rd, const Register& rn) argument
1562 clz(const Register& rd, const Register& rn) argument
1568 cls(const Register& rd, const Register& rn) argument
1694 ldar(const Register& rt, const Register& rn) argument
1700 ldaxr(const Register& rt, const Register& rn) argument
1706 stlr(const Register& rt, const Register& rn) argument
1712 stlxr(const Register& rs, const Register& rt, const Register& rn) argument
1720 ldarb(const Register& rt, const Register& rn) argument
1726 ldaxrb(const Register& rt, const Register& rn) argument
1732 stlrb(const Register& rt, const Register& rn) argument
1738 stlxrb(const Register& rs, const Register& rt, const Register& rn) argument
1746 ldarh(const Register& rt, const Register& rn) argument
1752 ldaxrh(const Register& rt, const Register& rn) argument
1758 stlrh(const Register& rt, const Register& rn) argument
1764 stlxrh(const Register& rs, const Register& rt, const Register& rn) argument
1842 fmov(FPRegister fd, Register rn) argument
2096 scvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
2108 ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
2245 AddSub(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, AddSubOp op) argument
2283 AddSubWithCarry(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, AddSubWithCarryOp op) argument
2353 Logical(const Register& rd, const Register& rn, const Operand& operand, LogicalOp op) argument
2390 LogicalImmediate(const Register& rd, const Register& rn, unsigned n, unsigned imm_s, unsigned imm_r, LogicalOp op) argument
2404 ConditionalCompare(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond, ConditionalCompareOp op) argument
2424 DataProcessing1Source(const Register& rd, const Register& rn, DataProcessing1SourceOp op) argument
2459 EmitShift(const Register& rd, const Register& rn, Shift shift, unsigned shift_amount) argument
2482 EmitExtendShift(const Register& rd, const Register& rn, Extend extend, unsigned left_shift) argument
2519 DataProcShiftedRegister(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, Instr op) argument
2533 DataProcExtendedRegister(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, Instr op) argument
[all...]
H A Dassembler-arm64.h1019 const Register& rn,
1024 const Register& rn,
1028 void cmn(const Register& rn, const Operand& operand);
1032 const Register& rn,
1037 const Register& rn,
1041 void cmp(const Register& rn, const Operand& operand);
1053 const Register& rn,
1058 const Register& rn,
1063 const Register& rn,
1068 const Register& rn,
1139 bfi(const Register& rd, const Register& rn, int lsb, int width) argument
1146 bfxil(const Register& rd, const Register& rn, int lsb, int width) argument
1154 asr(const Register& rd, const Register& rn, int shift) argument
1167 sbfx(const Register& rd, const Register& rn, int lsb, int width) argument
1174 sxtb(const Register& rd, const Register& rn) argument
1179 sxth(const Register& rd, const Register& rn) argument
1184 sxtw(const Register& rd, const Register& rn) argument
1190 lsl(const Register& rd, const Register& rn, int shift) argument
[all...]
H A Dmacro-assembler-arm64.h175 const Register& rn,
178 const Register& rn,
181 const Register& rn,
184 const Register& rn,
187 const Register& rn,
190 const Register& rn,
193 const Register& rn,
196 const Register& rn,
198 inline void Tst(const Register& rn, const Operand& operand);
200 const Register& rn,
[all...]
/external/vixl/src/vixl/a64/
H A Dsimulator-a64.cc1297 unsigned rn = instr->Rn(); local
1309 uint64_t address = reg<uint64_t>(rn, Reg31IsStackPointer);
1320 if ((rn == 31) && (AlignDown(address, 16) != address)) {
1653 int32_t rn = wreg(instr->Rn()); local
1655 if ((rn == kWMinInt) && (rm == -1)) {
1661 result = rn / rm;
1666 int64_t rn = xreg(instr->Rn()); local
1668 if ((rn == kXMinInt) && (rm == -1)) {
1674 result = rn / rm;
1679 uint32_t rn local
1690 uint64_t rn = static_cast<uint64_t>(xreg(instr->Rn())); local
2165 SimVRegister& rn = vreg(instr->Rn()); local
2213 SimVRegister& rn = vreg(instr->Rn()); local
2437 SimVRegister& rn = vreg(instr->Rn()); local
2571 SimVRegister& rn = vreg(instr->Rn()); local
2695 SimVRegister& rn = vreg(instr->Rn()); local
2761 SimVRegister& rn = vreg(instr->Rn()); local
2799 SimVRegister& rn = vreg(instr->Rn()); local
2905 SimVRegister& rn = vreg(instr->Rn()); local
2941 SimVRegister& rn = vreg(instr->Rn()); local
3404 SimVRegister& rn = vreg(instr->Rn()); local
3474 SimVRegister& rn = vreg(instr->Rn()); local
3491 SimVRegister& rn = vreg(instr->Rn()); local
3566 SimVRegister& rn = vreg(instr->Rn()); local
3612 SimVRegister& rn = vreg(instr->Rn()); local
3630 SimVRegister& rn = vreg(instr->Rn()); local
3646 SimVRegister& rn = vreg(instr->Rn()); local
3698 SimVRegister& rn = vreg(instr->Rn()); local
3827 SimVRegister& rn = vreg(instr->Rn()); local
3853 SimVRegister& rn = vreg(instr->Rn()); local
[all...]
H A Dmacro-assembler-a64.h607 const Register& rn,
610 const Register& rn,
613 const Register& rn,
616 const Register& rn,
619 const Register& rn,
622 const Register& rn,
625 const Register& rn,
628 const Register& rn,
630 void Tst(const Register& rn, const Operand& operand);
632 const Register& rn,
941 Asr(const Register& rd, const Register& rn, unsigned shift) argument
948 Asr(const Register& rd, const Register& rn, const Register& rm) argument
978 Bfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
988 Bfi(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
998 Bfxil(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
1035 Cinc(const Register& rd, const Register& rn, Condition cond) argument
1042 Cinv(const Register& rd, const Register& rn, Condition cond) argument
1054 Cls(const Register& rd, const Register& rn) argument
1061 Clz(const Register& rd, const Register& rn) argument
1068 Cneg(const Register& rd, const Register& rn, Condition cond) argument
1087 Csinc(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
1099 Csinv(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
1111 Csneg(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
1133 Extr(const Register& rd, const Register& rn, const Register& rm, unsigned lsb) argument
1321 Fmov(VRegister vd, Register rn) argument
1327 Fmov(const VRegister& vd, int index, const Register& rn) argument
1562 Lsl(const Register& rd, const Register& rn, unsigned shift) argument
1569 Lsl(const Register& rd, const Register& rn, const Register& rm) argument
1577 Lsr(const Register& rd, const Register& rn, unsigned shift) argument
1584 Lsr(const Register& rd, const Register& rn, const Register& rm) argument
1592 Madd(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1604 Mneg(const Register& rd, const Register& rn, const Register& rm) argument
1612 Mov(const Register& rd, const Register& rn) argument
1650 Msub(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1662 Mul(const Register& rd, const Register& rn, const Register& rm) argument
1675 Rbit(const Register& rd, const Register& rn) argument
1688 Rev(const Register& rd, const Register& rn) argument
1695 Rev16(const Register& rd, const Register& rn) argument
1702 Rev32(const Register& rd, const Register& rn) argument
1716 Ror(const Register& rd, const Register& rn, const Register& rm) argument
1724 Sbfiz(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
1734 Sbfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
1744 Sbfx(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
1754 Scvtf(const VRegister& vd, const Register& rn, int fbits = 0) argument
1760 Sdiv(const Register& rd, const Register& rn, const Register& rm) argument
1768 Smaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1780 Smsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1792 Smull(const Register& rd, const Register& rn, const Register& rm) argument
1899 Sxtb(const Register& rd, const Register& rn) argument
1906 Sxth(const Register& rd, const Register& rn) argument
1913 Sxtw(const Register& rd, const Register& rn) argument
1990 Ubfiz(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
2000 Ubfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
2010 Ubfx(const Register& rd, const Register& rn, unsigned lsb, unsigned width) argument
2020 Ucvtf(const VRegister& vd, const Register& rn, int fbits = 0) argument
2026 Udiv(const Register& rd, const Register& rn, const Register& rm) argument
2034 Umaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
2046 Umull(const Register& rd, const Register& rn, const Register& rm) argument
2064 Umsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
2087 Uxtb(const Register& rd, const Register& rn) argument
2094 Uxth(const Register& rd, const Register& rn) argument
2101 Uxtw(const Register& rd, const Register& rn) argument
2495 Dup(const VRegister& vd, const Register& rn) argument
2517 Ins(const VRegister& vd, int vd_index, const Register& rn) argument
2657 Mov(const VRegister& vd, int vd_index, const Register& rn) argument
2821 Crc32b(const Register& rd, const Register& rn, const Register& rm) argument
2828 Crc32h(const Register& rd, const Register& rn, const Register& rm) argument
2835 Crc32w(const Register& rd, const Register& rn, const Register& rm) argument
2842 Crc32x(const Register& rd, const Register& rn, const Register& rm) argument
2849 Crc32cb(const Register& rd, const Register& rn, const Register& rm) argument
2856 Crc32ch(const Register& rd, const Register& rn, const Register& rm) argument
2863 Crc32cw(const Register& rd, const Register& rn, const Register& rm) argument
2870 Crc32cx(const Register& rd, const Register& rn, const Register& rm) argument
[all...]
H A Dmacro-assembler-a64.cc634 const Register& rn,
637 LogicalMacro(rd, rn, operand, AND);
642 const Register& rn,
645 LogicalMacro(rd, rn, operand, ANDS);
649 void MacroAssembler::Tst(const Register& rn, argument
652 Ands(AppropriateZeroRegFor(rn), rn, operand); local
657 const Register& rn,
660 LogicalMacro(rd, rn, operand, BIC);
665 const Register& rn,
633 And(const Register& rd, const Register& rn, const Operand& operand) argument
641 Ands(const Register& rd, const Register& rn, const Operand& operand) argument
656 Bic(const Register& rd, const Register& rn, const Operand& operand) argument
664 Bics(const Register& rd, const Register& rn, const Operand& operand) argument
672 Orr(const Register& rd, const Register& rn, const Operand& operand) argument
680 Orn(const Register& rd, const Register& rn, const Operand& operand) argument
688 Eor(const Register& rd, const Register& rn, const Operand& operand) argument
696 Eon(const Register& rd, const Register& rn, const Operand& operand) argument
704 LogicalMacro(const Register& rd, const Register& rn, const Operand& operand, LogicalOp op) argument
1059 Ccmp(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
1072 Ccmn(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
1085 ConditionalCompareMacro(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond, ConditionalCompareOp op) argument
1112 Csel(const Register& rd, const Register& rn, const Operand& operand, Condition cond) argument
1155 Add(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S) argument
1169 Adds(const Register& rd, const Register& rn, const Operand& operand) argument
1176 Sub(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S) argument
1190 Subs(const Register& rd, const Register& rn, const Operand& operand) argument
1197 Cmn(const Register& rn, const Operand& operand) argument
1199 Adds(AppropriateZeroRegFor(rn), rn, operand); local
1203 Cmp(const Register& rn, const Operand& operand) argument
1205 Subs(AppropriateZeroRegFor(rn), rn, operand); local
1377 AddSubMacro(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, AddSubOp op) argument
1412 Adc(const Register& rd, const Register& rn, const Operand& operand) argument
1420 Adcs(const Register& rd, const Register& rn, const Operand& operand) argument
1428 Sbc(const Register& rd, const Register& rn, const Operand& operand) argument
1436 Sbcs(const Register& rd, const Register& rn, const Operand& operand) argument
1460 AddSubWithCarryMacro(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, AddSubWithCarryOp op) argument
[all...]
H A Dassembler-a64.cc895 const Register& rn,
897 AddSub(rd, rn, operand, LeaveFlags, ADD);
902 const Register& rn,
904 AddSub(rd, rn, operand, SetFlags, ADD);
908 void Assembler::cmn(const Register& rn,
910 Register zr = AppropriateZeroRegFor(rn);
911 adds(zr, rn, operand);
916 const Register& rn,
918 AddSub(rd, rn, operand, LeaveFlags, SUB);
923 const Register& rn,
[all...]
H A Dassembler-a64.h1312 const Register& rn,
1317 const Register& rn,
1321 void cmn(const Register& rn, const Operand& operand);
1325 const Register& rn,
1330 const Register& rn,
1334 void cmp(const Register& rn, const Operand& operand);
1346 const Register& rn,
1351 const Register& rn,
1356 const Register& rn,
1361 const Register& rn,
[all...]
/external/ipsec-tools/src/racoon/samples/roadwarrior/client/
H A Dphase1-down.sh11 DEFAULT_GW=`netstat -rn | awk '($1 == "default"){print $2}'`
14 DEFAULT_GW=`netstat -rn | awk '($1 == "0.0.0.0"){print $2}'`
34 if=`netstat -rn|awk '($1 == "default"){print $7}'`
41 if=`netstat -rn|awk '($1 == "0.0.0.0"){print $8}'`
H A Dphase1-up.sh10 DEFAULT_GW=`netstat -rn | awk '($1 == "default"){print $2}'`
13 DEFAULT_GW=`netstat -rn | awk '($1 == "0.0.0.0"){print $2}'`
35 if=`netstat -rn|awk '($1 == "default"){print $7}'`
42 if=`netstat -rn|awk '($1 == "0.0.0.0"){print $8}'`
/external/valgrind/none/tests/arm64/
H A Dinteger.stdout.exp2 add x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
3 add w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
4 adc x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
5 adc x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C
6 adc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 00000000
7 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 20000000 C
8 adc x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 00000000
9 adc x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 20000000 C
10 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000
11 adc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 000000000000000
[all...]
/external/strace/tests/
H A Dnet-yy.test42 child="$(sed -rn '/SIGCHLD/ s/^.*, si_pid=([1-9][0-9]*), .*/\1/p' "$LOG")"
47 sed -rn "/^$child"' /!d; / socket\(/,$ s/^[0-9]+ +[^ ]+ (.+)/\1/p' "$LOG" > "$LOG"-connect &&
48 sed -rn "/^$child"' /d; /SIGCHLD/d; / socket\(/,$ s/^[0-9]+ +[^ ]+ (.+)/\1/p' "$LOG" > "$LOG"-accept ||
H A Dunix-yy.test45 child="$(sed -rn '/SIGCHLD/ s/^.*, si_pid=([1-9][0-9]*), .*/\1/p' "$LOG")"
50 sed -rn "/^$child"' /!d; / socket\(/,$ s/^[0-9]+ +[^ ]+ (.+)/\1/p' "$LOG" > "$LOG"-connect &&
51 sed -rn "/^$child"' /d; /SIGCHLD/d; / socket\(/,$ s/^[0-9]+ +[^ ]+ (.+)/\1/p' "$LOG" > "$LOG"-accept ||
/external/v8/src/arm/
H A Ddisasm-arm.cc303 if (format[1] == 'n') { // 'rn: Rn register
733 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
740 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
746 Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
756 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
764 Format(instr, "ldrex'cond 'rt, ['rn]");
767 Format(instr, "ldrexb'cond 'rt, ['rn]");
770 Format(instr, "ldrexh'cond 'rt, ['rn]");
778 // The instruction is documented as strex rd, rt, [rn], but the
782 Format(instr, "strex'cond 'rd, 'rm, ['rn]");
[all...]
/external/jemalloc/test/include/test/
H A Dmath.h56 double acu, factor, oflo, gin, term, rn, a, b, an, dif; local
75 rn = p;
78 rn += 1.0;
79 term *= x / rn;
105 rn = pn[4] / pn[5];
106 dif = fabs(gin - rn);
107 if (dif <= acu && dif <= acu * rn) {
111 gin = rn;
/external/vixl/examples/
H A Dnon-const-visitor.h41 int rn = instr->Rn(); local
48 // Switch the bitfields for the `rn` and `rm` registers.
50 instr_bits |= (rn << Rm_offset) | (rm << Rn_offset);
/external/strace/qemu_multiarch_testing/
H A Dmake-hdc-img.sh20 size=$(du -ks hdc.dir | sed -rn 's/^([0-9]+).*/\1/p')
/external/icu/icu4c/source/i18n/
H A Duspoof_wsconf.cpp319 for (int32_t rn=0; rn<ignoreSet.getRangeCount(); rn++) {
320 UChar32 rangeStart = ignoreSet.getRangeStart(rn);
321 UChar32 rangeEnd = ignoreSet.getRangeEnd(rn);
/external/ltrace/sysdeps/linux-gnu/arm/
H A Dtrace.c336 enum arm_register rn = BITS(this_instr, 16, 19); local
338 if (arm_get_register(proc, rn, &rn_val) < 0)
491 const enum arm_register rn = BITS(inst1, 0, 3); local
515 if (arm_get_register(proc, rn, &addr) < 0)
527 const enum arm_register rn = BITS(inst2, 0, 3); local
529 if (arm_get_register(proc, rn, &next) < 0)
536 const enum arm_register rn = BITS(inst1, 0, 3); local
538 if (arm_get_register(proc, rn, &base) < 0)
542 if (rn == ARM_REG_PC) {

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