Searched refs:simm (Results 1 - 6 of 6) sorted by relevance

/external/pcre/dist/sljit/
H A DsljitNativeARM_64.c413 static sljit_si load_immediate(struct sljit_compiler *compiler, sljit_si dst, sljit_sw simm) argument
415 sljit_uw imm = (sljit_uw)simm;
422 if (simm >= -0x10000 && simm < 0)
430 bitmask = logical_imm(simm, 16);
435 bitmask = logical_imm(simm, 32);
445 if (simm >= -0x100000000l && simm < 0) {
456 if ((simm & 0xffff) == 0)
458 if ((simm
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/external/valgrind/VEX/priv/
H A Dhost_arm64_defs.h644 Int simm; /* needs to be 0 % 16 and in the range -4095 member in struct:__anon17954::__anon17955::__anon17973
905 extern ARM64Instr* ARM64Instr_AddToSP ( Int simm );
H A Dhost_arm_isel.c777 Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; local
778 if (simm >= -4095 && simm <= 4095) {
781 simm = -simm;
783 return ARMAMode1_RI(reg, simm);
843 Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; local
844 if (simm >= -255 && simm <= 255) {
847 simm
895 Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; local
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H A Dhost_arm64_defs.c970 extern ARM64Instr* ARM64Instr_AddToSP ( Int simm ) {
973 i->ARM64in.AddToSP.simm = simm;
974 vassert(-4096 < simm && simm < 4096);
975 vassert(0 == (simm & 0xF));
1524 Int simm = i->ARM64in.AddToSP.simm; local
1525 vex_printf("%s xsp, xsp, #%d", simm < 0 ? "sub" : "add",
1526 simm <
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H A Dhost_arm64_isel.c873 Long simm = (Long)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64; local
874 if (simm >= -255 && simm <= 255) {
876 simm >= -256 && simm <= 255
877 we will need to negate simm in the case where the op is Sub64.
881 if (e->Iex.Binop.op == Iop_Sub64) simm = -simm;
882 return ARM64AMode_RI9(reg, (Int)simm);
H A Dguest_arm64_toIR.c2466 ULong simm = sx_to_64(uimm, 21); local
2469 val = (guest_PC_curr_instr & 0xFFFFFFFFFFFFF000ULL) + (simm << 12);
2471 val = guest_PC_curr_instr + simm;
5535 00 111 100 01 0 imm9 01 n t LDR Bt, [Xn|SP], #simm
5536 01 111 100 01 0 imm9 01 n t LDR Ht, [Xn|SP], #simm
5537 10 111 100 01 0 imm9 01 n t LDR St, [Xn|SP], #simm
5538 11 111 100 01 0 imm9 01 n t LDR Dt, [Xn|SP], #simm
5539 00 111 100 11 0 imm9 01 n t LDR Qt, [Xn|SP], #simm
5542 00 111 100 01 0 imm9 11 n t LDR Bt, [Xn|SP, #simm]!
5543 01 111 100 01 0 imm9 11 n t LDR Ht, [Xn|SP, #simm]!
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