/external/v8/src/compiler/ |
H A D | live-range-separator.cc | 50 DCHECK_NULL(data->live_ranges()[splinter->vreg()]); 51 data->live_ranges()[splinter->vreg()] = splinter; 55 TRACE("creating splinter for range %d between %d and %d\n", range->vreg(), 108 for (size_t vreg = 0; vreg < virt_reg_count; ++vreg) { 109 TopLevelLiveRange *range = data()->live_ranges()[vreg]; 155 int to_remove = range->vreg();
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H A D | register-allocator-verifier.cc | 160 int vreg = unallocated->virtual_register(); local 161 constraint->virtual_register_ = vreg; 163 constraint->type_ = sequence()->IsFP(vreg) ? kFPSlot : kSlot; 169 if (sequence()->IsFP(vreg)) { 189 if (sequence()->IsFP(vreg)) { 196 constraint->type_ = sequence()->IsFP(vreg) ? kFPSlot : kSlot; 534 int vreg = pair.second; local 541 vreg); 547 pending, vreg); 549 new (zone()) FinalAssessment(vreg, pendin [all...] |
H A D | register-allocator.cc | 839 TopLevelLiveRange::TopLevelLiveRange(int vreg, MachineRepresentation rep) argument 841 vreg_(vreg), 857 return IsSplinter() ? splintered_from()->vreg() : vreg(); 1093 TRACE("Shorten live range %d to [%d\n", vreg(), start.value()); 1103 TRACE("Ensure live range %d in interval [%d %d[\n", vreg(), start.value(), 1124 TRACE("Add to live range %d interval [%d %d[\n", vreg(), start.value(), 1151 TRACE("Add to live range %d use position %d\n", vreg(), pos.value()); 1197 os << "Range: " << range->TopLevel()->vreg() << ":" << range->relative_id() 1324 os << range->vreg() << " "; 1429 int vreg = virtual_register_count_++; local 1439 int vreg = GetNextLiveRangeId(); local 2103 int vreg = unalloc->virtual_register(); local 3516 int vreg = iterator.Current(); local [all...] |
H A D | register-allocator-verifier.h | 213 void AddDelayedAssessment(InstructionOperand op, int vreg) { argument 216 map_.insert(std::make_pair(op, vreg)); 218 CHECK_EQ(it->second, vreg);
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H A D | graph-visualizer.cc | 258 void PrintLiveRange(const LiveRange* range, const char* type, int vreg); 547 int vreg = range->vreg(); local 550 PrintLiveRange(child, type, vreg); 555 int vreg) { 558 os_ << vreg << ":" << range->relative_id() << " " << type; 592 os_ << " " << vreg; local 554 PrintLiveRange(const LiveRange* range, const char* type, int vreg) argument
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H A D | instruction.cc | 688 int vreg = (output->IsConstant()) local 691 CHECK(!definitions.Contains(vreg)); 692 definitions.Add(vreg);
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H A D | register-allocator.h | 477 explicit TopLevelLiveRange(int vreg, MachineRepresentation rep); 581 int vreg() const { return vreg_; } function in class:v8::internal::compiler::final 812 return code()->IsReference(top_range->vreg());
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/external/v8/test/unittests/compiler/ |
H A D | instruction-sequence-unittest.h | 51 TestOperand(TestOperandType type, VReg vreg, int value = kNoValue) argument 52 : type_(type), vreg_(vreg), value_(value) {} 66 static TestOperand Reg(VReg vreg, int index = kNoValue) { argument 69 return TestOperand(type, vreg, index); 74 static TestOperand Slot(VReg vreg, int index = kNoValue) { argument 77 return TestOperand(type, vreg, index); 87 static TestOperand Use(VReg vreg) { return TestOperand(kNone, vreg); } argument 91 static TestOperand Unique(VReg vreg) { return TestOperand(kUnique, vreg); } argument 93 UniqueReg(VReg vreg) argument 143 Return(VReg vreg) argument [all...] |
H A D | instruction-sequence-unittest.cc | 150 VReg vreg = NewReg(); local 151 InstructionOperand outputs[1]{ConvertOutputOp(vreg, output_op)}; 153 return vreg; 194 VReg vreg) { 195 CHECK(vreg.value_ != kNoValue); 196 phi->SetInput(input, vreg.value_); 202 VReg vreg = NewReg(); local 203 sequence()->AddConstant(vreg.value_, Constant(imm)); 204 InstructionOperand outputs[1]{ConstantOperand(vreg.value_)}; 206 return vreg; 193 SetInput(PhiInstruction* phi, size_t input, VReg vreg) argument 401 ConvertOutputOp(VReg vreg, TestOperand op) argument [all...] |
H A D | live-range-unittest.cc | 435 TopLevelLiveRange* vreg = TestRangeBuilder(zone()).Id(2).Build(0, 100); local 436 EXPECT_EQ(2, vreg->vreg()); 437 EXPECT_EQ(0, vreg->relative_id()); 441 vreg->SetSplinter(splinter); 442 vreg->Splinter(LifetimePosition::FromInt(4), LifetimePosition::FromInt(12), 445 EXPECT_EQ(101, splinter->vreg()); 448 LiveRange* child = vreg->SplitAt(LifetimePosition::FromInt(50), zone()); 458 vreg->Merge(splinter, zone());
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H A D | instruction-selector-unittest.cc | 76 int vreg = ConstantOperand::cast(output)->virtual_register(); local 77 s.constants_.insert(std::make_pair(vreg, sequence.GetConstant(vreg)));
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/external/valgrind/VEX/priv/ |
H A D | host_generic_reg_alloc2.c | 109 vreg. Is safely left at False, and becomes True after a 115 Bound /* in use (holding value of some vreg) */ 118 /* If .disp == Bound, what vreg is it bound to? */ 119 HReg vreg; member in struct:__anon18111 125 (vreg_state) from vreg numbers back to entries in rreg_state. It 127 hregNumber(rreg_state[j].vreg) == i -- that is, the two entries 129 which involve looking for a particular vreg: there is no need to 131 vreg_state. The FAQ "does this vreg already have an associated 134 To indicate, in vreg_state[i], that a given vreg is not currently 149 finding the vreg whic 604 HReg vreg = reg_usage_arr[ii].vRegs[j]; local 1283 HReg vreg = reg_usage_arr[ii].vRegs[j]; local 1336 HReg vreg = reg_usage_arr[ii].vRegs[j]; local [all...] |
/external/v8/test/cctest/compiler/ |
H A D | test-instruction.cc | 84 UnallocatedOperand Unallocated(int vreg) { argument 85 return UnallocatedOperand(UnallocatedOperand::ANY, vreg); 281 int vreg = 15; local 283 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), 284 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), 285 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), 286 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg)}; 289 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), 290 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), 291 UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg), [all...] |
/external/vixl/src/vixl/a64/ |
H A D | simulator-a64.cc | 652 (lane_size_in_bytes == kSRegSizeInBytes) ? vreg(code).Get<float>(lane) 653 : vreg(code).Get<double>(lane); 1996 LogicVRegister(vreg(dst)).SetUint(kFormatD, 1, xreg(src)); 1999 set_xreg(dst, LogicVRegister(vreg(src)).Uint(kFormatD, 1)); 2164 SimVRegister& rd = vreg(instr->Rd()); 2165 SimVRegister& rn = vreg(instr->Rn()); 2174 case FABS_s: fabs_(kFormatS, vreg(fd), vreg(fn)); return; 2175 case FABS_d: fabs_(kFormatD, vreg(fd), vreg(f [all...] |
H A D | simulator-a64.h | 866 T vreg(unsigned code) const { 877 // Common specialized accessors for the vreg() template. 879 return vreg<int8_t>(code); 883 return vreg<int16_t>(code); 887 return vreg<float>(code); 891 return vreg<uint32_t>(code); 895 return vreg<double>(code); 899 return vreg<uint64_t>(code); 903 return vreg<qreg_t>(code); 909 T vreg(unsigne [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_debug.c | 45 else if( value - c->vreg >= 0 && 46 value - c->vreg < BRW_WM_MAX_VREG) 47 printf("r%ld", (long) (value - c->vreg));
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H A D | brw_wm_pass0.c | 52 memset(&c->vreg[c->nr_vreg], 0, sizeof(*c->vreg)); 53 return &c->vreg[c->nr_vreg++];
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H A D | brw_wm.c | 285 void *vreg = c->vreg; local 290 c->vreg = vreg; 311 c->vreg = rzalloc_array(c, struct brw_wm_value, BRW_WM_MAX_VREG);
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H A D | brw_wm_pass2.c | 242 dst[i] = &c->vreg[c->nr_vreg++];
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/external/v8/src/x64/ |
H A D | assembler-x64-inl.h | 222 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, argument 228 emit_vex3_byte2(w, vreg, l, pp); 231 emit_vex2_byte1(reg, vreg, l, pp); 236 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, argument 240 XMMRegister ivreg = {vreg.code()}; 246 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, argument 252 emit_vex3_byte2(w, vreg, l, pp); 255 emit_vex2_byte1(reg, vreg, l, pp); 260 void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm, argument 264 XMMRegister ivreg = {vreg [all...] |
H A D | assembler-x64.cc | 3973 void Assembler::bmi1q(byte op, Register reg, Register vreg, Register rm) { argument 3976 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1); 3982 void Assembler::bmi1q(byte op, Register reg, Register vreg, const Operand& rm) { argument 3985 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1); 3991 void Assembler::bmi1l(byte op, Register reg, Register vreg, Register rm) { argument 3994 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0); 4000 void Assembler::bmi1l(byte op, Register reg, Register vreg, const Operand& rm) { argument 4003 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0); 4141 void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, argument 4145 emit_vex_prefix(reg, vreg, r 4151 bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, const Operand& rm) argument 4161 bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm) argument 4171 bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, const Operand& rm) argument 4184 Register vreg = {0}; // VEX.vvvv unused local 4196 Register vreg = {0}; // VEX.vvvv unused local 4208 Register vreg = {0}; // VEX.vvvv unused local 4220 Register vreg = {0}; // VEX.vvvv unused local [all...] |
/external/vixl/test/ |
H A D | test-utils-a64.cc | 145 const VRegister& vreg) { 146 VIXL_ASSERT(vreg.Is128Bits()); 148 vec128_t result = core->qreg(vreg.code()); 142 Equal128(uint64_t expected_h, uint64_t expected_l, const RegisterDump* core, const VRegister& vreg) argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 30 /// registers, including vreg register classes, use/def chains for registers, 60 /// Each element in this list contains the register class of the vreg and the 720 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 721 LiveIns.push_back(std::make_pair(Reg, vreg));
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 633 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", "; 639 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg); 961 assert(Op.isReg() && "Non-register vreg operand!"); 963 O << getRegisterName(Reg, AArch64::vreg); 1269 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
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/external/v8/src/ia32/ |
H A D | assembler-ia32.cc | 2793 void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) { argument 2796 emit_vex_prefix(vreg, kLZ, kNone, k0F38, kW0); 2832 void Assembler::bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg, argument 2836 emit_vex_prefix(vreg, kLZ, pp, k0F38, kW0); 2845 Register vreg = {0}; // VEX.vvvv unused local 2847 emit_vex_prefix(vreg, kLZ, kF2, k0F3A, kW0); 2875 void Assembler::emit_vex_prefix(XMMRegister vreg, VectorLength l, SIMDPrefix pp, argument 2881 EMIT(w | ((~vreg.code() & 0xf) << 3) | l | pp); 2884 EMIT(((~vreg.code()) << 3) | l | pp); 2889 void Assembler::emit_vex_prefix(Register vreg, VectorLengt argument [all...] |