Searched refs:Dsrl32 (Results 1 - 4 of 4) sorted by last modified time
| /art/compiler/optimizing/ |
| H A D | code_generator_mips64.cc | 1222 __ Dsrl32(dst, lhs, shift_value);
1907 __ Dsrl32(TMP, dividend, 31);
1913 __ Dsrl32(TMP, TMP, 32 - ctz_imm);
1959 __ Dsrl32(TMP, TMP, 32 - ctz_imm);
1970 __ Dsrl32(out, out, 32 - ctz_imm);
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 392 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) { function in class:art::mips64::Mips64Assembler
1082 Dsrl32(rd, rd, shift_cnt & 31);
1932 Dsrl32(TMP2, reg, 0);
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| H A D | assembler_mips64.h | 177 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
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| H A D | assembler_mips64_test.cc | 950 TEST_F(AssemblerMIPS64Test, Dsrl32) {
951 DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Dsrl32, 5, "dsrl32 ${reg1}, ${reg2}, {imm}"),
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