Searched refs:LoadConst32 (Results 1 - 8 of 8) sorted by relevance
| /art/compiler/optimizing/ |
| H A D | code_generator_mips.cc | 229 __ LoadConst32(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex());
288 __ LoadConst32(calling_convention.GetRegisterAt(0), string_index);
917 __ LoadConst32(dst, value);
963 __ LoadConst32(dst, value);
1099 __ LoadConst32(AT, mirror::Class::kStatusInitialized);
1281 __ LoadConst32(TMP, low);
1290 __ LoadConst32(TMP, high);
1302 __ LoadConst32(TMP, low);
1311 __ LoadConst32(TMP, high);
1321 __ LoadConst32(TM
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| H A D | intrinsics_mips.cc | 285 __ LoadConst32(AT, 0x00FF00FF);
296 __ LoadConst32(AT, 0x0F0F0F0F);
302 __ LoadConst32(AT, 0x33333333);
308 __ LoadConst32(AT, 0x55555555);
344 __ LoadConst32(AT, 0x00FF00FF);
362 __ LoadConst32(AT, 0x0F0F0F0F);
373 __ LoadConst32(AT, 0x33333333);
384 __ LoadConst32(AT, 0x55555555);
542 __ LoadConst32(TMP, 32);
549 __ LoadConst32(TM
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| H A D | code_generator_mips64.cc | 188 __ LoadConst32(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex());
243 __ LoadConst32(calling_convention.GetRegisterAt(0), string_index);
689 __ LoadConst32(gpr, value);
768 __ LoadConst32(gpr, value);
862 __ LoadConst32(location.AsRegister<GpuRegister>(), value);
982 __ LoadConst32(AT, mirror::Class::kStatusInitialized);
1722 __ LoadConst32(rhs, value);
1739 __ LoadConst32(res, 0);
1743 __ LoadConst32(res, -1);
1745 __ LoadConst32(re
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| H A D | intrinsics_mips64.cc | 1496 __ LoadConst32(tmp_reg, std::numeric_limits<uint16_t>::max());
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 1359 void MipsAssembler::LoadConst32(Register rd, int32_t value) { function in class:art::mips::MipsAssembler
1376 LoadConst32(reg_lo, low);
1378 LoadConst32(reg_hi, high);
1390 LoadConst32(AT, offset);
1398 LoadConst32(temp, value);
1410 LoadConst32(AT, offset);
1420 LoadConst32(temp, low);
1427 LoadConst32(temp, high);
1437 LoadConst32(temp, value);
1448 LoadConst32(tem
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| H A D | assembler_mips.h | 356 void LoadConst32(Register rd, int32_t value);
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 1035 void Mips64Assembler::LoadConst32(GpuRegister rd, int32_t value) { function in class:art::mips64::Mips64Assembler
1808 LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1));
1853 LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1));
1911 LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1));
1948 LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1));
2108 LoadConst32(scratch.AsGpuRegister(), imm);
2347 LoadConst32(out_reg.AsGpuRegister(), 0);
2388 LoadConst32(out_reg.AsGpuRegister(), 0);
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| H A D | assembler_mips64.h | 324 void LoadConst32(GpuRegister rd, int32_t value);
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