Searched refs:LoadFromOffset (Results 1 - 23 of 23) sorted by last modified time

/art/compiler/linker/arm/
H A Drelative_patcher_thumb2.cc85 assembler.LoadFromOffset(
/art/compiler/optimizing/
H A Dcode_generator_arm.cc477 // __ LoadFromOffset(kLoadWord, out, out, offset);
748 __ LoadFromOffset(kLoadWord, static_cast<Register>(reg_id), SP, stack_index);
910 __ LoadFromOffset(kLoadWord, IP, IP, 0);
1077 __ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), SP, source.GetStackIndex());
1095 __ LoadFromOffset(kLoadWord, IP, SP, source.GetStackIndex());
1123 __ LoadFromOffset(kLoadWordPair, destination.AsRegisterPairLow<Register>(),
1204 __ LoadFromOffset(kLoadWord, LR, TR, entry_point_offset);
1883 __ LoadFromOffset(kLoadWord, temp, SP, receiver.GetStackIndex());
1885 __ LoadFromOffset(kLoadWord, temp, temp, class_offset);
1888 __ LoadFromOffset(kLoadWor
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H A Dcode_generator_mips.cc611 __ LoadFromOffset(kLoadWord, reg, SP, offset);
624 __ LoadFromOffset(kLoadWord, reg_l, SP, offset_l);
627 __ LoadFromOffset(kLoadWord, reg_h, SP, offset_h);
650 __ LoadFromOffset(kLoadWord,
654 __ LoadFromOffset(kLoadWord,
678 __ LoadFromOffset(kLoadWord,
835 __ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), SP, source.GetStackIndex());
854 __ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex());
879 __ LoadFromOffset(kLoadDoubleword, r, SP, off);
903 __ LoadFromOffset(kLoadWor
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H A Dcode_generator_mips64.cc495 __ LoadFromOffset(load_type,
499 __ LoadFromOffset(load_type,
524 __ LoadFromOffset(kLoadWord,
673 __ LoadFromOffset(load_type,
784 __ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex());
787 __ LoadFromOffset(kLoadDoubleword, TMP, SP, source.GetStackIndex());
835 __ LoadFromOffset(load_type, TMP, SP, mem_loc.GetStackIndex());
882 __ LoadFromOffset(kLoadDoubleword,
935 __ LoadFromOffset(kLoadDoubleword, GpuRegister(reg_id), SP, stack_index);
973 __ LoadFromOffset(kLoadDoublewor
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H A Dintrinsics_arm.cc494 __ LoadFromOffset(kLoadWord,
1011 __ LoadFromOffset(
1152 __ LoadFromOffset(kLoadWord, LR, TR,
1225 __ LoadFromOffset(
1253 __ LoadFromOffset(
1279 __ LoadFromOffset(kLoadWord,
1325 __ LoadFromOffset(kLoadWord, temp, input, length_offset);
1335 __ LoadFromOffset(kLoadWord, input_len, input, length_offset);
1358 __ LoadFromOffset(kLoadWord, temp, input, length_offset);
1485 __ LoadFromOffset(kLoadWor
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H A Dintrinsics_mips.cc1471 __ LoadFromOffset(kLoadWord,
1947 __ LoadFromOffset(kLoadWord,
2106 __ LoadFromOffset(kLoadWord,
2192 __ LoadFromOffset(kLoadWord,
2225 __ LoadFromOffset(kLoadWord,
2254 __ LoadFromOffset(kLoadWord,
H A Dintrinsics_mips64.cc917 __ LoadFromOffset(kLoadUnsignedWord,
1358 __ LoadFromOffset(kLoadDoubleword,
1508 __ LoadFromOffset(kLoadDoubleword,
1585 __ LoadFromOffset(kLoadDoubleword,
1619 __ LoadFromOffset(kLoadDoubleword,
1650 __ LoadFromOffset(kLoadDoubleword,
/art/compiler/trampolines/
H A Dtrampoline_compiler.cc58 __ LoadFromOffset(kLoadWord, PC, R0, offset.Int32Value());
61 __ LoadFromOffset(kLoadWord, IP, R0, JNIEnvExt::SelfOffset(4).Int32Value());
62 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value());
65 __ LoadFromOffset(kLoadWord, PC, R9, offset.Int32Value());
127 __ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value());
130 __ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset(4).Int32Value());
131 __ LoadFromOffset(kLoadWord, T9, T9, offset.Int32Value());
134 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value());
159 __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value());
162 __ LoadFromOffset(kLoadDoublewor
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/art/compiler/utils/arm/
H A Dassembler_arm.cc526 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value());
533 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value());
541 LoadFromOffset(kLoadWord, dst.AsCoreRegister(),
551 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), SP, src.Int32Value());
558 LoadFromOffset(kLoadWord, dst.AsCoreRegister(),
585 assembler->LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset);
588 assembler->LoadFromOffset(kLoadWord, dst.AsRegisterPairLow(), src_register, src_offset);
589 assembler->LoadFromOffset(kLoadWord, dst.AsRegisterPairHigh(), src_register, src_offset + 4);
609 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), TR, offs.Int32Value());
617 LoadFromOffset(kLoadWor
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H A Dassembler_arm.h782 virtual void LoadFromOffset(LoadOperandType type,
H A Dassembler_arm32.cc1467 void Arm32Assembler::LoadFromOffset(LoadOperandType type, function in class:art::arm::Arm32Assembler
H A Dassembler_arm32.h271 void LoadFromOffset(LoadOperandType type,
H A Dassembler_thumb2.cc3647 void Thumb2Assembler::LoadFromOffset(LoadOperandType type, function in class:art::arm::Thumb2Assembler
H A Dassembler_thumb2.h320 void LoadFromOffset(LoadOperandType type,
/art/compiler/utils/arm64/
H A Dassembler_arm64.cc196 LoadFromOffset(scratch.AsXRegister(), SP, in_off.Int32Value());
245 void Arm64Assembler::LoadFromOffset(XRegister dest, XRegister base, function in class:art::arm64::Arm64Assembler
324 LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value());
362 LoadFromOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
371 LoadFromOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value());
394 LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value());
413 LoadFromOffset(scratch.AsXRegister(), base.AsXRegister(), src_offset.Int32Value());
432 LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value());
467 LoadFromOffset(scratch.AsXRegister(), src.AsXRegister(), src_offset.Int32Value());
520 LoadFromOffset(scratc
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H A Dassembler_arm64.h267 void LoadFromOffset(XRegister dest, XRegister base, int32_t offset);
/art/compiler/utils/
H A Dassembler_thumb_test.cc838 TEST_F(Thumb2AssemblerTest, LoadFromOffset) {
839 __ LoadFromOffset(kLoadWord, R2, R4, 12);
840 __ LoadFromOffset(kLoadWord, R2, R4, 0xfff);
841 __ LoadFromOffset(kLoadWord, R2, R4, 0x1000);
842 __ LoadFromOffset(kLoadWord, R2, R4, 0x1000a4);
843 __ LoadFromOffset(kLoadWord, R2, R4, 0x101000);
844 __ LoadFromOffset(kLoadWord, R4, R4, 0x101000);
845 __ LoadFromOffset(kLoadUnsignedHalfword, R2, R4, 12);
846 __ LoadFromOffset(kLoadUnsignedHalfword, R2, R4, 0xfff);
847 __ LoadFromOffset(kLoadUnsignedHalfwor
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/art/compiler/utils/mips/
H A Dassembler_mips.cc2265 void MipsAssembler::LoadFromOffset(LoadOperandType type, Register reg, Register base, function in class:art::mips::MipsAssembler
2352 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset);
2355 LoadFromOffset(kLoadDoubleword, dst.AsRegisterPairLow(), src_register, src_offset);
2494 LoadFromOffset(kLoadWord, reg, SP, stack_offset);
2498 LoadFromOffset(kLoadWord, RA, SP, stack_offset);
2601 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value());
2617 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), SP, src.Int32Value());
2624 LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
2634 LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
2642 LoadFromOffset(kLoadWor
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H A Dassembler_mips.h388 void LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset);
H A Dassembler_mips_test.cc726 TEST_F(AssemblerMIPSTest, LoadFromOffset) {
727 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A0, 0);
728 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 0);
729 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 256);
730 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 1000);
731 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 0x8000);
732 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 0x10000);
733 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 0x12345678);
734 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, -256);
735 __ LoadFromOffset(mip
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/art/compiler/utils/mips64/
H A Dassembler_mips64.cc1803 void Mips64Assembler::LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, function in class:art::mips64::Mips64Assembler
1886 LoadFromOffset(kLoadWord, dst.AsGpuRegister(), src_register, src_offset);
1889 LoadFromOffset(kLoadDoubleword, dst.AsGpuRegister(), src_register, src_offset);
2034 LoadFromOffset(kLoadDoubleword, reg, SP, stack_offset);
2038 LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset);
2130 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, in_off.Int32Value());
2147 LoadFromOffset(kLoadUnsignedWord, dest.AsGpuRegister(), SP, src.Int32Value());
2154 LoadFromOffset(kLoadUnsignedWord, dest.AsGpuRegister(),
2169 LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(),
2177 LoadFromOffset(kLoadDoublewor
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H A Dassembler_mips64.h355 void LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
H A Dassembler_mips64_test.cc1007 TEST_F(AssemblerMIPS64Test, LoadFromOffset) {
1008 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A0, 0);
1009 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 0);
1010 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 1);
1011 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 256);
1012 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 1000);
1013 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 0x7FFF);
1014 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 0x8000);
1015 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 0x8001);
1016 __ LoadFromOffset(mips6
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