Searched refs:StoreToOffset (Results 1 - 19 of 19) sorted by path

/art/compiler/optimizing/
H A Dcode_generator_arm.cc743 __ StoreToOffset(kStoreWord, static_cast<Register>(reg_id), SP, stack_index);
926 __ StoreToOffset(kStoreWord, kMethodRegisterArgument, SP, 0);
1090 __ StoreToOffset(kStoreWord, source.AsRegister<Register>(), SP, destination.GetStackIndex());
1096 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex());
1144 __ StoreToOffset(kStoreWord, R1, SP, destination.GetStackIndex());
1145 __ StoreToOffset(kStoreWord, R2, SP, destination.GetHighStackIndex(kArmWordSize));
1147 __ StoreToOffset(kStoreWordPair, source.AsRegisterPairLow<Register>(),
3833 __ StoreToOffset(kStoreByte, value.AsRegister<Register>(), base, offset);
3839 __ StoreToOffset(kStoreHalfword, value.AsRegister<Register>(), base, offset);
3853 __ StoreToOffset(kStoreWor
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H A Dcode_generator_mips.cc612 __ StoreToOffset(kStoreWord, TMP, SP, offset);
625 __ StoreToOffset(kStoreWord, TMP, SP, offset_l);
628 __ StoreToOffset(kStoreWord, TMP, SP, offset_h);
658 __ StoreToOffset(kStoreWord,
662 __ StoreToOffset(kStoreWord, TMP, SP, index1 + stack_offset);
849 __ StoreToOffset(kStoreWord, source.AsRegister<Register>(), SP, destination.GetStackIndex());
855 __ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex());
898 __ StoreToOffset(kStoreDoubleword, source.AsRegisterPairLow<Register>(), SP, off);
904 __ StoreToOffset(kStoreWord, TMP, SP, off);
906 __ StoreToOffset(kStoreWor
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H A Dcode_generator_mips64.cc503 __ StoreToOffset(store_type,
507 __ StoreToOffset(store_type, TMP, SP, index1 + stack_offset);
749 __ StoreToOffset(store_type,
778 __ StoreToOffset(store_type, gpr, SP, destination.GetStackIndex());
785 __ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex());
788 __ StoreToOffset(kStoreDoubleword, TMP, SP, destination.GetStackIndex());
848 __ StoreToOffset(store_type, reg_loc.AsRegister<GpuRegister>(), SP, mem_loc.GetStackIndex());
930 __ StoreToOffset(kStoreDoubleword, GpuRegister(reg_id), SP, stack_index);
1474 __ StoreToOffset(kStoreByte, value, obj, offset);
1477 __ StoreToOffset(kStoreByt
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/art/compiler/utils/arm/
H A Dassembler_arm.cc421 StoreToOffset(kStoreWord, R0, SP, 0);
432 StoreToOffset(kStoreWord, reg.AsCoreRegister(), SP, offset);
495 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
498 StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value());
499 StoreToOffset(kStoreWord, src.AsRegisterPairHigh(),
512 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
518 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
525 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
527 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4);
534 StoreToOffset(kStoreWor
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H A Dassembler_arm.h787 virtual void StoreToOffset(StoreOperandType type,
H A Dassembler_arm32.cc1544 void Arm32Assembler::StoreToOffset(StoreOperandType type, function in class:art::arm::Arm32Assembler
H A Dassembler_arm32.h276 void StoreToOffset(StoreOperandType type,
H A Dassembler_thumb2.cc3733 void Thumb2Assembler::StoreToOffset(StoreOperandType type, function in class:art::arm::Thumb2Assembler
H A Dassembler_thumb2.h325 void StoreToOffset(StoreOperandType type,
H A Dassembler_thumb2_test.cc287 __ StoreToOffset(type, arm::R0, arm::SP, offset);
288 __ StoreToOffset(type, arm::IP, arm::SP, offset);
289 __ StoreToOffset(type, arm::IP, arm::R5, offset);
303 __ StoreToOffset(type, arm::R0, arm::SP, offset);
304 __ StoreToOffset(type, arm::IP, arm::SP, offset);
305 __ StoreToOffset(type, arm::IP, arm::R5, offset);
313 "str ip, [r5, #4]\n" // StoreToOffset(type, ip, r5, 4100 & 0xfff)
318 "str ip, [r6, #0]\n" // StoreToOffset(type, ip, r6, 4096 & 0xfff)
328 __ StoreToOffset(type, arm::R0, arm::SP, offset);
337 __ StoreToOffset(typ
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/art/compiler/utils/arm64/
H A Dassembler_arm64.cc60 StoreToOffset(TR, SP, offset.Int32Value());
114 void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { function in class:art::arm64::Arm64Assembler
136 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value());
155 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value());
172 StoreToOffset(scratch.AsXRegister(), TR, offs.Int32Value());
181 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
195 StoreToOffset(source.AsXRegister(), SP, dest_off.Int32Value());
197 StoreToOffset(scratch.AsXRegister(), SP, dest_off.Int32Value() + 8);
363 StoreToOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value());
372 StoreToOffset(scratc
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H A Dassembler_arm64.h259 void StoreToOffset(XRegister source, XRegister base, int32_t offset);
/art/compiler/utils/
H A Dassembler_thumb_test.cc868 TEST_F(Thumb2AssemblerTest, StoreToOffset) {
869 __ StoreToOffset(kStoreWord, R2, R4, 12);
870 __ StoreToOffset(kStoreWord, R2, R4, 0xfff);
871 __ StoreToOffset(kStoreWord, R2, R4, 0x1000);
872 __ StoreToOffset(kStoreWord, R2, R4, 0x1000a4);
873 __ StoreToOffset(kStoreWord, R2, R4, 0x101000);
874 __ StoreToOffset(kStoreWord, R4, R4, 0x101000);
875 __ StoreToOffset(kStoreHalfword, R2, R4, 12);
876 __ StoreToOffset(kStoreHalfword, R2, R4, 0xfff);
877 __ StoreToOffset(kStoreHalfwor
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/art/compiler/utils/mips/
H A Dassembler_mips.cc2366 void MipsAssembler::StoreToOffset(StoreOperandType type, Register reg, Register base, function in class:art::mips::MipsAssembler
2452 StoreToOffset(kStoreWord, RA, SP, stack_offset);
2457 StoreToOffset(kStoreWord, reg, SP, stack_offset);
2462 StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0);
2472 StoreToOffset(kStoreWord, reg.AsCoreRegister(), SP, offset);
2537 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
2540 StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value());
2541 StoreToOffset(kStoreWord, src.AsRegisterPairHigh(),
2556 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
2562 StoreToOffset(kStoreWor
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H A Dassembler_mips.h391 void StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset);
H A Dassembler_mips_test.cc1008 TEST_F(AssemblerMIPSTest, StoreToOffset) {
1009 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A0, 0);
1010 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0);
1011 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 256);
1012 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 1000);
1013 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0x8000);
1014 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0x10000);
1015 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0x12345678);
1016 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, -256);
1017 __ StoreToOffset(mip
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/art/compiler/utils/mips64/
H A Dassembler_mips64.cc1906 void Mips64Assembler::StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, function in class:art::mips64::Mips64Assembler
1991 StoreToOffset(kStoreDoubleword, RA, SP, stack_offset);
1996 StoreToOffset(kStoreDoubleword, reg, SP, stack_offset);
2001 StoreToOffset(kStoreDoubleword, method_reg.AsMips64().AsGpuRegister(), SP, 0);
2017 StoreToOffset((size == 4) ? kStoreWord : kStoreDoubleword,
2074 StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value());
2076 StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value());
2095 StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value());
2101 StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value());
2109 StoreToOffset(kStoreWor
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H A Dassembler_mips64.h357 void StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
H A Dassembler_mips64_test.cc1383 TEST_F(AssemblerMIPS64Test, StoreToOffset) {
1384 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A0, 0);
1385 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0);
1386 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 1);
1387 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 256);
1388 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 1000);
1389 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x7FFF);
1390 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x8000);
1391 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x8001);
1392 __ StoreToOffset(mips6
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