Searched refs:rt (Results 1 - 11 of 11) sorted by relevance

/art/runtime/
H A Dreference_table_test.cc35 ReferenceTable rt("test", 0, 11);
40 rt.Dump(oss);
42 EXPECT_EQ(0U, rt.Size());
46 rt.Remove(nullptr);
47 EXPECT_EQ(0U, rt.Size());
50 rt.Remove(o1);
51 EXPECT_EQ(0U, rt.Size());
55 rt.Add(o1);
56 EXPECT_EQ(1U, rt.Size());
58 rt
[all...]
/art/compiler/utils/mips/
H A Dassembler_mips.h124 void Addu(Register rd, Register rs, Register rt);
125 void Addiu(Register rt, Register rs, uint16_t imm16);
126 void Subu(Register rd, Register rs, Register rt);
128 void MultR2(Register rs, Register rt); // R2
129 void MultuR2(Register rs, Register rt); // R2
130 void DivR2(Register rs, Register rt); // R2
131 void DivuR2(Register rs, Register rt); // R2
132 void MulR2(Register rd, Register rs, Register rt); // R2
133 void DivR2(Register rd, Register rs, Register rt); // R2
134 void ModR2(Register rd, Register rs, Register rt); // R
[all...]
H A Dassembler_mips.cc125 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument
127 CHECK_NE(rt, kNoRegister);
131 static_cast<uint32_t>(rt) << kRtShift |
138 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument
140 CHECK_NE(rt, kNoRegister);
143 static_cast<uint32_t>(rt) << kRtShift |
186 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { argument
187 EmitR(0, rs, rt, rd, 0, 0x21);
190 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) { argument
191 EmitI(0x9, rs, rt, imm1
194 Subu(Register rd, Register rs, Register rt) argument
198 MultR2(Register rs, Register rt) argument
203 MultuR2(Register rs, Register rt) argument
208 DivR2(Register rs, Register rt) argument
213 DivuR2(Register rs, Register rt) argument
218 MulR2(Register rd, Register rs, Register rt) argument
223 DivR2(Register rd, Register rs, Register rt) argument
229 ModR2(Register rd, Register rs, Register rt) argument
235 DivuR2(Register rd, Register rs, Register rt) argument
241 ModuR2(Register rd, Register rs, Register rt) argument
247 MulR6(Register rd, Register rs, Register rt) argument
252 MuhR6(Register rd, Register rs, Register rt) argument
257 MuhuR6(Register rd, Register rs, Register rt) argument
262 DivR6(Register rd, Register rs, Register rt) argument
267 ModR6(Register rd, Register rs, Register rt) argument
272 DivuR6(Register rd, Register rs, Register rt) argument
277 ModuR6(Register rd, Register rs, Register rt) argument
282 And(Register rd, Register rs, Register rt) argument
286 Andi(Register rt, Register rs, uint16_t imm16) argument
290 Or(Register rd, Register rs, Register rt) argument
294 Ori(Register rt, Register rs, uint16_t imm16) argument
298 Xor(Register rd, Register rs, Register rt) argument
302 Xori(Register rt, Register rs, uint16_t imm16) argument
306 Nor(Register rd, Register rs, Register rt) argument
310 Movz(Register rd, Register rs, Register rt) argument
315 Movn(Register rd, Register rs, Register rt) argument
320 Seleqz(Register rd, Register rs, Register rt) argument
325 Selnez(Register rd, Register rs, Register rt) argument
350 Seb(Register rd, Register rt) argument
354 Seh(Register rd, Register rt) argument
358 Wsbh(Register rd, Register rt) argument
362 Bitswap(Register rd, Register rt) argument
367 Sll(Register rd, Register rt, int shamt) argument
372 Srl(Register rd, Register rt, int shamt) argument
377 Rotr(Register rd, Register rt, int shamt) argument
382 Sra(Register rd, Register rt, int shamt) argument
387 Sllv(Register rd, Register rt, Register rs) argument
391 Srlv(Register rd, Register rt, Register rs) argument
395 Rotrv(Register rd, Register rt, Register rs) argument
399 Srav(Register rd, Register rt, Register rs) argument
403 Ext(Register rd, Register rt, int pos, int size) argument
410 Ins(Register rd, Register rt, int pos, int size) argument
417 Lb(Register rt, Register rs, uint16_t imm16) argument
421 Lh(Register rt, Register rs, uint16_t imm16) argument
425 Lw(Register rt, Register rs, uint16_t imm16) argument
429 Lwl(Register rt, Register rs, uint16_t imm16) argument
434 Lwr(Register rt, Register rs, uint16_t imm16) argument
439 Lbu(Register rt, Register rs, uint16_t imm16) argument
443 Lhu(Register rt, Register rs, uint16_t imm16) argument
447 Lui(Register rt, uint16_t imm16) argument
466 Sb(Register rt, Register rs, uint16_t imm16) argument
470 Sh(Register rt, Register rs, uint16_t imm16) argument
474 Sw(Register rt, Register rs, uint16_t imm16) argument
478 Swl(Register rt, Register rs, uint16_t imm16) argument
483 Swr(Register rt, Register rs, uint16_t imm16) argument
488 LlR2(Register rt, Register base, int16_t imm16) argument
493 ScR2(Register rt, Register base, int16_t imm16) argument
498 LlR6(Register rt, Register base, int16_t imm9) argument
504 ScR6(Register rt, Register base, int16_t imm9) argument
510 Slt(Register rd, Register rs, Register rt) argument
514 Sltu(Register rd, Register rs, Register rt) argument
518 Slti(Register rt, Register rs, uint16_t imm16) argument
522 Sltiu(Register rt, Register rs, uint16_t imm16) argument
530 Beq(Register rs, Register rt, uint16_t imm16) argument
534 Bne(Register rs, Register rt, uint16_t imm16) argument
538 Beqz(Register rt, uint16_t imm16) argument
542 Bnez(Register rt, uint16_t imm16) argument
546 Bltz(Register rt, uint16_t imm16) argument
550 Bgez(Register rt, uint16_t imm16) argument
554 Blez(Register rt, uint16_t imm16) argument
558 Bgtz(Register rt, uint16_t imm16) argument
622 Jic(Register rt, uint16_t imm16) argument
627 Jialc(Register rt, uint16_t imm16) argument
632 Bltc(Register rs, Register rt, uint16_t imm16) argument
640 Bltzc(Register rt, uint16_t imm16) argument
646 Bgtzc(Register rt, uint16_t imm16) argument
652 Bgec(Register rs, Register rt, uint16_t imm16) argument
660 Bgezc(Register rt, uint16_t imm16) argument
666 Blezc(Register rt, uint16_t imm16) argument
672 Bltuc(Register rs, Register rt, uint16_t imm16) argument
680 Bgeuc(Register rs, Register rt, uint16_t imm16) argument
688 Beqc(Register rs, Register rt, uint16_t imm16) argument
696 Bnec(Register rs, Register rt, uint16_t imm16) argument
726 EmitBcondR2(BranchCondition cond, Register rs, Register rt, uint16_t imm16) argument
780 EmitBcondR6(BranchCondition cond, Register rs, Register rt, uint32_t imm16_21) argument
1272 Mfc1(Register rt, FRegister fs) argument
1276 Mtc1(Register rt, FRegister fs) argument
1280 Mfhc1(Register rt, FRegister fs) argument
1284 Mthc1(Register rt, FRegister fs) argument
1288 MoveFromFpuHigh(Register rt, FRegister fs) argument
1297 MoveToFpuHigh(Register rt, FRegister fs) argument
1353 PopAndReturn(Register rd, Register rt) argument
1459 Addiu32(Register rt, Register rs, int32_t value, Register temp) argument
2163 Beq(Register rs, Register rt, MipsLabel* label) argument
2167 Bne(Register rs, Register rt, MipsLabel* label) argument
2171 Beqz(Register rt, MipsLabel* label) argument
2175 Bnez(Register rt, MipsLabel* label) argument
2179 Bltz(Register rt, MipsLabel* label) argument
2183 Bgez(Register rt, MipsLabel* label) argument
2187 Blez(Register rt, MipsLabel* label) argument
2191 Bgtz(Register rt, MipsLabel* label) argument
2195 Blt(Register rs, Register rt, MipsLabel* label) argument
2205 Bge(Register rs, Register rt, MipsLabel* label) argument
2217 Bltu(Register rs, Register rt, MipsLabel* label) argument
2227 Bgeu(Register rs, Register rt, MipsLabel* label) argument
[all...]
/art/compiler/utils/mips64/
H A Dassembler_mips64.h122 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
123 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
124 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
125 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
126 void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
127 void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
129 void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
130 void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
131 void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
132 void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
[all...]
H A Dassembler_mips64.cc91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, argument
94 CHECK_NE(rt, kNoGpuRegister);
98 static_cast<uint32_t>(rt) << kRtShift |
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, argument
120 CHECK_NE(rt, kNoGpuRegister);
124 static_cast<uint32_t>(rt) << kRtShift |
131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { argument
133 CHECK_NE(rt, kNoGpuRegister);
136 static_cast<uint32_t>(rt) << kRtShift |
179 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { argument
183 Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
187 Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
191 Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
195 Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
199 Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
203 MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
207 MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
211 DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
215 ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
219 DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
223 ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
227 Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
231 Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
235 Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
239 Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
243 Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
247 Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
251 And(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
255 Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
259 Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
263 Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
267 Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
271 Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
275 Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
279 Bitswap(GpuRegister rd, GpuRegister rt) argument
283 Dbitswap(GpuRegister rd, GpuRegister rt) argument
287 Seb(GpuRegister rd, GpuRegister rt) argument
291 Seh(GpuRegister rd, GpuRegister rt) argument
295 Dsbh(GpuRegister rd, GpuRegister rt) argument
299 Dshd(GpuRegister rd, GpuRegister rt) argument
303 Dext(GpuRegister rt, GpuRegister rs, int pos, int size) argument
309 Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) argument
316 Wsbh(GpuRegister rd, GpuRegister rt) argument
320 Sc(GpuRegister rt, GpuRegister base, int16_t imm9) argument
325 Scd(GpuRegister rt, GpuRegister base, int16_t imm9) argument
330 Ll(GpuRegister rt, GpuRegister base, int16_t imm9) argument
335 Lld(GpuRegister rt, GpuRegister base, int16_t imm9) argument
340 Sll(GpuRegister rd, GpuRegister rt, int shamt) argument
344 Srl(GpuRegister rd, GpuRegister rt, int shamt) argument
348 Rotr(GpuRegister rd, GpuRegister rt, int shamt) argument
352 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument
356 Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
360 Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
364 Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
368 Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
372 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument
376 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument
380 Drotr(GpuRegister rd, GpuRegister rt, int shamt) argument
384 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument
388 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument
392 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument
396 Drotr32(GpuRegister rd, GpuRegister rt, int shamt) argument
400 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument
404 Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
408 Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
412 Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
416 Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
420 Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
424 Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
428 Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
432 Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
436 Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
440 Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
444 Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
448 Lui(GpuRegister rt, uint16_t imm16) argument
465 Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
469 Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
473 Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
477 Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
481 Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
485 Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
489 Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
493 Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
497 Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
501 Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
546 Jic(GpuRegister rt, uint16_t imm16) argument
550 Jialc(GpuRegister rt, uint16_t imm16) argument
554 Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
561 Bltzc(GpuRegister rt, uint16_t imm16) argument
566 Bgtzc(GpuRegister rt, uint16_t imm16) argument
571 Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
578 Bgezc(GpuRegister rt, uint16_t imm16) argument
583 Blezc(GpuRegister rt, uint16_t imm16) argument
588 Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
595 Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
602 Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
609 Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
634 EmitBcondc(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint32_t imm16_21) argument
973 Mfc1(GpuRegister rt, FpuRegister fs) argument
977 Mfhc1(GpuRegister rt, FpuRegister fs) argument
981 Mtc1(GpuRegister rt, FpuRegister fs) argument
985 Mthc1(GpuRegister rt, FpuRegister fs) argument
989 Dmfc1(GpuRegister rt, FpuRegister fs) argument
993 Dmtc1(GpuRegister rt, FpuRegister fs) argument
1161 Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) argument
1747 Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument
1751 Bltzc(GpuRegister rt, Mips64Label* label) argument
1755 Bgtzc(GpuRegister rt, Mips64Label* label) argument
1759 Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument
1763 Bgezc(GpuRegister rt, Mips64Label* label) argument
1767 Blezc(GpuRegister rt, Mips64Label* label) argument
1771 Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument
1775 Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument
1779 Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument
1783 Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument
[all...]
/art/compiler/utils/arm/
H A Dassembler_arm32.cc830 void Arm32Assembler::ldrex(Register rt, Register rn, Condition cond) { argument
832 CHECK_NE(rt, kNoRegister);
839 (static_cast<int32_t>(rt) << kLdExRtShift) |
845 void Arm32Assembler::ldrexd(Register rt, Register rt2, Register rn, Condition cond) { argument
847 CHECK_NE(rt, kNoRegister);
849 CHECK_NE(rt, R14);
850 CHECK_EQ(0u, static_cast<uint32_t>(rt) % 2);
851 CHECK_EQ(static_cast<uint32_t>(rt) + 1, static_cast<uint32_t>(rt2));
858 static_cast<uint32_t>(rt) << 12 |
865 Register rt,
864 strex(Register rd, Register rt, Register rn, Condition cond) argument
882 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
921 vmovsr(SRegister sn, Register rt, Condition cond) argument
936 vmovrs(Register rt, SRegister sn, Condition cond) argument
951 vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond) argument
972 vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond) argument
994 vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond) argument
1014 vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond) argument
[all...]
H A Dassembler_thumb2.h175 void strex(Register rd, Register rt, Register rn, Condition cond = AL) OVERRIDE;
178 void strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond = AL);
180 void ldrexd(Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE;
181 void strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE;
198 void vmovsr(SRegister sn, Register rt, Condition cond = AL) OVERRIDE;
199 void vmovrs(Register rt, SRegister sn, Condition cond = AL) OVERRIDE;
200 void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
201 void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) OVERRIDE;
202 void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
203 void vmovrrd(Register rt, Registe
489 LoadNarrowLiteral(uint32_t location, Register rt, Size size) argument
498 LoadWideLiteral(uint32_t location, Register rt, Register rt2, Size size = kLongOrFPLiteral1KiB) argument
525 LoadLiteralAddress(uint32_t location, Register rt, Size size) argument
[all...]
H A Dassembler_thumb2.cc406 inline int16_t Thumb2Assembler::LdrLitEncoding16(Register rt, int32_t offset) { argument
407 DCHECK(!IsHighRegister(rt));
410 return B14 | B11 | (static_cast<int32_t>(rt) << 8) | (offset >> 2);
413 inline int32_t Thumb2Assembler::LdrLitEncoding32(Register rt, int32_t offset) { argument
415 return LdrRtRnImm12Encoding(rt, PC, offset);
418 inline int32_t Thumb2Assembler::LdrdEncoding32(Register rt, Register rt2, Register rn, int32_t offset) { argument
423 (static_cast<int32_t>(rn) << 16) | (static_cast<int32_t>(rt) << 12) |
449 inline int16_t Thumb2Assembler::LdrRtRnImm5Encoding16(Register rt, Register rn, int32_t offset) { argument
450 DCHECK(!IsHighRegister(rt));
455 (static_cast<int32_t>(rn) << 3) | static_cast<int32_t>(rt) |
473 LdrRtRnImm12Encoding(Register rt, Register rn, int32_t offset) argument
2725 ldrex(Register rt, Register rn, uint16_t imm, Condition cond) argument
2740 ldrex(Register rt, Register rn, Condition cond) argument
2745 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument
2765 ldrexd(Register rt, Register rt2, Register rn, Condition cond) argument
2781 strex(Register rd, Register rt, Register rn, Condition cond) argument
2789 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
2830 vmovsr(SRegister sn, Register rt, Condition cond) argument
2845 vmovrs(Register rt, SRegister sn, Condition cond) argument
2860 vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond) argument
2881 vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond) argument
2903 vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond) argument
2923 vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond) argument
3442 LoadLiteral(Register rt, Literal* literal) argument
3457 LoadLiteral(Register rt, Register rt2, Literal* literal) argument
[all...]
H A Dassembler_arm32.h137 void strex(Register rd, Register rt, Register rn, Condition cond = AL) OVERRIDE;
138 void ldrexd(Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE;
139 void strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE;
153 void vmovsr(SRegister sn, Register rt, Condition cond = AL) OVERRIDE;
154 void vmovrs(Register rt, SRegister sn, Condition cond = AL) OVERRIDE;
155 void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
156 void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) OVERRIDE;
157 void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
158 void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) OVERRIDE;
257 void LoadLiteral(Register rt, Litera
[all...]
H A Dassembler_arm.h596 virtual void strex(Register rd, Register rt, Register rn, Condition cond = AL) = 0;
597 virtual void ldrexd(Register rt, Register rt2, Register rn, Condition cond = AL) = 0;
598 virtual void strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond = AL) = 0;
619 virtual void vmovsr(SRegister sn, Register rt, Condition cond = AL) = 0;
620 virtual void vmovrs(Register rt, SRegister sn, Condition cond = AL) = 0;
621 virtual void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) = 0;
622 virtual void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) = 0;
623 virtual void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) = 0;
624 virtual void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) = 0;
719 virtual void LoadLiteral(Register rt, Litera
[all...]
/art/disassembler/
H A Ddisassembler_mips.cc415 uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type. local
457 args << "cc" << (rt >> 2);
528 case 'T': args << 'r' << rt; break; local
529 case 't': args << 'f' << rt; break; local
549 if (((op == 0x36 && rs == 0 && rt != 0) || // jic
550 (op == 0x19 && rs == rt && rt != 0)) && // daddiu
553 ((last_instr_ >> 21) & 0x1F) == rt) {
560 args << " ; move r" << rt << ", "; local

Completed in 76 milliseconds