Searched refs:shamt (Results 1 - 4 of 4) sorted by relevance

/art/compiler/utils/mips64/
H A Dassembler_mips64.h164 void Sll(GpuRegister rd, GpuRegister rt, int shamt);
165 void Srl(GpuRegister rd, GpuRegister rt, int shamt);
166 void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
167 void Sra(GpuRegister rd, GpuRegister rt, int shamt);
172 void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
173 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
174 void Drotr(GpuRegister rd, GpuRegister rt, int shamt);
175 void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
176 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
177 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS6
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H A Dassembler_mips64.cc92 int shamt, int funct) {
100 shamt << kShamtShift |
106 int shamt, int funct) {
113 shamt << kShamtShift |
119 int shamt, int funct) {
126 shamt << kShamtShift |
340 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { argument
341 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
344 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { argument
345 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt,
91 EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct) argument
105 EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct) argument
118 EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct) argument
348 Rotr(GpuRegister rd, GpuRegister rt, int shamt) argument
352 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument
372 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument
376 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument
380 Drotr(GpuRegister rd, GpuRegister rt, int shamt) argument
384 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument
388 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument
392 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument
396 Drotr32(GpuRegister rd, GpuRegister rt, int shamt) argument
400 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument
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/art/compiler/utils/mips/
H A Dassembler_mips.cc125 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument
133 shamt << kShamtShift |
367 void MipsAssembler::Sll(Register rd, Register rt, int shamt) { argument
368 CHECK(IsUint<5>(shamt)) << shamt;
369 EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x00);
372 void MipsAssembler::Srl(Register rd, Register rt, int shamt) { argument
373 CHECK(IsUint<5>(shamt)) << shamt;
374 EmitR(0, static_cast<Register>(0), rt, rd, shamt,
377 Rotr(Register rd, Register rt, int shamt) argument
382 Sra(Register rd, Register rt, int shamt) argument
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H A Dassembler_mips.h167 void Sll(Register rd, Register rt, int shamt);
168 void Srl(Register rd, Register rt, int shamt);
169 void Rotr(Register rd, Register rt, int shamt); // R2+
170 void Sra(Register rd, Register rt, int shamt);
763 void EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);

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