H A D | assembler_mips64.cc | 92 int shamt, int funct) { 100 shamt << kShamtShift | 106 int shamt, int funct) { 113 shamt << kShamtShift | 119 int shamt, int funct) { 126 shamt << kShamtShift | 340 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { argument 341 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00); 344 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { argument 345 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 91 EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct) argument 105 EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct) argument 118 EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct) argument 348 Rotr(GpuRegister rd, GpuRegister rt, int shamt) argument 352 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument 372 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument 376 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument 380 Drotr(GpuRegister rd, GpuRegister rt, int shamt) argument 384 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument 388 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument 392 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument 396 Drotr32(GpuRegister rd, GpuRegister rt, int shamt) argument 400 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument [all...] |