code_generator.h revision ec525fc30848189051b888da53ba051bc0878b78
1/* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_H_ 18#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_H_ 19 20#include "arch/instruction_set.h" 21#include "arch/instruction_set_features.h" 22#include "base/bit_field.h" 23#include "driver/compiler_options.h" 24#include "globals.h" 25#include "locations.h" 26#include "memory_region.h" 27#include "nodes.h" 28#include "stack_map_stream.h" 29 30namespace art { 31 32// Binary encoding of 2^32 for type double. 33static int64_t constexpr k2Pow32EncodingForDouble = INT64_C(0x41F0000000000000); 34// Binary encoding of 2^31 for type double. 35static int64_t constexpr k2Pow31EncodingForDouble = INT64_C(0x41E0000000000000); 36 37// Maximum value for a primitive integer. 38static int32_t constexpr kPrimIntMax = 0x7fffffff; 39// Maximum value for a primitive long. 40static int64_t constexpr kPrimLongMax = 0x7fffffffffffffff; 41 42class Assembler; 43class CodeGenerator; 44class DexCompilationUnit; 45class ParallelMoveResolver; 46class SrcMapElem; 47template <class Alloc> 48class SrcMap; 49using DefaultSrcMap = SrcMap<std::allocator<SrcMapElem>>; 50 51class CodeAllocator { 52 public: 53 CodeAllocator() {} 54 virtual ~CodeAllocator() {} 55 56 virtual uint8_t* Allocate(size_t size) = 0; 57 58 private: 59 DISALLOW_COPY_AND_ASSIGN(CodeAllocator); 60}; 61 62struct PcInfo { 63 uint32_t dex_pc; 64 uintptr_t native_pc; 65}; 66 67class SlowPathCode : public ArenaObject<kArenaAllocSlowPaths> { 68 public: 69 SlowPathCode() { 70 for (size_t i = 0; i < kMaximumNumberOfExpectedRegisters; ++i) { 71 saved_core_stack_offsets_[i] = kRegisterNotSaved; 72 saved_fpu_stack_offsets_[i] = kRegisterNotSaved; 73 } 74 } 75 76 virtual ~SlowPathCode() {} 77 78 virtual void EmitNativeCode(CodeGenerator* codegen) = 0; 79 80 void SaveLiveRegisters(CodeGenerator* codegen, LocationSummary* locations); 81 void RestoreLiveRegisters(CodeGenerator* codegen, LocationSummary* locations); 82 void RecordPcInfo(CodeGenerator* codegen, HInstruction* instruction, uint32_t dex_pc); 83 84 bool IsCoreRegisterSaved(int reg) const { 85 return saved_core_stack_offsets_[reg] != kRegisterNotSaved; 86 } 87 88 bool IsFpuRegisterSaved(int reg) const { 89 return saved_fpu_stack_offsets_[reg] != kRegisterNotSaved; 90 } 91 92 uint32_t GetStackOffsetOfCoreRegister(int reg) const { 93 return saved_core_stack_offsets_[reg]; 94 } 95 96 uint32_t GetStackOffsetOfFpuRegister(int reg) const { 97 return saved_fpu_stack_offsets_[reg]; 98 } 99 100 private: 101 static constexpr size_t kMaximumNumberOfExpectedRegisters = 32; 102 static constexpr uint32_t kRegisterNotSaved = -1; 103 uint32_t saved_core_stack_offsets_[kMaximumNumberOfExpectedRegisters]; 104 uint32_t saved_fpu_stack_offsets_[kMaximumNumberOfExpectedRegisters]; 105 DISALLOW_COPY_AND_ASSIGN(SlowPathCode); 106}; 107 108class InvokeDexCallingConventionVisitor { 109 public: 110 virtual Location GetNextLocation(Primitive::Type type) = 0; 111 112 protected: 113 InvokeDexCallingConventionVisitor() {} 114 virtual ~InvokeDexCallingConventionVisitor() {} 115 116 // The current index for core registers. 117 uint32_t gp_index_ = 0u; 118 // The current index for floating-point registers. 119 uint32_t float_index_ = 0u; 120 // The current stack index. 121 uint32_t stack_index_ = 0u; 122 123 private: 124 DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitor); 125}; 126 127class CodeGenerator { 128 public: 129 // Compiles the graph to executable instructions. Returns whether the compilation 130 // succeeded. 131 void CompileBaseline(CodeAllocator* allocator, bool is_leaf = false); 132 void CompileOptimized(CodeAllocator* allocator); 133 static CodeGenerator* Create(HGraph* graph, 134 InstructionSet instruction_set, 135 const InstructionSetFeatures& isa_features, 136 const CompilerOptions& compiler_options); 137 virtual ~CodeGenerator() {} 138 139 HGraph* GetGraph() const { return graph_; } 140 141 HBasicBlock* GetNextBlockToEmit() const; 142 HBasicBlock* FirstNonEmptyBlock(HBasicBlock* block) const; 143 bool GoesToNextBlock(HBasicBlock* current, HBasicBlock* next) const; 144 145 size_t GetStackSlotOfParameter(HParameterValue* parameter) const { 146 // Note that this follows the current calling convention. 147 return GetFrameSize() 148 + kVRegSize // Art method 149 + parameter->GetIndex() * kVRegSize; 150 } 151 152 virtual void Initialize() = 0; 153 virtual void Finalize(CodeAllocator* allocator); 154 virtual void GenerateFrameEntry() = 0; 155 virtual void GenerateFrameExit() = 0; 156 virtual void Bind(HBasicBlock* block) = 0; 157 virtual void Move(HInstruction* instruction, Location location, HInstruction* move_for) = 0; 158 virtual Assembler* GetAssembler() = 0; 159 virtual size_t GetWordSize() const = 0; 160 virtual size_t GetFloatingPointSpillSlotSize() const = 0; 161 virtual uintptr_t GetAddressOf(HBasicBlock* block) const = 0; 162 void InitializeCodeGeneration(size_t number_of_spill_slots, 163 size_t maximum_number_of_live_core_registers, 164 size_t maximum_number_of_live_fp_registers, 165 size_t number_of_out_slots, 166 const GrowableArray<HBasicBlock*>& block_order); 167 int32_t GetStackSlot(HLocal* local) const; 168 Location GetTemporaryLocation(HTemporary* temp) const; 169 170 uint32_t GetFrameSize() const { return frame_size_; } 171 void SetFrameSize(uint32_t size) { frame_size_ = size; } 172 uint32_t GetCoreSpillMask() const { return core_spill_mask_; } 173 uint32_t GetFpuSpillMask() const { return fpu_spill_mask_; } 174 175 size_t GetNumberOfCoreRegisters() const { return number_of_core_registers_; } 176 size_t GetNumberOfFloatingPointRegisters() const { return number_of_fpu_registers_; } 177 virtual void SetupBlockedRegisters(bool is_baseline) const = 0; 178 179 virtual void ComputeSpillMask() { 180 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_; 181 DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved"; 182 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; 183 } 184 185 static uint32_t ComputeRegisterMask(const int* registers, size_t length) { 186 uint32_t mask = 0; 187 for (size_t i = 0, e = length; i < e; ++i) { 188 mask |= (1 << registers[i]); 189 } 190 return mask; 191 } 192 193 virtual void DumpCoreRegister(std::ostream& stream, int reg) const = 0; 194 virtual void DumpFloatingPointRegister(std::ostream& stream, int reg) const = 0; 195 virtual InstructionSet GetInstructionSet() const = 0; 196 197 const CompilerOptions& GetCompilerOptions() const { return compiler_options_; } 198 199 // Saves the register in the stack. Returns the size taken on stack. 200 virtual size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) = 0; 201 // Restores the register from the stack. Returns the size taken on stack. 202 virtual size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) = 0; 203 204 virtual size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) = 0; 205 virtual size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) = 0; 206 207 virtual bool NeedsTwoRegisters(Primitive::Type type) const = 0; 208 // Returns whether we should split long moves in parallel moves. 209 virtual bool ShouldSplitLongMoves() const { return false; } 210 211 bool IsCoreCalleeSaveRegister(int reg) const { 212 return (core_callee_save_mask_ & (1 << reg)) != 0; 213 } 214 215 bool IsFloatingPointCalleeSaveRegister(int reg) const { 216 return (fpu_callee_save_mask_ & (1 << reg)) != 0; 217 } 218 219 void RecordPcInfo(HInstruction* instruction, uint32_t dex_pc, SlowPathCode* slow_path = nullptr); 220 bool CanMoveNullCheckToUser(HNullCheck* null_check); 221 void MaybeRecordImplicitNullCheck(HInstruction* instruction); 222 223 void AddSlowPath(SlowPathCode* slow_path) { 224 slow_paths_.Add(slow_path); 225 } 226 227 void BuildSourceMap(DefaultSrcMap* src_map) const; 228 void BuildMappingTable(std::vector<uint8_t>* vector) const; 229 void BuildVMapTable(std::vector<uint8_t>* vector) const; 230 void BuildNativeGCMap( 231 std::vector<uint8_t>* vector, const DexCompilationUnit& dex_compilation_unit) const; 232 void BuildStackMaps(std::vector<uint8_t>* vector); 233 234 bool IsBaseline() const { 235 return is_baseline_; 236 } 237 238 bool IsLeafMethod() const { 239 return is_leaf_; 240 } 241 242 void MarkNotLeaf() { 243 is_leaf_ = false; 244 requires_current_method_ = true; 245 } 246 247 void SetRequiresCurrentMethod() { 248 requires_current_method_ = true; 249 } 250 251 bool RequiresCurrentMethod() const { 252 return requires_current_method_; 253 } 254 255 // Clears the spill slots taken by loop phis in the `LocationSummary` of the 256 // suspend check. This is called when the code generator generates code 257 // for the suspend check at the back edge (instead of where the suspend check 258 // is, which is the loop entry). At this point, the spill slots for the phis 259 // have not been written to. 260 void ClearSpillSlotsFromLoopPhisInStackMap(HSuspendCheck* suspend_check) const; 261 262 bool* GetBlockedCoreRegisters() const { return blocked_core_registers_; } 263 bool* GetBlockedFloatingPointRegisters() const { return blocked_fpu_registers_; } 264 265 // Helper that returns the pointer offset of an index in an object array. 266 // Note: this method assumes we always have the same pointer size, regardless 267 // of the architecture. 268 static size_t GetCacheOffset(uint32_t index); 269 270 void EmitParallelMoves(Location from1, 271 Location to1, 272 Primitive::Type type1, 273 Location from2, 274 Location to2, 275 Primitive::Type type2); 276 277 static bool StoreNeedsWriteBarrier(Primitive::Type type, HInstruction* value) { 278 // Check that null value is not represented as an integer constant. 279 DCHECK(type != Primitive::kPrimNot || !value->IsIntConstant()); 280 return type == Primitive::kPrimNot && !value->IsNullConstant(); 281 } 282 283 void AddAllocatedRegister(Location location) { 284 allocated_registers_.Add(location); 285 } 286 287 void AllocateLocations(HInstruction* instruction); 288 289 // Tells whether the stack frame of the compiled method is 290 // considered "empty", that is either actually having a size of zero, 291 // or just containing the saved return address register. 292 bool HasEmptyFrame() const { 293 return GetFrameSize() == (CallPushesPC() ? GetWordSize() : 0); 294 } 295 296 static int32_t GetInt32ValueOf(HConstant* constant) { 297 if (constant->IsIntConstant()) { 298 return constant->AsIntConstant()->GetValue(); 299 } else if (constant->IsNullConstant()) { 300 return 0; 301 } else { 302 DCHECK(constant->IsFloatConstant()); 303 return bit_cast<int32_t, float>(constant->AsFloatConstant()->GetValue()); 304 } 305 } 306 307 static int64_t GetInt64ValueOf(HConstant* constant) { 308 if (constant->IsIntConstant()) { 309 return constant->AsIntConstant()->GetValue(); 310 } else if (constant->IsNullConstant()) { 311 return 0; 312 } else if (constant->IsFloatConstant()) { 313 return bit_cast<int32_t, float>(constant->AsFloatConstant()->GetValue()); 314 } else if (constant->IsLongConstant()) { 315 return constant->AsLongConstant()->GetValue(); 316 } else { 317 DCHECK(constant->IsDoubleConstant()); 318 return bit_cast<int64_t, double>(constant->AsDoubleConstant()->GetValue()); 319 } 320 } 321 322 size_t GetFirstRegisterSlotInSlowPath() const { 323 return first_register_slot_in_slow_path_; 324 } 325 326 uint32_t FrameEntrySpillSize() const { 327 return GetFpuSpillSize() + GetCoreSpillSize(); 328 } 329 330 virtual ParallelMoveResolver* GetMoveResolver() = 0; 331 332 protected: 333 CodeGenerator(HGraph* graph, 334 size_t number_of_core_registers, 335 size_t number_of_fpu_registers, 336 size_t number_of_register_pairs, 337 uint32_t core_callee_save_mask, 338 uint32_t fpu_callee_save_mask, 339 const CompilerOptions& compiler_options) 340 : frame_size_(0), 341 core_spill_mask_(0), 342 fpu_spill_mask_(0), 343 first_register_slot_in_slow_path_(0), 344 blocked_core_registers_(graph->GetArena()->AllocArray<bool>(number_of_core_registers)), 345 blocked_fpu_registers_(graph->GetArena()->AllocArray<bool>(number_of_fpu_registers)), 346 blocked_register_pairs_(graph->GetArena()->AllocArray<bool>(number_of_register_pairs)), 347 number_of_core_registers_(number_of_core_registers), 348 number_of_fpu_registers_(number_of_fpu_registers), 349 number_of_register_pairs_(number_of_register_pairs), 350 core_callee_save_mask_(core_callee_save_mask), 351 fpu_callee_save_mask_(fpu_callee_save_mask), 352 is_baseline_(false), 353 graph_(graph), 354 compiler_options_(compiler_options), 355 pc_infos_(graph->GetArena(), 32), 356 slow_paths_(graph->GetArena(), 8), 357 block_order_(nullptr), 358 current_block_index_(0), 359 is_leaf_(true), 360 requires_current_method_(false), 361 stack_map_stream_(graph->GetArena()) {} 362 363 // Register allocation logic. 364 void AllocateRegistersLocally(HInstruction* instruction) const; 365 366 // Backend specific implementation for allocating a register. 367 virtual Location AllocateFreeRegister(Primitive::Type type) const = 0; 368 369 static size_t FindFreeEntry(bool* array, size_t length); 370 static size_t FindTwoFreeConsecutiveAlignedEntries(bool* array, size_t length); 371 372 virtual Location GetStackLocation(HLoadLocal* load) const = 0; 373 374 virtual HGraphVisitor* GetLocationBuilder() = 0; 375 virtual HGraphVisitor* GetInstructionVisitor() = 0; 376 377 // Returns the location of the first spilled entry for floating point registers, 378 // relative to the stack pointer. 379 uint32_t GetFpuSpillStart() const { 380 return GetFrameSize() - FrameEntrySpillSize(); 381 } 382 383 uint32_t GetFpuSpillSize() const { 384 return POPCOUNT(fpu_spill_mask_) * GetFloatingPointSpillSlotSize(); 385 } 386 387 uint32_t GetCoreSpillSize() const { 388 return POPCOUNT(core_spill_mask_) * GetWordSize(); 389 } 390 391 bool HasAllocatedCalleeSaveRegisters() const { 392 // We check the core registers against 1 because it always comprises the return PC. 393 return (POPCOUNT(allocated_registers_.GetCoreRegisters() & core_callee_save_mask_) != 1) 394 || (POPCOUNT(allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_) != 0); 395 } 396 397 bool CallPushesPC() const { 398 InstructionSet instruction_set = GetInstructionSet(); 399 return instruction_set == kX86 || instruction_set == kX86_64; 400 } 401 402 // Arm64 has its own type for a label, so we need to templatize this method 403 // to share the logic. 404 template <typename T> 405 T* CommonGetLabelOf(T* raw_pointer_to_labels_array, HBasicBlock* block) const { 406 block = FirstNonEmptyBlock(block); 407 return raw_pointer_to_labels_array + block->GetBlockId(); 408 } 409 410 // Frame size required for this method. 411 uint32_t frame_size_; 412 uint32_t core_spill_mask_; 413 uint32_t fpu_spill_mask_; 414 uint32_t first_register_slot_in_slow_path_; 415 416 // Registers that were allocated during linear scan. 417 RegisterSet allocated_registers_; 418 419 // Arrays used when doing register allocation to know which 420 // registers we can allocate. `SetupBlockedRegisters` updates the 421 // arrays. 422 bool* const blocked_core_registers_; 423 bool* const blocked_fpu_registers_; 424 bool* const blocked_register_pairs_; 425 size_t number_of_core_registers_; 426 size_t number_of_fpu_registers_; 427 size_t number_of_register_pairs_; 428 const uint32_t core_callee_save_mask_; 429 const uint32_t fpu_callee_save_mask_; 430 431 // Whether we are using baseline. 432 bool is_baseline_; 433 434 private: 435 void InitLocationsBaseline(HInstruction* instruction); 436 size_t GetStackOffsetOfSavedRegister(size_t index); 437 void CompileInternal(CodeAllocator* allocator, bool is_baseline); 438 void BlockIfInRegister(Location location, bool is_out = false) const; 439 440 HGraph* const graph_; 441 const CompilerOptions& compiler_options_; 442 443 GrowableArray<PcInfo> pc_infos_; 444 GrowableArray<SlowPathCode*> slow_paths_; 445 446 // The order to use for code generation. 447 const GrowableArray<HBasicBlock*>* block_order_; 448 449 // The current block index in `block_order_` of the block 450 // we are generating code for. 451 size_t current_block_index_; 452 453 // Whether the method is a leaf method. 454 bool is_leaf_; 455 456 // Whether an instruction in the graph accesses the current method. 457 bool requires_current_method_; 458 459 StackMapStream stack_map_stream_; 460 461 friend class OptimizingCFITest; 462 463 DISALLOW_COPY_AND_ASSIGN(CodeGenerator); 464}; 465 466template <typename C, typename F> 467class CallingConvention { 468 public: 469 CallingConvention(const C* registers, 470 size_t number_of_registers, 471 const F* fpu_registers, 472 size_t number_of_fpu_registers) 473 : registers_(registers), 474 number_of_registers_(number_of_registers), 475 fpu_registers_(fpu_registers), 476 number_of_fpu_registers_(number_of_fpu_registers) {} 477 478 size_t GetNumberOfRegisters() const { return number_of_registers_; } 479 size_t GetNumberOfFpuRegisters() const { return number_of_fpu_registers_; } 480 481 C GetRegisterAt(size_t index) const { 482 DCHECK_LT(index, number_of_registers_); 483 return registers_[index]; 484 } 485 486 F GetFpuRegisterAt(size_t index) const { 487 DCHECK_LT(index, number_of_fpu_registers_); 488 return fpu_registers_[index]; 489 } 490 491 size_t GetStackOffsetOf(size_t index) const { 492 // We still reserve the space for parameters passed by registers. 493 // Add one for the method pointer. 494 return (index + 1) * kVRegSize; 495 } 496 497 private: 498 const C* registers_; 499 const size_t number_of_registers_; 500 const F* fpu_registers_; 501 const size_t number_of_fpu_registers_; 502 503 DISALLOW_COPY_AND_ASSIGN(CallingConvention); 504}; 505 506} // namespace art 507 508#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_H_ 509