code_generator_x86_64.h revision 17077d888a6752a2e5f8161eee1b2c3285783d12
1/* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_64_H_ 18#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_64_H_ 19 20#include "arch/x86_64/instruction_set_features_x86_64.h" 21#include "code_generator.h" 22#include "dex/compiler_enums.h" 23#include "driver/compiler_options.h" 24#include "nodes.h" 25#include "parallel_move_resolver.h" 26#include "utils/x86_64/assembler_x86_64.h" 27 28namespace art { 29namespace x86_64 { 30 31// Use a local definition to prevent copying mistakes. 32static constexpr size_t kX86_64WordSize = kX86_64PointerSize; 33 34// Some x86_64 instructions require a register to be available as temp. 35static constexpr Register TMP = R11; 36 37static constexpr Register kParameterCoreRegisters[] = { RSI, RDX, RCX, R8, R9 }; 38static constexpr FloatRegister kParameterFloatRegisters[] = 39 { XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7 }; 40 41static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters); 42static constexpr size_t kParameterFloatRegistersLength = arraysize(kParameterFloatRegisters); 43 44static constexpr Register kRuntimeParameterCoreRegisters[] = { RDI, RSI, RDX, RCX }; 45static constexpr size_t kRuntimeParameterCoreRegistersLength = 46 arraysize(kRuntimeParameterCoreRegisters); 47static constexpr FloatRegister kRuntimeParameterFpuRegisters[] = { XMM0, XMM1 }; 48static constexpr size_t kRuntimeParameterFpuRegistersLength = 49 arraysize(kRuntimeParameterFpuRegisters); 50 51// These XMM registers are non-volatile in ART ABI, but volatile in native ABI. 52// If the ART ABI changes, this list must be updated. It is used to ensure that 53// these are not clobbered by any direct call to native code (such as math intrinsics). 54static constexpr FloatRegister non_volatile_xmm_regs[] = { XMM12, XMM13, XMM14, XMM15 }; 55 56 57class InvokeRuntimeCallingConvention : public CallingConvention<Register, FloatRegister> { 58 public: 59 InvokeRuntimeCallingConvention() 60 : CallingConvention(kRuntimeParameterCoreRegisters, 61 kRuntimeParameterCoreRegistersLength, 62 kRuntimeParameterFpuRegisters, 63 kRuntimeParameterFpuRegistersLength, 64 kX86_64PointerSize) {} 65 66 private: 67 DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConvention); 68}; 69 70class InvokeDexCallingConvention : public CallingConvention<Register, FloatRegister> { 71 public: 72 InvokeDexCallingConvention() : CallingConvention( 73 kParameterCoreRegisters, 74 kParameterCoreRegistersLength, 75 kParameterFloatRegisters, 76 kParameterFloatRegistersLength, 77 kX86_64PointerSize) {} 78 79 private: 80 DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConvention); 81}; 82 83class FieldAccessCallingConventionX86_64 : public FieldAccessCallingConvention { 84 public: 85 FieldAccessCallingConventionX86_64() {} 86 87 Location GetObjectLocation() const OVERRIDE { 88 return Location::RegisterLocation(RSI); 89 } 90 Location GetFieldIndexLocation() const OVERRIDE { 91 return Location::RegisterLocation(RDI); 92 } 93 Location GetReturnLocation(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE { 94 return Location::RegisterLocation(RAX); 95 } 96 Location GetSetValueLocation(Primitive::Type type, bool is_instance) const OVERRIDE { 97 return Primitive::Is64BitType(type) 98 ? Location::RegisterLocation(RDX) 99 : (is_instance 100 ? Location::RegisterLocation(RDX) 101 : Location::RegisterLocation(RSI)); 102 } 103 Location GetFpuLocation(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE { 104 return Location::FpuRegisterLocation(XMM0); 105 } 106 107 private: 108 DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionX86_64); 109}; 110 111 112class InvokeDexCallingConventionVisitorX86_64 : public InvokeDexCallingConventionVisitor { 113 public: 114 InvokeDexCallingConventionVisitorX86_64() {} 115 virtual ~InvokeDexCallingConventionVisitorX86_64() {} 116 117 Location GetNextLocation(Primitive::Type type) OVERRIDE; 118 Location GetReturnLocation(Primitive::Type type) const OVERRIDE; 119 Location GetMethodLocation() const OVERRIDE; 120 121 private: 122 InvokeDexCallingConvention calling_convention; 123 124 DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorX86_64); 125}; 126 127class CodeGeneratorX86_64; 128 129class ParallelMoveResolverX86_64 : public ParallelMoveResolverWithSwap { 130 public: 131 ParallelMoveResolverX86_64(ArenaAllocator* allocator, CodeGeneratorX86_64* codegen) 132 : ParallelMoveResolverWithSwap(allocator), codegen_(codegen) {} 133 134 void EmitMove(size_t index) OVERRIDE; 135 void EmitSwap(size_t index) OVERRIDE; 136 void SpillScratch(int reg) OVERRIDE; 137 void RestoreScratch(int reg) OVERRIDE; 138 139 X86_64Assembler* GetAssembler() const; 140 141 private: 142 void Exchange32(CpuRegister reg, int mem); 143 void Exchange32(XmmRegister reg, int mem); 144 void Exchange32(int mem1, int mem2); 145 void Exchange64(CpuRegister reg, int mem); 146 void Exchange64(XmmRegister reg, int mem); 147 void Exchange64(int mem1, int mem2); 148 149 CodeGeneratorX86_64* const codegen_; 150 151 DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverX86_64); 152}; 153 154class LocationsBuilderX86_64 : public HGraphVisitor { 155 public: 156 LocationsBuilderX86_64(HGraph* graph, CodeGeneratorX86_64* codegen) 157 : HGraphVisitor(graph), codegen_(codegen) {} 158 159#define DECLARE_VISIT_INSTRUCTION(name, super) \ 160 void Visit##name(H##name* instr) OVERRIDE; 161 162 FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION) 163 FOR_EACH_CONCRETE_INSTRUCTION_X86_64(DECLARE_VISIT_INSTRUCTION) 164 165#undef DECLARE_VISIT_INSTRUCTION 166 167 void VisitInstruction(HInstruction* instruction) OVERRIDE { 168 LOG(FATAL) << "Unreachable instruction " << instruction->DebugName() 169 << " (id " << instruction->GetId() << ")"; 170 } 171 172 private: 173 void HandleInvoke(HInvoke* invoke); 174 void HandleBitwiseOperation(HBinaryOperation* operation); 175 void HandleShift(HBinaryOperation* operation); 176 void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info); 177 void HandleFieldGet(HInstruction* instruction); 178 179 CodeGeneratorX86_64* const codegen_; 180 InvokeDexCallingConventionVisitorX86_64 parameter_visitor_; 181 182 DISALLOW_COPY_AND_ASSIGN(LocationsBuilderX86_64); 183}; 184 185class InstructionCodeGeneratorX86_64 : public HGraphVisitor { 186 public: 187 InstructionCodeGeneratorX86_64(HGraph* graph, CodeGeneratorX86_64* codegen); 188 189#define DECLARE_VISIT_INSTRUCTION(name, super) \ 190 void Visit##name(H##name* instr) OVERRIDE; 191 192 FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION) 193 FOR_EACH_CONCRETE_INSTRUCTION_X86_64(DECLARE_VISIT_INSTRUCTION) 194 195#undef DECLARE_VISIT_INSTRUCTION 196 197 void VisitInstruction(HInstruction* instruction) OVERRIDE { 198 LOG(FATAL) << "Unreachable instruction " << instruction->DebugName() 199 << " (id " << instruction->GetId() << ")"; 200 } 201 202 X86_64Assembler* GetAssembler() const { return assembler_; } 203 204 private: 205 // Generate code for the given suspend check. If not null, `successor` 206 // is the block to branch to if the suspend check is not needed, and after 207 // the suspend call. 208 void GenerateSuspendCheck(HSuspendCheck* instruction, HBasicBlock* successor); 209 void GenerateClassInitializationCheck(SlowPathCode* slow_path, CpuRegister class_reg); 210 void HandleBitwiseOperation(HBinaryOperation* operation); 211 void GenerateRemFP(HRem* rem); 212 void DivRemOneOrMinusOne(HBinaryOperation* instruction); 213 void DivByPowerOfTwo(HDiv* instruction); 214 void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction); 215 void GenerateDivRemIntegral(HBinaryOperation* instruction); 216 void HandleShift(HBinaryOperation* operation); 217 218 void HandleFieldSet(HInstruction* instruction, 219 const FieldInfo& field_info, 220 bool value_can_be_null); 221 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info); 222 223 // Generate a heap reference load using one register `out`: 224 // 225 // out <- *(out + offset) 226 // 227 // while honoring heap poisoning and/or read barriers (if any). 228 // Register `temp` is used when generating a read barrier. 229 void GenerateReferenceLoadOneRegister(HInstruction* instruction, 230 Location out, 231 uint32_t offset, 232 Location temp); 233 // Generate a heap reference load using two different registers 234 // `out` and `obj`: 235 // 236 // out <- *(obj + offset) 237 // 238 // while honoring heap poisoning and/or read barriers (if any). 239 // Register `temp` is used when generating a Baker's read barrier. 240 void GenerateReferenceLoadTwoRegisters(HInstruction* instruction, 241 Location out, 242 Location obj, 243 uint32_t offset, 244 Location temp); 245 // Generate a GC root reference load: 246 // 247 // root <- *(obj + offset) 248 // 249 // while honoring read barriers (if any). 250 void GenerateGcRootFieldLoad(HInstruction* instruction, 251 Location root, 252 CpuRegister obj, 253 uint32_t offset); 254 255 void GenerateImplicitNullCheck(HNullCheck* instruction); 256 void GenerateExplicitNullCheck(HNullCheck* instruction); 257 void PushOntoFPStack(Location source, uint32_t temp_offset, 258 uint32_t stack_adjustment, bool is_float); 259 void GenerateTestAndBranch(HInstruction* instruction, 260 size_t condition_input_index, 261 Label* true_target, 262 Label* false_target); 263 void GenerateCompareTestAndBranch(HCondition* condition, 264 Label* true_target, 265 Label* false_target); 266 void GenerateFPJumps(HCondition* cond, Label* true_label, Label* false_label); 267 void HandleGoto(HInstruction* got, HBasicBlock* successor); 268 269 X86_64Assembler* const assembler_; 270 CodeGeneratorX86_64* const codegen_; 271 272 DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorX86_64); 273}; 274 275// Class for fixups to jump tables. 276class JumpTableRIPFixup; 277 278class CodeGeneratorX86_64 : public CodeGenerator { 279 public: 280 CodeGeneratorX86_64(HGraph* graph, 281 const X86_64InstructionSetFeatures& isa_features, 282 const CompilerOptions& compiler_options, 283 OptimizingCompilerStats* stats = nullptr); 284 virtual ~CodeGeneratorX86_64() {} 285 286 void GenerateFrameEntry() OVERRIDE; 287 void GenerateFrameExit() OVERRIDE; 288 void Bind(HBasicBlock* block) OVERRIDE; 289 void Move(HInstruction* instruction, Location location, HInstruction* move_for) OVERRIDE; 290 void MoveConstant(Location destination, int32_t value) OVERRIDE; 291 void MoveLocation(Location dst, Location src, Primitive::Type dst_type) OVERRIDE; 292 void AddLocationAsTemp(Location location, LocationSummary* locations) OVERRIDE; 293 294 size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE; 295 size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE; 296 size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE; 297 size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE; 298 299 // Generate code to invoke a runtime entry point. 300 void InvokeRuntime(QuickEntrypointEnum entrypoint, 301 HInstruction* instruction, 302 uint32_t dex_pc, 303 SlowPathCode* slow_path) OVERRIDE; 304 305 void InvokeRuntime(int32_t entry_point_offset, 306 HInstruction* instruction, 307 uint32_t dex_pc, 308 SlowPathCode* slow_path); 309 310 size_t GetWordSize() const OVERRIDE { 311 return kX86_64WordSize; 312 } 313 314 size_t GetFloatingPointSpillSlotSize() const OVERRIDE { 315 return kX86_64WordSize; 316 } 317 318 HGraphVisitor* GetLocationBuilder() OVERRIDE { 319 return &location_builder_; 320 } 321 322 HGraphVisitor* GetInstructionVisitor() OVERRIDE { 323 return &instruction_visitor_; 324 } 325 326 X86_64Assembler* GetAssembler() OVERRIDE { 327 return &assembler_; 328 } 329 330 const X86_64Assembler& GetAssembler() const OVERRIDE { 331 return assembler_; 332 } 333 334 ParallelMoveResolverX86_64* GetMoveResolver() OVERRIDE { 335 return &move_resolver_; 336 } 337 338 uintptr_t GetAddressOf(HBasicBlock* block) const OVERRIDE { 339 return GetLabelOf(block)->Position(); 340 } 341 342 Location GetStackLocation(HLoadLocal* load) const OVERRIDE; 343 344 void SetupBlockedRegisters(bool is_baseline) const OVERRIDE; 345 Location AllocateFreeRegister(Primitive::Type type) const OVERRIDE; 346 void DumpCoreRegister(std::ostream& stream, int reg) const OVERRIDE; 347 void DumpFloatingPointRegister(std::ostream& stream, int reg) const OVERRIDE; 348 void Finalize(CodeAllocator* allocator) OVERRIDE; 349 350 InstructionSet GetInstructionSet() const OVERRIDE { 351 return InstructionSet::kX86_64; 352 } 353 354 // Emit a write barrier. 355 void MarkGCCard(CpuRegister temp, 356 CpuRegister card, 357 CpuRegister object, 358 CpuRegister value, 359 bool value_can_be_null); 360 361 void GenerateMemoryBarrier(MemBarrierKind kind); 362 363 // Helper method to move a value between two locations. 364 void Move(Location destination, Location source); 365 366 Label* GetLabelOf(HBasicBlock* block) const { 367 return CommonGetLabelOf<Label>(block_labels_, block); 368 } 369 370 void Initialize() OVERRIDE { 371 block_labels_ = CommonInitializeLabels<Label>(); 372 } 373 374 bool NeedsTwoRegisters(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE { 375 return false; 376 } 377 378 // Check if the desired_dispatch_info is supported. If it is, return it, 379 // otherwise return a fall-back info that should be used instead. 380 HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch( 381 const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info, 382 MethodReference target_method) OVERRIDE; 383 384 void GenerateStaticOrDirectCall(HInvokeStaticOrDirect* invoke, Location temp) OVERRIDE; 385 void GenerateVirtualCall(HInvokeVirtual* invoke, Location temp) OVERRIDE; 386 387 void MoveFromReturnRegister(Location trg, Primitive::Type type) OVERRIDE; 388 389 void EmitLinkerPatches(ArenaVector<LinkerPatch>* linker_patches) OVERRIDE; 390 391 const X86_64InstructionSetFeatures& GetInstructionSetFeatures() const { 392 return isa_features_; 393 } 394 395 // Fast path implementation of ReadBarrier::Barrier for a heap 396 // reference field load when Baker's read barriers are used. 397 void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction, 398 Location out, 399 CpuRegister obj, 400 uint32_t offset, 401 Location temp, 402 bool needs_null_check); 403 // Fast path implementation of ReadBarrier::Barrier for a heap 404 // reference array load when Baker's read barriers are used. 405 void GenerateArrayLoadWithBakerReadBarrier(HInstruction* instruction, 406 Location out, 407 CpuRegister obj, 408 uint32_t data_offset, 409 Location index, 410 Location temp, 411 bool needs_null_check); 412 413 // Generate a read barrier for a heap reference within `instruction` 414 // using a slow path. 415 // 416 // A read barrier for an object reference read from the heap is 417 // implemented as a call to the artReadBarrierSlow runtime entry 418 // point, which is passed the values in locations `ref`, `obj`, and 419 // `offset`: 420 // 421 // mirror::Object* artReadBarrierSlow(mirror::Object* ref, 422 // mirror::Object* obj, 423 // uint32_t offset); 424 // 425 // The `out` location contains the value returned by 426 // artReadBarrierSlow. 427 // 428 // When `index` provided (i.e., when it is different from 429 // Location::NoLocation()), the offset value passed to 430 // artReadBarrierSlow is adjusted to take `index` into account. 431 void GenerateReadBarrierSlow(HInstruction* instruction, 432 Location out, 433 Location ref, 434 Location obj, 435 uint32_t offset, 436 Location index = Location::NoLocation()); 437 438 // If read barriers are enabled, generate a read barrier for a heap 439 // reference using a slow path. If heap poisoning is enabled, also 440 // unpoison the reference in `out`. 441 void MaybeGenerateReadBarrierSlow(HInstruction* instruction, 442 Location out, 443 Location ref, 444 Location obj, 445 uint32_t offset, 446 Location index = Location::NoLocation()); 447 448 // Generate a read barrier for a GC root within `instruction` using 449 // a slow path. 450 // 451 // A read barrier for an object reference GC root is implemented as 452 // a call to the artReadBarrierForRootSlow runtime entry point, 453 // which is passed the value in location `root`: 454 // 455 // mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root); 456 // 457 // The `out` location contains the value returned by 458 // artReadBarrierForRootSlow. 459 void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root); 460 461 int ConstantAreaStart() const { 462 return constant_area_start_; 463 } 464 465 Address LiteralDoubleAddress(double v); 466 Address LiteralFloatAddress(float v); 467 Address LiteralInt32Address(int32_t v); 468 Address LiteralInt64Address(int64_t v); 469 470 // Load a 64 bit value into a register in the most efficient manner. 471 void Load64BitValue(CpuRegister dest, int64_t value); 472 Address LiteralCaseTable(HPackedSwitch* switch_instr); 473 474 // Store a 64 bit value into a DoubleStackSlot in the most efficient manner. 475 void Store64BitValueToStack(Location dest, int64_t value); 476 477 // Assign a 64 bit constant to an address. 478 void MoveInt64ToAddress(const Address& addr_low, 479 const Address& addr_high, 480 int64_t v, 481 HInstruction* instruction); 482 483 // Ensure that prior stores complete to memory before subsequent loads. 484 // The locked add implementation will avoid serializing device memory, but will 485 // touch (but not change) the top of the stack. The locked add should not be used for 486 // ordering non-temporal stores. 487 void MemoryFence(bool force_mfence = false) { 488 if (!force_mfence && isa_features_.PrefersLockedAddSynchronization()) { 489 assembler_.lock()->addl(Address(CpuRegister(RSP), 0), Immediate(0)); 490 } else { 491 assembler_.mfence(); 492 } 493 } 494 495 private: 496 // Factored implementation of GenerateFieldLoadWithBakerReadBarrier 497 // and GenerateArrayLoadWithBakerReadBarrier. 498 void GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction, 499 Location ref, 500 CpuRegister obj, 501 const Address& src, 502 Location temp, 503 bool needs_null_check); 504 505 struct PcRelativeDexCacheAccessInfo { 506 PcRelativeDexCacheAccessInfo(const DexFile& dex_file, uint32_t element_off) 507 : target_dex_file(dex_file), element_offset(element_off), label() { } 508 509 const DexFile& target_dex_file; 510 uint32_t element_offset; 511 Label label; 512 }; 513 514 // Labels for each block that will be compiled. 515 Label* block_labels_; // Indexed by block id. 516 Label frame_entry_label_; 517 LocationsBuilderX86_64 location_builder_; 518 InstructionCodeGeneratorX86_64 instruction_visitor_; 519 ParallelMoveResolverX86_64 move_resolver_; 520 X86_64Assembler assembler_; 521 const X86_64InstructionSetFeatures& isa_features_; 522 523 // Offset to the start of the constant area in the assembled code. 524 // Used for fixups to the constant area. 525 int constant_area_start_; 526 527 // Method patch info. Using ArenaDeque<> which retains element addresses on push/emplace_back(). 528 ArenaDeque<MethodPatchInfo<Label>> method_patches_; 529 ArenaDeque<MethodPatchInfo<Label>> relative_call_patches_; 530 // PC-relative DexCache access info. 531 ArenaDeque<PcRelativeDexCacheAccessInfo> pc_relative_dex_cache_patches_; 532 533 // When we don't know the proper offset for the value, we use kDummy32BitOffset. 534 // We will fix this up in the linker later to have the right value. 535 static constexpr int32_t kDummy32BitOffset = 256; 536 537 // Fixups for jump tables need to be handled specially. 538 ArenaVector<JumpTableRIPFixup*> fixups_to_jump_tables_; 539 540 DISALLOW_COPY_AND_ASSIGN(CodeGeneratorX86_64); 541}; 542 543} // namespace x86_64 544} // namespace art 545 546#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_64_H_ 547