code_generator_x86_64.h revision 5f7b58ea1adfc0639dd605b65f59198d3763f801 
1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_64_H_
18#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_64_H_
19
20#include "arch/x86_64/instruction_set_features_x86_64.h"
21#include "code_generator.h"
22#include "dex/compiler_enums.h"
23#include "driver/compiler_options.h"
24#include "nodes.h"
25#include "parallel_move_resolver.h"
26#include "utils/x86_64/assembler_x86_64.h"
27
28namespace art {
29namespace x86_64 {
30
31// Use a local definition to prevent copying mistakes.
32static constexpr size_t kX86_64WordSize = kX86_64PointerSize;
33
34// Some x86_64 instructions require a register to be available as temp.
35static constexpr Register TMP = R11;
36
37static constexpr Register kParameterCoreRegisters[] = { RSI, RDX, RCX, R8, R9 };
38static constexpr FloatRegister kParameterFloatRegisters[] =
39    { XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7 };
40
41static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters);
42static constexpr size_t kParameterFloatRegistersLength = arraysize(kParameterFloatRegisters);
43
44static constexpr Register kRuntimeParameterCoreRegisters[] = { RDI, RSI, RDX, RCX };
45static constexpr size_t kRuntimeParameterCoreRegistersLength =
46    arraysize(kRuntimeParameterCoreRegisters);
47static constexpr FloatRegister kRuntimeParameterFpuRegisters[] = { XMM0, XMM1 };
48static constexpr size_t kRuntimeParameterFpuRegistersLength =
49    arraysize(kRuntimeParameterFpuRegisters);
50
51// These XMM registers are non-volatile in ART ABI, but volatile in native ABI.
52// If the ART ABI changes, this list must be updated.  It is used to ensure that
53// these are not clobbered by any direct call to native code (such as math intrinsics).
54static constexpr FloatRegister non_volatile_xmm_regs[] = { XMM12, XMM13, XMM14, XMM15 };
55
56
57class InvokeRuntimeCallingConvention : public CallingConvention<Register, FloatRegister> {
58 public:
59  InvokeRuntimeCallingConvention()
60      : CallingConvention(kRuntimeParameterCoreRegisters,
61                          kRuntimeParameterCoreRegistersLength,
62                          kRuntimeParameterFpuRegisters,
63                          kRuntimeParameterFpuRegistersLength,
64                          kX86_64PointerSize) {}
65
66 private:
67  DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConvention);
68};
69
70class InvokeDexCallingConvention : public CallingConvention<Register, FloatRegister> {
71 public:
72  InvokeDexCallingConvention() : CallingConvention(
73      kParameterCoreRegisters,
74      kParameterCoreRegistersLength,
75      kParameterFloatRegisters,
76      kParameterFloatRegistersLength,
77      kX86_64PointerSize) {}
78
79 private:
80  DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConvention);
81};
82
83class FieldAccessCallingConventionX86_64 : public FieldAccessCallingConvention {
84 public:
85  FieldAccessCallingConventionX86_64() {}
86
87  Location GetObjectLocation() const OVERRIDE {
88    return Location::RegisterLocation(RSI);
89  }
90  Location GetFieldIndexLocation() const OVERRIDE {
91    return Location::RegisterLocation(RDI);
92  }
93  Location GetReturnLocation(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE {
94    return Location::RegisterLocation(RAX);
95  }
96  Location GetSetValueLocation(Primitive::Type type, bool is_instance) const OVERRIDE {
97    return Primitive::Is64BitType(type)
98        ? Location::RegisterLocation(RDX)
99        : (is_instance
100            ? Location::RegisterLocation(RDX)
101            : Location::RegisterLocation(RSI));
102  }
103  Location GetFpuLocation(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE {
104    return Location::FpuRegisterLocation(XMM0);
105  }
106
107 private:
108  DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionX86_64);
109};
110
111
112class InvokeDexCallingConventionVisitorX86_64 : public InvokeDexCallingConventionVisitor {
113 public:
114  InvokeDexCallingConventionVisitorX86_64() {}
115  virtual ~InvokeDexCallingConventionVisitorX86_64() {}
116
117  Location GetNextLocation(Primitive::Type type) OVERRIDE;
118  Location GetReturnLocation(Primitive::Type type) const OVERRIDE;
119  Location GetMethodLocation() const OVERRIDE;
120
121 private:
122  InvokeDexCallingConvention calling_convention;
123
124  DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorX86_64);
125};
126
127class CodeGeneratorX86_64;
128
129class ParallelMoveResolverX86_64 : public ParallelMoveResolverWithSwap {
130 public:
131  ParallelMoveResolverX86_64(ArenaAllocator* allocator, CodeGeneratorX86_64* codegen)
132      : ParallelMoveResolverWithSwap(allocator), codegen_(codegen) {}
133
134  void EmitMove(size_t index) OVERRIDE;
135  void EmitSwap(size_t index) OVERRIDE;
136  void SpillScratch(int reg) OVERRIDE;
137  void RestoreScratch(int reg) OVERRIDE;
138
139  X86_64Assembler* GetAssembler() const;
140
141 private:
142  void Exchange32(CpuRegister reg, int mem);
143  void Exchange32(XmmRegister reg, int mem);
144  void Exchange32(int mem1, int mem2);
145  void Exchange64(CpuRegister reg, int mem);
146  void Exchange64(XmmRegister reg, int mem);
147  void Exchange64(int mem1, int mem2);
148
149  CodeGeneratorX86_64* const codegen_;
150
151  DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverX86_64);
152};
153
154class LocationsBuilderX86_64 : public HGraphVisitor {
155 public:
156  LocationsBuilderX86_64(HGraph* graph, CodeGeneratorX86_64* codegen)
157      : HGraphVisitor(graph), codegen_(codegen) {}
158
159#define DECLARE_VISIT_INSTRUCTION(name, super)     \
160  void Visit##name(H##name* instr) OVERRIDE;
161
162  FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
163  FOR_EACH_CONCRETE_INSTRUCTION_X86_64(DECLARE_VISIT_INSTRUCTION)
164
165#undef DECLARE_VISIT_INSTRUCTION
166
167  void VisitInstruction(HInstruction* instruction) OVERRIDE {
168    LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
169               << " (id " << instruction->GetId() << ")";
170  }
171
172 private:
173  void HandleInvoke(HInvoke* invoke);
174  void HandleBitwiseOperation(HBinaryOperation* operation);
175  void HandleCondition(HCondition* condition);
176  void HandleShift(HBinaryOperation* operation);
177  void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info);
178  void HandleFieldGet(HInstruction* instruction);
179
180  CodeGeneratorX86_64* const codegen_;
181  InvokeDexCallingConventionVisitorX86_64 parameter_visitor_;
182
183  DISALLOW_COPY_AND_ASSIGN(LocationsBuilderX86_64);
184};
185
186class InstructionCodeGeneratorX86_64 : public HGraphVisitor {
187 public:
188  InstructionCodeGeneratorX86_64(HGraph* graph, CodeGeneratorX86_64* codegen);
189
190#define DECLARE_VISIT_INSTRUCTION(name, super)     \
191  void Visit##name(H##name* instr) OVERRIDE;
192
193  FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
194  FOR_EACH_CONCRETE_INSTRUCTION_X86_64(DECLARE_VISIT_INSTRUCTION)
195
196#undef DECLARE_VISIT_INSTRUCTION
197
198  void VisitInstruction(HInstruction* instruction) OVERRIDE {
199    LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
200               << " (id " << instruction->GetId() << ")";
201  }
202
203  X86_64Assembler* GetAssembler() const { return assembler_; }
204
205 private:
206  // Generate code for the given suspend check. If not null, `successor`
207  // is the block to branch to if the suspend check is not needed, and after
208  // the suspend call.
209  void GenerateSuspendCheck(HSuspendCheck* instruction, HBasicBlock* successor);
210  void GenerateClassInitializationCheck(SlowPathCode* slow_path, CpuRegister class_reg);
211  void HandleBitwiseOperation(HBinaryOperation* operation);
212  void GenerateRemFP(HRem* rem);
213  void DivRemOneOrMinusOne(HBinaryOperation* instruction);
214  void DivByPowerOfTwo(HDiv* instruction);
215  void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction);
216  void GenerateDivRemIntegral(HBinaryOperation* instruction);
217  void HandleCondition(HCondition* condition);
218  void HandleShift(HBinaryOperation* operation);
219
220  void HandleFieldSet(HInstruction* instruction,
221                      const FieldInfo& field_info,
222                      bool value_can_be_null);
223  void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
224
225  // Generate a heap reference load using one register `out`:
226  //
227  //   out <- *(out + offset)
228  //
229  // while honoring heap poisoning and/or read barriers (if any).
230  // Register `temp` is used when generating a read barrier.
231  void GenerateReferenceLoadOneRegister(HInstruction* instruction,
232                                        Location out,
233                                        uint32_t offset,
234                                        Location temp);
235  // Generate a heap reference load using two different registers
236  // `out` and `obj`:
237  //
238  //   out <- *(obj + offset)
239  //
240  // while honoring heap poisoning and/or read barriers (if any).
241  // Register `temp` is used when generating a Baker's read barrier.
242  void GenerateReferenceLoadTwoRegisters(HInstruction* instruction,
243                                         Location out,
244                                         Location obj,
245                                         uint32_t offset,
246                                         Location temp);
247  // Generate a GC root reference load:
248  //
249  //   root <- *(obj + offset)
250  //
251  // while honoring read barriers (if any).
252  void GenerateGcRootFieldLoad(HInstruction* instruction,
253                               Location root,
254                               CpuRegister obj,
255                               uint32_t offset);
256
257  void GenerateImplicitNullCheck(HNullCheck* instruction);
258  void GenerateExplicitNullCheck(HNullCheck* instruction);
259  void PushOntoFPStack(Location source, uint32_t temp_offset,
260                       uint32_t stack_adjustment, bool is_float);
261  void GenerateTestAndBranch(HInstruction* instruction,
262                             size_t condition_input_index,
263                             Label* true_target,
264                             Label* false_target);
265  void GenerateCompareTestAndBranch(HCondition* condition,
266                                    Label* true_target,
267                                    Label* false_target);
268  void GenerateFPJumps(HCondition* cond, Label* true_label, Label* false_label);
269  void HandleGoto(HInstruction* got, HBasicBlock* successor);
270
271  X86_64Assembler* const assembler_;
272  CodeGeneratorX86_64* const codegen_;
273
274  DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorX86_64);
275};
276
277// Class for fixups to jump tables.
278class JumpTableRIPFixup;
279
280class CodeGeneratorX86_64 : public CodeGenerator {
281 public:
282  CodeGeneratorX86_64(HGraph* graph,
283                  const X86_64InstructionSetFeatures& isa_features,
284                  const CompilerOptions& compiler_options,
285                  OptimizingCompilerStats* stats = nullptr);
286  virtual ~CodeGeneratorX86_64() {}
287
288  void GenerateFrameEntry() OVERRIDE;
289  void GenerateFrameExit() OVERRIDE;
290  void Bind(HBasicBlock* block) OVERRIDE;
291  void Move(HInstruction* instruction, Location location, HInstruction* move_for) OVERRIDE;
292  void MoveConstant(Location destination, int32_t value) OVERRIDE;
293  void MoveLocation(Location dst, Location src, Primitive::Type dst_type) OVERRIDE;
294  void AddLocationAsTemp(Location location, LocationSummary* locations) OVERRIDE;
295
296  size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
297  size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
298  size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
299  size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE;
300
301  // Generate code to invoke a runtime entry point.
302  void InvokeRuntime(QuickEntrypointEnum entrypoint,
303                     HInstruction* instruction,
304                     uint32_t dex_pc,
305                     SlowPathCode* slow_path) OVERRIDE;
306
307  void InvokeRuntime(int32_t entry_point_offset,
308                     HInstruction* instruction,
309                     uint32_t dex_pc,
310                     SlowPathCode* slow_path);
311
312  size_t GetWordSize() const OVERRIDE {
313    return kX86_64WordSize;
314  }
315
316  size_t GetFloatingPointSpillSlotSize() const OVERRIDE {
317    return kX86_64WordSize;
318  }
319
320  HGraphVisitor* GetLocationBuilder() OVERRIDE {
321    return &location_builder_;
322  }
323
324  HGraphVisitor* GetInstructionVisitor() OVERRIDE {
325    return &instruction_visitor_;
326  }
327
328  X86_64Assembler* GetAssembler() OVERRIDE {
329    return &assembler_;
330  }
331
332  const X86_64Assembler& GetAssembler() const OVERRIDE {
333    return assembler_;
334  }
335
336  ParallelMoveResolverX86_64* GetMoveResolver() OVERRIDE {
337    return &move_resolver_;
338  }
339
340  uintptr_t GetAddressOf(HBasicBlock* block) const OVERRIDE {
341    return GetLabelOf(block)->Position();
342  }
343
344  Location GetStackLocation(HLoadLocal* load) const OVERRIDE;
345
346  void SetupBlockedRegisters(bool is_baseline) const OVERRIDE;
347  Location AllocateFreeRegister(Primitive::Type type) const OVERRIDE;
348  void DumpCoreRegister(std::ostream& stream, int reg) const OVERRIDE;
349  void DumpFloatingPointRegister(std::ostream& stream, int reg) const OVERRIDE;
350  void Finalize(CodeAllocator* allocator) OVERRIDE;
351
352  InstructionSet GetInstructionSet() const OVERRIDE {
353    return InstructionSet::kX86_64;
354  }
355
356  // Emit a write barrier.
357  void MarkGCCard(CpuRegister temp,
358                  CpuRegister card,
359                  CpuRegister object,
360                  CpuRegister value,
361                  bool value_can_be_null);
362
363  void GenerateMemoryBarrier(MemBarrierKind kind);
364
365  // Helper method to move a value between two locations.
366  void Move(Location destination, Location source);
367
368  Label* GetLabelOf(HBasicBlock* block) const {
369    return CommonGetLabelOf<Label>(block_labels_, block);
370  }
371
372  void Initialize() OVERRIDE {
373    block_labels_ = CommonInitializeLabels<Label>();
374  }
375
376  bool NeedsTwoRegisters(Primitive::Type type ATTRIBUTE_UNUSED) const OVERRIDE {
377    return false;
378  }
379
380  // Check if the desired_dispatch_info is supported. If it is, return it,
381  // otherwise return a fall-back info that should be used instead.
382  HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch(
383      const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info,
384      MethodReference target_method) OVERRIDE;
385
386  void GenerateStaticOrDirectCall(HInvokeStaticOrDirect* invoke, Location temp) OVERRIDE;
387  void GenerateVirtualCall(HInvokeVirtual* invoke, Location temp) OVERRIDE;
388
389  void MoveFromReturnRegister(Location trg, Primitive::Type type) OVERRIDE;
390
391  void EmitLinkerPatches(ArenaVector<LinkerPatch>* linker_patches) OVERRIDE;
392
393  const X86_64InstructionSetFeatures& GetInstructionSetFeatures() const {
394    return isa_features_;
395  }
396
397  // Fast path implementation of ReadBarrier::Barrier for a heap
398  // reference field load when Baker's read barriers are used.
399  void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction,
400                                             Location out,
401                                             CpuRegister obj,
402                                             uint32_t offset,
403                                             Location temp,
404                                             bool needs_null_check);
405  // Fast path implementation of ReadBarrier::Barrier for a heap
406  // reference array load when Baker's read barriers are used.
407  void GenerateArrayLoadWithBakerReadBarrier(HInstruction* instruction,
408                                             Location out,
409                                             CpuRegister obj,
410                                             uint32_t data_offset,
411                                             Location index,
412                                             Location temp,
413                                             bool needs_null_check);
414
415  // Generate a read barrier for a heap reference within `instruction`
416  // using a slow path.
417  //
418  // A read barrier for an object reference read from the heap is
419  // implemented as a call to the artReadBarrierSlow runtime entry
420  // point, which is passed the values in locations `ref`, `obj`, and
421  // `offset`:
422  //
423  //   mirror::Object* artReadBarrierSlow(mirror::Object* ref,
424  //                                      mirror::Object* obj,
425  //                                      uint32_t offset);
426  //
427  // The `out` location contains the value returned by
428  // artReadBarrierSlow.
429  //
430  // When `index` provided (i.e., when it is different from
431  // Location::NoLocation()), the offset value passed to
432  // artReadBarrierSlow is adjusted to take `index` into account.
433  void GenerateReadBarrierSlow(HInstruction* instruction,
434                               Location out,
435                               Location ref,
436                               Location obj,
437                               uint32_t offset,
438                               Location index = Location::NoLocation());
439
440  // If read barriers are enabled, generate a read barrier for a heap
441  // reference using a slow path. If heap poisoning is enabled, also
442  // unpoison the reference in `out`.
443  void MaybeGenerateReadBarrierSlow(HInstruction* instruction,
444                                    Location out,
445                                    Location ref,
446                                    Location obj,
447                                    uint32_t offset,
448                                    Location index = Location::NoLocation());
449
450  // Generate a read barrier for a GC root within `instruction` using
451  // a slow path.
452  //
453  // A read barrier for an object reference GC root is implemented as
454  // a call to the artReadBarrierForRootSlow runtime entry point,
455  // which is passed the value in location `root`:
456  //
457  //   mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root);
458  //
459  // The `out` location contains the value returned by
460  // artReadBarrierForRootSlow.
461  void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root);
462
463  int ConstantAreaStart() const {
464    return constant_area_start_;
465  }
466
467  Address LiteralDoubleAddress(double v);
468  Address LiteralFloatAddress(float v);
469  Address LiteralInt32Address(int32_t v);
470  Address LiteralInt64Address(int64_t v);
471
472  // Load a 64 bit value into a register in the most efficient manner.
473  void Load64BitValue(CpuRegister dest, int64_t value);
474  Address LiteralCaseTable(HPackedSwitch* switch_instr);
475
476  // Store a 64 bit value into a DoubleStackSlot in the most efficient manner.
477  void Store64BitValueToStack(Location dest, int64_t value);
478
479  // Assign a 64 bit constant to an address.
480  void MoveInt64ToAddress(const Address& addr_low,
481                          const Address& addr_high,
482                          int64_t v,
483                          HInstruction* instruction);
484
485  // Ensure that prior stores complete to memory before subsequent loads.
486  // The locked add implementation will avoid serializing device memory, but will
487  // touch (but not change) the top of the stack. The locked add should not be used for
488  // ordering non-temporal stores.
489  void MemoryFence(bool force_mfence = false) {
490    if (!force_mfence && isa_features_.PrefersLockedAddSynchronization()) {
491      assembler_.lock()->addl(Address(CpuRegister(RSP), 0), Immediate(0));
492    } else {
493      assembler_.mfence();
494    }
495  }
496
497 private:
498  // Factored implementation of GenerateFieldLoadWithBakerReadBarrier
499  // and GenerateArrayLoadWithBakerReadBarrier.
500  void GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction,
501                                                 Location ref,
502                                                 CpuRegister obj,
503                                                 const Address& src,
504                                                 Location temp,
505                                                 bool needs_null_check);
506
507  struct PcRelativeDexCacheAccessInfo {
508    PcRelativeDexCacheAccessInfo(const DexFile& dex_file, uint32_t element_off)
509        : target_dex_file(dex_file), element_offset(element_off), label() { }
510
511    const DexFile& target_dex_file;
512    uint32_t element_offset;
513    Label label;
514  };
515
516  // Labels for each block that will be compiled.
517  Label* block_labels_;  // Indexed by block id.
518  Label frame_entry_label_;
519  LocationsBuilderX86_64 location_builder_;
520  InstructionCodeGeneratorX86_64 instruction_visitor_;
521  ParallelMoveResolverX86_64 move_resolver_;
522  X86_64Assembler assembler_;
523  const X86_64InstructionSetFeatures& isa_features_;
524
525  // Offset to the start of the constant area in the assembled code.
526  // Used for fixups to the constant area.
527  int constant_area_start_;
528
529  // Method patch info. Using ArenaDeque<> which retains element addresses on push/emplace_back().
530  ArenaDeque<MethodPatchInfo<Label>> method_patches_;
531  ArenaDeque<MethodPatchInfo<Label>> relative_call_patches_;
532  // PC-relative DexCache access info.
533  ArenaDeque<PcRelativeDexCacheAccessInfo> pc_relative_dex_cache_patches_;
534
535  // When we don't know the proper offset for the value, we use kDummy32BitOffset.
536  // We will fix this up in the linker later to have the right value.
537  static constexpr int32_t kDummy32BitOffset = 256;
538
539  // Fixups for jump tables need to be handled specially.
540  ArenaVector<JumpTableRIPFixup*> fixups_to_jump_tables_;
541
542  DISALLOW_COPY_AND_ASSIGN(CodeGeneratorX86_64);
543};
544
545}  // namespace x86_64
546}  // namespace art
547
548#endif  // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_X86_64_H_
549