assembler_x86.h revision 13735955f39b3b304c37d2b2840663c131262c18 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
18#define ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
19
20#include <vector>
21#include "base/macros.h"
22#include "constants_x86.h"
23#include "globals.h"
24#include "managed_register_x86.h"
25#include "offsets.h"
26#include "utils/assembler.h"
27#include "utils.h"
28
29namespace art {
30namespace x86 {
31
32class Immediate {
33 public:
34  explicit Immediate(int32_t value) : value_(value) {}
35
36  int32_t value() const { return value_; }
37
38  bool is_int8() const { return IsInt(8, value_); }
39  bool is_uint8() const { return IsUint(8, value_); }
40  bool is_int16() const { return IsInt(16, value_); }
41  bool is_uint16() const { return IsUint(16, value_); }
42
43 private:
44  const int32_t value_;
45
46  DISALLOW_COPY_AND_ASSIGN(Immediate);
47};
48
49
50class Operand {
51 public:
52  uint8_t mod() const {
53    return (encoding_at(0) >> 6) & 3;
54  }
55
56  Register rm() const {
57    return static_cast<Register>(encoding_at(0) & 7);
58  }
59
60  ScaleFactor scale() const {
61    return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
62  }
63
64  Register index() const {
65    return static_cast<Register>((encoding_at(1) >> 3) & 7);
66  }
67
68  Register base() const {
69    return static_cast<Register>(encoding_at(1) & 7);
70  }
71
72  int8_t disp8() const {
73    CHECK_GE(length_, 2);
74    return static_cast<int8_t>(encoding_[length_ - 1]);
75  }
76
77  int32_t disp32() const {
78    CHECK_GE(length_, 5);
79    int32_t value;
80    memcpy(&value, &encoding_[length_ - 4], sizeof(value));
81    return value;
82  }
83
84  bool IsRegister(Register reg) const {
85    return ((encoding_[0] & 0xF8) == 0xC0)  // Addressing mode is register only.
86        && ((encoding_[0] & 0x07) == reg);  // Register codes match.
87  }
88
89 protected:
90  // Operand can be sub classed (e.g: Address).
91  Operand() : length_(0) { }
92
93  void SetModRM(int mod, Register rm) {
94    CHECK_EQ(mod & ~3, 0);
95    encoding_[0] = (mod << 6) | rm;
96    length_ = 1;
97  }
98
99  void SetSIB(ScaleFactor scale, Register index, Register base) {
100    CHECK_EQ(length_, 1);
101    CHECK_EQ(scale & ~3, 0);
102    encoding_[1] = (scale << 6) | (index << 3) | base;
103    length_ = 2;
104  }
105
106  void SetDisp8(int8_t disp) {
107    CHECK(length_ == 1 || length_ == 2);
108    encoding_[length_++] = static_cast<uint8_t>(disp);
109  }
110
111  void SetDisp32(int32_t disp) {
112    CHECK(length_ == 1 || length_ == 2);
113    int disp_size = sizeof(disp);
114    memmove(&encoding_[length_], &disp, disp_size);
115    length_ += disp_size;
116  }
117
118 private:
119  uint8_t length_;
120  uint8_t encoding_[6];
121
122  explicit Operand(Register reg) { SetModRM(3, reg); }
123
124  // Get the operand encoding byte at the given index.
125  uint8_t encoding_at(int index) const {
126    CHECK_GE(index, 0);
127    CHECK_LT(index, length_);
128    return encoding_[index];
129  }
130
131  friend class X86Assembler;
132
133  DISALLOW_COPY_AND_ASSIGN(Operand);
134};
135
136
137class Address : public Operand {
138 public:
139  Address(Register base, int32_t disp) {
140    Init(base, disp);
141  }
142
143  Address(Register base, Offset disp) {
144    Init(base, disp.Int32Value());
145  }
146
147  Address(Register base, FrameOffset disp) {
148    CHECK_EQ(base, ESP);
149    Init(ESP, disp.Int32Value());
150  }
151
152  Address(Register base, MemberOffset disp) {
153    Init(base, disp.Int32Value());
154  }
155
156  void Init(Register base, int32_t disp) {
157    if (disp == 0 && base != EBP) {
158      SetModRM(0, base);
159      if (base == ESP) SetSIB(TIMES_1, ESP, base);
160    } else if (disp >= -128 && disp <= 127) {
161      SetModRM(1, base);
162      if (base == ESP) SetSIB(TIMES_1, ESP, base);
163      SetDisp8(disp);
164    } else {
165      SetModRM(2, base);
166      if (base == ESP) SetSIB(TIMES_1, ESP, base);
167      SetDisp32(disp);
168    }
169  }
170
171
172  Address(Register index, ScaleFactor scale, int32_t disp) {
173    CHECK_NE(index, ESP);  // Illegal addressing mode.
174    SetModRM(0, ESP);
175    SetSIB(scale, index, EBP);
176    SetDisp32(disp);
177  }
178
179  Address(Register base, Register index, ScaleFactor scale, int32_t disp) {
180    CHECK_NE(index, ESP);  // Illegal addressing mode.
181    if (disp == 0 && base != EBP) {
182      SetModRM(0, ESP);
183      SetSIB(scale, index, base);
184    } else if (disp >= -128 && disp <= 127) {
185      SetModRM(1, ESP);
186      SetSIB(scale, index, base);
187      SetDisp8(disp);
188    } else {
189      SetModRM(2, ESP);
190      SetSIB(scale, index, base);
191      SetDisp32(disp);
192    }
193  }
194
195  static Address Absolute(uintptr_t addr) {
196    Address result;
197    result.SetModRM(0, EBP);
198    result.SetDisp32(addr);
199    return result;
200  }
201
202  static Address Absolute(ThreadOffset<4> addr) {
203    return Absolute(addr.Int32Value());
204  }
205
206 private:
207  Address() {}
208
209  DISALLOW_COPY_AND_ASSIGN(Address);
210};
211
212
213class X86Assembler FINAL : public Assembler {
214 public:
215  explicit X86Assembler() {}
216  virtual ~X86Assembler() {}
217
218  /*
219   * Emit Machine Instructions.
220   */
221  void call(Register reg);
222  void call(const Address& address);
223  void call(Label* label);
224  void call(const ExternalLabel& label);
225
226  void pushl(Register reg);
227  void pushl(const Address& address);
228  void pushl(const Immediate& imm);
229
230  void popl(Register reg);
231  void popl(const Address& address);
232
233  void movl(Register dst, const Immediate& src);
234  void movl(Register dst, Register src);
235
236  void movl(Register dst, const Address& src);
237  void movl(const Address& dst, Register src);
238  void movl(const Address& dst, const Immediate& imm);
239  void movl(const Address& dst, Label* lbl);
240
241  void movzxb(Register dst, ByteRegister src);
242  void movzxb(Register dst, const Address& src);
243  void movsxb(Register dst, ByteRegister src);
244  void movsxb(Register dst, const Address& src);
245  void movb(Register dst, const Address& src);
246  void movb(const Address& dst, ByteRegister src);
247  void movb(const Address& dst, const Immediate& imm);
248
249  void movzxw(Register dst, Register src);
250  void movzxw(Register dst, const Address& src);
251  void movsxw(Register dst, Register src);
252  void movsxw(Register dst, const Address& src);
253  void movw(Register dst, const Address& src);
254  void movw(const Address& dst, Register src);
255  void movw(const Address& dst, const Immediate& imm);
256
257  void leal(Register dst, const Address& src);
258
259  void cmovl(Condition condition, Register dst, Register src);
260
261  void setb(Condition condition, Register dst);
262
263  void movaps(XmmRegister dst, XmmRegister src);
264  void movss(XmmRegister dst, const Address& src);
265  void movss(const Address& dst, XmmRegister src);
266  void movss(XmmRegister dst, XmmRegister src);
267
268  void movd(XmmRegister dst, Register src);
269  void movd(Register dst, XmmRegister src);
270
271  void addss(XmmRegister dst, XmmRegister src);
272  void addss(XmmRegister dst, const Address& src);
273  void subss(XmmRegister dst, XmmRegister src);
274  void subss(XmmRegister dst, const Address& src);
275  void mulss(XmmRegister dst, XmmRegister src);
276  void mulss(XmmRegister dst, const Address& src);
277  void divss(XmmRegister dst, XmmRegister src);
278  void divss(XmmRegister dst, const Address& src);
279
280  void movsd(XmmRegister dst, const Address& src);
281  void movsd(const Address& dst, XmmRegister src);
282  void movsd(XmmRegister dst, XmmRegister src);
283
284  void addsd(XmmRegister dst, XmmRegister src);
285  void addsd(XmmRegister dst, const Address& src);
286  void subsd(XmmRegister dst, XmmRegister src);
287  void subsd(XmmRegister dst, const Address& src);
288  void mulsd(XmmRegister dst, XmmRegister src);
289  void mulsd(XmmRegister dst, const Address& src);
290  void divsd(XmmRegister dst, XmmRegister src);
291  void divsd(XmmRegister dst, const Address& src);
292
293  void cvtsi2ss(XmmRegister dst, Register src);
294  void cvtsi2sd(XmmRegister dst, Register src);
295
296  void cvtss2si(Register dst, XmmRegister src);
297  void cvtss2sd(XmmRegister dst, XmmRegister src);
298
299  void cvtsd2si(Register dst, XmmRegister src);
300  void cvtsd2ss(XmmRegister dst, XmmRegister src);
301
302  void cvttss2si(Register dst, XmmRegister src);
303  void cvttsd2si(Register dst, XmmRegister src);
304
305  void cvtdq2pd(XmmRegister dst, XmmRegister src);
306
307  void comiss(XmmRegister a, XmmRegister b);
308  void comisd(XmmRegister a, XmmRegister b);
309
310  void sqrtsd(XmmRegister dst, XmmRegister src);
311  void sqrtss(XmmRegister dst, XmmRegister src);
312
313  void xorpd(XmmRegister dst, const Address& src);
314  void xorpd(XmmRegister dst, XmmRegister src);
315  void xorps(XmmRegister dst, const Address& src);
316  void xorps(XmmRegister dst, XmmRegister src);
317
318  void andpd(XmmRegister dst, const Address& src);
319
320  void flds(const Address& src);
321  void fstps(const Address& dst);
322
323  void fldl(const Address& src);
324  void fstpl(const Address& dst);
325
326  void fnstcw(const Address& dst);
327  void fldcw(const Address& src);
328
329  void fistpl(const Address& dst);
330  void fistps(const Address& dst);
331  void fildl(const Address& src);
332
333  void fincstp();
334  void ffree(const Immediate& index);
335
336  void fsin();
337  void fcos();
338  void fptan();
339
340  void xchgl(Register dst, Register src);
341  void xchgl(Register reg, const Address& address);
342
343  void cmpw(const Address& address, const Immediate& imm);
344
345  void cmpl(Register reg, const Immediate& imm);
346  void cmpl(Register reg0, Register reg1);
347  void cmpl(Register reg, const Address& address);
348
349  void cmpl(const Address& address, Register reg);
350  void cmpl(const Address& address, const Immediate& imm);
351
352  void testl(Register reg1, Register reg2);
353  void testl(Register reg, const Immediate& imm);
354  void testl(Register reg1, const Address& address);
355
356  void andl(Register dst, const Immediate& imm);
357  void andl(Register dst, Register src);
358
359  void orl(Register dst, const Immediate& imm);
360  void orl(Register dst, Register src);
361
362  void xorl(Register dst, Register src);
363  void xorl(Register dst, const Immediate& imm);
364
365  void addl(Register dst, Register src);
366  void addl(Register reg, const Immediate& imm);
367  void addl(Register reg, const Address& address);
368
369  void addl(const Address& address, Register reg);
370  void addl(const Address& address, const Immediate& imm);
371
372  void adcl(Register dst, Register src);
373  void adcl(Register reg, const Immediate& imm);
374  void adcl(Register dst, const Address& address);
375
376  void subl(Register dst, Register src);
377  void subl(Register reg, const Immediate& imm);
378  void subl(Register reg, const Address& address);
379
380  void cdq();
381
382  void idivl(Register reg);
383
384  void imull(Register dst, Register src);
385  void imull(Register reg, const Immediate& imm);
386  void imull(Register reg, const Address& address);
387
388  void imull(Register reg);
389  void imull(const Address& address);
390
391  void mull(Register reg);
392  void mull(const Address& address);
393
394  void sbbl(Register dst, Register src);
395  void sbbl(Register reg, const Immediate& imm);
396  void sbbl(Register reg, const Address& address);
397
398  void incl(Register reg);
399  void incl(const Address& address);
400
401  void decl(Register reg);
402  void decl(const Address& address);
403
404  void shll(Register reg, const Immediate& imm);
405  void shll(Register operand, Register shifter);
406  void shrl(Register reg, const Immediate& imm);
407  void shrl(Register operand, Register shifter);
408  void sarl(Register reg, const Immediate& imm);
409  void sarl(Register operand, Register shifter);
410  void shld(Register dst, Register src);
411
412  void negl(Register reg);
413  void notl(Register reg);
414
415  void enter(const Immediate& imm);
416  void leave();
417
418  void ret();
419  void ret(const Immediate& imm);
420
421  void nop();
422  void int3();
423  void hlt();
424
425  void j(Condition condition, Label* label);
426
427  void jmp(Register reg);
428  void jmp(const Address& address);
429  void jmp(Label* label);
430
431  X86Assembler* lock();
432  void cmpxchgl(const Address& address, Register reg);
433
434  void mfence();
435
436  X86Assembler* fs();
437  X86Assembler* gs();
438
439  //
440  // Macros for High-level operations.
441  //
442
443  void AddImmediate(Register reg, const Immediate& imm);
444
445  void LoadDoubleConstant(XmmRegister dst, double value);
446
447  void DoubleNegate(XmmRegister d);
448  void FloatNegate(XmmRegister f);
449
450  void DoubleAbs(XmmRegister reg);
451
452  void LockCmpxchgl(const Address& address, Register reg) {
453    lock()->cmpxchgl(address, reg);
454  }
455
456  //
457  // Misc. functionality
458  //
459  int PreferredLoopAlignment() { return 16; }
460  void Align(int alignment, int offset);
461  void Bind(Label* label);
462
463  //
464  // Overridden common assembler high-level functionality
465  //
466
467  // Emit code that will create an activation on the stack
468  void BuildFrame(size_t frame_size, ManagedRegister method_reg,
469                  const std::vector<ManagedRegister>& callee_save_regs,
470                  const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
471
472  // Emit code that will remove an activation from the stack
473  void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
474      OVERRIDE;
475
476  void IncreaseFrameSize(size_t adjust) OVERRIDE;
477  void DecreaseFrameSize(size_t adjust) OVERRIDE;
478
479  // Store routines
480  void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
481  void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
482  void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
483
484  void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
485
486  void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch)
487      OVERRIDE;
488
489  void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
490                                  ManagedRegister scratch) OVERRIDE;
491
492  void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE;
493
494  void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
495                     ManagedRegister scratch) OVERRIDE;
496
497  // Load routines
498  void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
499
500  void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) OVERRIDE;
501
502  void LoadRef(ManagedRegister dest, FrameOffset  src) OVERRIDE;
503
504  void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
505
506  void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
507
508  void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) OVERRIDE;
509
510  // Copying routines
511  void Move(ManagedRegister dest, ManagedRegister src, size_t size) OVERRIDE;
512
513  void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
514                              ManagedRegister scratch) OVERRIDE;
515
516  void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
517      OVERRIDE;
518
519  void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
520
521  void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
522
523  void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
524            size_t size) OVERRIDE;
525
526  void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
527            size_t size) OVERRIDE;
528
529  void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
530            size_t size) OVERRIDE;
531
532  void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
533            ManagedRegister scratch, size_t size) OVERRIDE;
534
535  void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
536            ManagedRegister scratch, size_t size) OVERRIDE;
537
538  void MemoryBarrier(ManagedRegister) OVERRIDE;
539
540  // Sign extension
541  void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
542
543  // Zero extension
544  void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
545
546  // Exploit fast access in managed code to Thread::Current()
547  void GetCurrentThread(ManagedRegister tr) OVERRIDE;
548  void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
549
550  // Set up out_reg to hold a Object** into the handle scope, or to be NULL if the
551  // value is null and null_allowed. in_reg holds a possibly stale reference
552  // that can be used to avoid loading the handle scope entry to see if the value is
553  // NULL.
554  void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, ManagedRegister in_reg,
555                       bool null_allowed) OVERRIDE;
556
557  // Set up out_off to hold a Object** into the handle scope, or to be NULL if the
558  // value is null and null_allowed.
559  void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, ManagedRegister scratch,
560                       bool null_allowed) OVERRIDE;
561
562  // src holds a handle scope entry (Object**) load this into dst
563  void LoadReferenceFromHandleScope(ManagedRegister dst, ManagedRegister src) OVERRIDE;
564
565  // Heap::VerifyObject on src. In some cases (such as a reference to this) we
566  // know that src may not be null.
567  void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
568  void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
569
570  // Call to address held at [base+offset]
571  void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
572  void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
573  void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) OVERRIDE;
574
575  // Generate code to check if Thread::Current()->exception_ is non-null
576  // and branch to a ExceptionSlowPath if it is.
577  void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
578
579  void InitializeFrameDescriptionEntry() OVERRIDE;
580  void FinalizeFrameDescriptionEntry() OVERRIDE;
581  std::vector<uint8_t>* GetFrameDescriptionEntry() OVERRIDE {
582    return &cfi_info_;
583  }
584
585 private:
586  inline void EmitUint8(uint8_t value);
587  inline void EmitInt32(int32_t value);
588  inline void EmitRegisterOperand(int rm, int reg);
589  inline void EmitXmmRegisterOperand(int rm, XmmRegister reg);
590  inline void EmitFixup(AssemblerFixup* fixup);
591  inline void EmitOperandSizeOverride();
592
593  void EmitOperand(int rm, const Operand& operand);
594  void EmitImmediate(const Immediate& imm);
595  void EmitComplex(int rm, const Operand& operand, const Immediate& immediate);
596  void EmitLabel(Label* label, int instruction_size);
597  void EmitLabelLink(Label* label);
598  void EmitNearLabelLink(Label* label);
599
600  void EmitGenericShift(int rm, Register reg, const Immediate& imm);
601  void EmitGenericShift(int rm, Register operand, Register shifter);
602
603  std::vector<uint8_t> cfi_info_;
604  uint32_t cfi_cfa_offset_, cfi_pc_;
605
606  DISALLOW_COPY_AND_ASSIGN(X86Assembler);
607};
608
609inline void X86Assembler::EmitUint8(uint8_t value) {
610  buffer_.Emit<uint8_t>(value);
611}
612
613inline void X86Assembler::EmitInt32(int32_t value) {
614  buffer_.Emit<int32_t>(value);
615}
616
617inline void X86Assembler::EmitRegisterOperand(int rm, int reg) {
618  CHECK_GE(rm, 0);
619  CHECK_LT(rm, 8);
620  buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
621}
622
623inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
624  EmitRegisterOperand(rm, static_cast<Register>(reg));
625}
626
627inline void X86Assembler::EmitFixup(AssemblerFixup* fixup) {
628  buffer_.EmitFixup(fixup);
629}
630
631inline void X86Assembler::EmitOperandSizeOverride() {
632  EmitUint8(0x66);
633}
634
635// Slowpath entered when Thread::Current()->_exception is non-null
636class X86ExceptionSlowPath FINAL : public SlowPath {
637 public:
638  explicit X86ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
639  virtual void Emit(Assembler *sp_asm) OVERRIDE;
640 private:
641  const size_t stack_adjust_;
642};
643
644}  // namespace x86
645}  // namespace art
646
647#endif  // ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
648