assembler_x86_64.h revision 705664321a5cc1418255172f92d7d7195cf60a7b 
1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
18#define ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
19
20#include <vector>
21#include "base/macros.h"
22#include "constants_x86_64.h"
23#include "globals.h"
24#include "managed_register_x86_64.h"
25#include "offsets.h"
26#include "utils/assembler.h"
27#include "utils.h"
28
29namespace art {
30namespace x86_64 {
31
32// Encodes an immediate value for operands.
33//
34// Note: Immediates can be 64b on x86-64 for certain instructions, but are often restricted
35// to 32b.
36//
37// Note: As we support cross-compilation, the value type must be int64_t. Please be aware of
38// conversion rules in expressions regarding negation, especially size_t on 32b.
39class Immediate : public ValueObject {
40 public:
41  explicit Immediate(int64_t value) : value_(value) {}
42
43  int64_t value() const { return value_; }
44
45  bool is_int8() const { return IsInt(8, value_); }
46  bool is_uint8() const { return IsUint(8, value_); }
47  bool is_int16() const { return IsInt(16, value_); }
48  bool is_uint16() const { return IsUint(16, value_); }
49  bool is_int32() const {
50    // This does not work on 32b machines: return IsInt(32, value_);
51    int64_t limit = static_cast<int64_t>(1) << 31;
52    return (-limit <= value_) && (value_ < limit);
53  }
54
55 private:
56  const int64_t value_;
57};
58
59
60class Operand : public ValueObject {
61 public:
62  uint8_t mod() const {
63    return (encoding_at(0) >> 6) & 3;
64  }
65
66  Register rm() const {
67    return static_cast<Register>(encoding_at(0) & 7);
68  }
69
70  ScaleFactor scale() const {
71    return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
72  }
73
74  Register index() const {
75    return static_cast<Register>((encoding_at(1) >> 3) & 7);
76  }
77
78  Register base() const {
79    return static_cast<Register>(encoding_at(1) & 7);
80  }
81
82  uint8_t rex() const {
83    return rex_;
84  }
85
86  int8_t disp8() const {
87    CHECK_GE(length_, 2);
88    return static_cast<int8_t>(encoding_[length_ - 1]);
89  }
90
91  int32_t disp32() const {
92    CHECK_GE(length_, 5);
93    int32_t value;
94    memcpy(&value, &encoding_[length_ - 4], sizeof(value));
95    return value;
96  }
97
98  bool IsRegister(CpuRegister reg) const {
99    return ((encoding_[0] & 0xF8) == 0xC0)  // Addressing mode is register only.
100        && ((encoding_[0] & 0x07) == reg.LowBits())  // Register codes match.
101        && (reg.NeedsRex() == ((rex_ & 1) != 0));  // REX.000B bits match.
102  }
103
104 protected:
105  // Operand can be sub classed (e.g: Address).
106  Operand() : rex_(0), length_(0) { }
107
108  void SetModRM(uint8_t mod, CpuRegister rm) {
109    CHECK_EQ(mod & ~3, 0);
110    if (rm.NeedsRex()) {
111      rex_ |= 0x41;  // REX.000B
112    }
113    encoding_[0] = (mod << 6) | rm.LowBits();
114    length_ = 1;
115  }
116
117  void SetSIB(ScaleFactor scale, CpuRegister index, CpuRegister base) {
118    CHECK_EQ(length_, 1);
119    CHECK_EQ(scale & ~3, 0);
120    if (base.NeedsRex()) {
121      rex_ |= 0x41;  // REX.000B
122    }
123    if (index.NeedsRex()) {
124      rex_ |= 0x42;  // REX.00X0
125    }
126    encoding_[1] = (scale << 6) | (static_cast<uint8_t>(index.LowBits()) << 3) |
127        static_cast<uint8_t>(base.LowBits());
128    length_ = 2;
129  }
130
131  void SetDisp8(int8_t disp) {
132    CHECK(length_ == 1 || length_ == 2);
133    encoding_[length_++] = static_cast<uint8_t>(disp);
134  }
135
136  void SetDisp32(int32_t disp) {
137    CHECK(length_ == 1 || length_ == 2);
138    int disp_size = sizeof(disp);
139    memmove(&encoding_[length_], &disp, disp_size);
140    length_ += disp_size;
141  }
142
143 private:
144  uint8_t rex_;
145  uint8_t length_;
146  uint8_t encoding_[6];
147
148  explicit Operand(CpuRegister reg) : rex_(0), length_(0) { SetModRM(3, reg); }
149
150  // Get the operand encoding byte at the given index.
151  uint8_t encoding_at(int index) const {
152    CHECK_GE(index, 0);
153    CHECK_LT(index, length_);
154    return encoding_[index];
155  }
156
157  friend class X86_64Assembler;
158};
159
160
161class Address : public Operand {
162 public:
163  Address(CpuRegister base, int32_t disp) {
164    Init(base, disp);
165  }
166
167  Address(CpuRegister base, Offset disp) {
168    Init(base, disp.Int32Value());
169  }
170
171  Address(CpuRegister base, FrameOffset disp) {
172    CHECK_EQ(base.AsRegister(), RSP);
173    Init(CpuRegister(RSP), disp.Int32Value());
174  }
175
176  Address(CpuRegister base, MemberOffset disp) {
177    Init(base, disp.Int32Value());
178  }
179
180  void Init(CpuRegister base, int32_t disp) {
181    if (disp == 0 && base.AsRegister() != RBP) {
182      SetModRM(0, base);
183      if (base.AsRegister() == RSP) {
184        SetSIB(TIMES_1, CpuRegister(RSP), base);
185      }
186    } else if (disp >= -128 && disp <= 127) {
187      SetModRM(1, base);
188      if (base.AsRegister() == RSP) {
189        SetSIB(TIMES_1, CpuRegister(RSP), base);
190      }
191      SetDisp8(disp);
192    } else {
193      SetModRM(2, base);
194      if (base.AsRegister() == RSP) {
195        SetSIB(TIMES_1, CpuRegister(RSP), base);
196      }
197      SetDisp32(disp);
198    }
199  }
200
201
202  Address(CpuRegister index, ScaleFactor scale, int32_t disp) {
203    CHECK_NE(index.AsRegister(), RSP);  // Illegal addressing mode.
204    SetModRM(0, CpuRegister(RSP));
205    SetSIB(scale, index, CpuRegister(RBP));
206    SetDisp32(disp);
207  }
208
209  Address(CpuRegister base, CpuRegister index, ScaleFactor scale, int32_t disp) {
210    CHECK_NE(index.AsRegister(), RSP);  // Illegal addressing mode.
211    if (disp == 0 && base.AsRegister() != RBP) {
212      SetModRM(0, CpuRegister(RSP));
213      SetSIB(scale, index, base);
214    } else if (disp >= -128 && disp <= 127) {
215      SetModRM(1, CpuRegister(RSP));
216      SetSIB(scale, index, base);
217      SetDisp8(disp);
218    } else {
219      SetModRM(2, CpuRegister(RSP));
220      SetSIB(scale, index, base);
221      SetDisp32(disp);
222    }
223  }
224
225  // If no_rip is true then the Absolute address isn't RIP relative.
226  static Address Absolute(uintptr_t addr, bool no_rip = false) {
227    Address result;
228    if (no_rip) {
229      result.SetModRM(0, CpuRegister(RSP));
230      result.SetSIB(TIMES_1, CpuRegister(RSP), CpuRegister(RBP));
231      result.SetDisp32(addr);
232    } else {
233      result.SetModRM(0, CpuRegister(RBP));
234      result.SetDisp32(addr);
235    }
236    return result;
237  }
238
239  // If no_rip is true then the Absolute address isn't RIP relative.
240  static Address Absolute(ThreadOffset<8> addr, bool no_rip = false) {
241    return Absolute(addr.Int32Value(), no_rip);
242  }
243
244 private:
245  Address() {}
246};
247
248
249class X86_64Assembler FINAL : public Assembler {
250 public:
251  X86_64Assembler() : cfi_cfa_offset_(0), cfi_pc_(0) {}
252  virtual ~X86_64Assembler() {}
253
254  /*
255   * Emit Machine Instructions.
256   */
257  void call(CpuRegister reg);
258  void call(const Address& address);
259  void call(Label* label);
260
261  void pushq(CpuRegister reg);
262  void pushq(const Address& address);
263  void pushq(const Immediate& imm);
264
265  void popq(CpuRegister reg);
266  void popq(const Address& address);
267
268  void movq(CpuRegister dst, const Immediate& src);
269  void movl(CpuRegister dst, const Immediate& src);
270  void movq(CpuRegister dst, CpuRegister src);
271  void movl(CpuRegister dst, CpuRegister src);
272
273  void movq(CpuRegister dst, const Address& src);
274  void movl(CpuRegister dst, const Address& src);
275  void movq(const Address& dst, CpuRegister src);
276  void movl(const Address& dst, CpuRegister src);
277  void movl(const Address& dst, const Immediate& imm);
278
279  void movzxb(CpuRegister dst, CpuRegister src);
280  void movzxb(CpuRegister dst, const Address& src);
281  void movsxb(CpuRegister dst, CpuRegister src);
282  void movsxb(CpuRegister dst, const Address& src);
283  void movb(CpuRegister dst, const Address& src);
284  void movb(const Address& dst, CpuRegister src);
285  void movb(const Address& dst, const Immediate& imm);
286
287  void movzxw(CpuRegister dst, CpuRegister src);
288  void movzxw(CpuRegister dst, const Address& src);
289  void movsxw(CpuRegister dst, CpuRegister src);
290  void movsxw(CpuRegister dst, const Address& src);
291  void movw(CpuRegister dst, const Address& src);
292  void movw(const Address& dst, CpuRegister src);
293  void movw(const Address& dst, const Immediate& imm);
294
295  void leaq(CpuRegister dst, const Address& src);
296
297  void movaps(XmmRegister dst, XmmRegister src);
298
299  void movss(XmmRegister dst, const Address& src);
300  void movss(const Address& dst, XmmRegister src);
301  void movss(XmmRegister dst, XmmRegister src);
302
303  void movd(XmmRegister dst, CpuRegister src);
304  void movd(CpuRegister dst, XmmRegister src);
305
306  void addss(XmmRegister dst, XmmRegister src);
307  void addss(XmmRegister dst, const Address& src);
308  void subss(XmmRegister dst, XmmRegister src);
309  void subss(XmmRegister dst, const Address& src);
310  void mulss(XmmRegister dst, XmmRegister src);
311  void mulss(XmmRegister dst, const Address& src);
312  void divss(XmmRegister dst, XmmRegister src);
313  void divss(XmmRegister dst, const Address& src);
314
315  void movsd(XmmRegister dst, const Address& src);
316  void movsd(const Address& dst, XmmRegister src);
317  void movsd(XmmRegister dst, XmmRegister src);
318
319  void addsd(XmmRegister dst, XmmRegister src);
320  void addsd(XmmRegister dst, const Address& src);
321  void subsd(XmmRegister dst, XmmRegister src);
322  void subsd(XmmRegister dst, const Address& src);
323  void mulsd(XmmRegister dst, XmmRegister src);
324  void mulsd(XmmRegister dst, const Address& src);
325  void divsd(XmmRegister dst, XmmRegister src);
326  void divsd(XmmRegister dst, const Address& src);
327
328  void cvtsi2ss(XmmRegister dst, CpuRegister src);
329  void cvtsi2sd(XmmRegister dst, CpuRegister src);
330
331  void cvtss2si(CpuRegister dst, XmmRegister src);
332  void cvtss2sd(XmmRegister dst, XmmRegister src);
333
334  void cvtsd2si(CpuRegister dst, XmmRegister src);
335  void cvtsd2ss(XmmRegister dst, XmmRegister src);
336
337  void cvttss2si(CpuRegister dst, XmmRegister src);
338  void cvttsd2si(CpuRegister dst, XmmRegister src);
339
340  void cvtdq2pd(XmmRegister dst, XmmRegister src);
341
342  void comiss(XmmRegister a, XmmRegister b);
343  void comisd(XmmRegister a, XmmRegister b);
344
345  void sqrtsd(XmmRegister dst, XmmRegister src);
346  void sqrtss(XmmRegister dst, XmmRegister src);
347
348  void xorpd(XmmRegister dst, const Address& src);
349  void xorpd(XmmRegister dst, XmmRegister src);
350  void xorps(XmmRegister dst, const Address& src);
351  void xorps(XmmRegister dst, XmmRegister src);
352
353  void andpd(XmmRegister dst, const Address& src);
354
355  void flds(const Address& src);
356  void fstps(const Address& dst);
357
358  void fldl(const Address& src);
359  void fstpl(const Address& dst);
360
361  void fnstcw(const Address& dst);
362  void fldcw(const Address& src);
363
364  void fistpl(const Address& dst);
365  void fistps(const Address& dst);
366  void fildl(const Address& src);
367
368  void fincstp();
369  void ffree(const Immediate& index);
370
371  void fsin();
372  void fcos();
373  void fptan();
374
375  void xchgl(CpuRegister dst, CpuRegister src);
376  void xchgq(CpuRegister dst, CpuRegister src);
377  void xchgl(CpuRegister reg, const Address& address);
378
379  void cmpw(const Address& address, const Immediate& imm);
380
381  void cmpl(CpuRegister reg, const Immediate& imm);
382  void cmpl(CpuRegister reg0, CpuRegister reg1);
383  void cmpl(CpuRegister reg, const Address& address);
384  void cmpl(const Address& address, CpuRegister reg);
385  void cmpl(const Address& address, const Immediate& imm);
386
387  void cmpq(CpuRegister reg0, CpuRegister reg1);
388  void cmpq(CpuRegister reg0, const Immediate& imm);
389  void cmpq(CpuRegister reg0, const Address& address);
390
391  void testl(CpuRegister reg1, CpuRegister reg2);
392  void testl(CpuRegister reg, const Immediate& imm);
393
394  void testq(CpuRegister reg, const Address& address);
395
396  void andl(CpuRegister dst, const Immediate& imm);
397  void andl(CpuRegister dst, CpuRegister src);
398  void andq(CpuRegister dst, const Immediate& imm);
399
400  void orl(CpuRegister dst, const Immediate& imm);
401  void orl(CpuRegister dst, CpuRegister src);
402
403  void xorl(CpuRegister dst, CpuRegister src);
404  void xorq(CpuRegister dst, const Immediate& imm);
405  void xorq(CpuRegister dst, CpuRegister src);
406
407  void addl(CpuRegister dst, CpuRegister src);
408  void addl(CpuRegister reg, const Immediate& imm);
409  void addl(CpuRegister reg, const Address& address);
410  void addl(const Address& address, CpuRegister reg);
411  void addl(const Address& address, const Immediate& imm);
412
413  void addq(CpuRegister reg, const Immediate& imm);
414  void addq(CpuRegister dst, CpuRegister src);
415  void addq(CpuRegister dst, const Address& address);
416
417  void subl(CpuRegister dst, CpuRegister src);
418  void subl(CpuRegister reg, const Immediate& imm);
419  void subl(CpuRegister reg, const Address& address);
420
421  void subq(CpuRegister reg, const Immediate& imm);
422  void subq(CpuRegister dst, CpuRegister src);
423  void subq(CpuRegister dst, const Address& address);
424
425  void cdq();
426
427  void idivl(CpuRegister reg);
428
429  void imull(CpuRegister dst, CpuRegister src);
430  void imull(CpuRegister reg, const Immediate& imm);
431  void imull(CpuRegister reg, const Address& address);
432
433  void imulq(CpuRegister dst, CpuRegister src);
434  void imulq(CpuRegister reg, const Immediate& imm);
435  void imulq(CpuRegister reg, const Address& address);
436
437  void imull(CpuRegister reg);
438  void imull(const Address& address);
439
440  void mull(CpuRegister reg);
441  void mull(const Address& address);
442
443  void shll(CpuRegister reg, const Immediate& imm);
444  void shll(CpuRegister operand, CpuRegister shifter);
445  void shrl(CpuRegister reg, const Immediate& imm);
446  void shrl(CpuRegister operand, CpuRegister shifter);
447  void sarl(CpuRegister reg, const Immediate& imm);
448  void sarl(CpuRegister operand, CpuRegister shifter);
449
450  void shrq(CpuRegister reg, const Immediate& imm);
451
452  void negl(CpuRegister reg);
453  void negq(CpuRegister reg);
454
455  void notl(CpuRegister reg);
456  void notq(CpuRegister reg);
457
458  void enter(const Immediate& imm);
459  void leave();
460
461  void ret();
462  void ret(const Immediate& imm);
463
464  void nop();
465  void int3();
466  void hlt();
467
468  void j(Condition condition, Label* label);
469
470  void jmp(CpuRegister reg);
471  void jmp(const Address& address);
472  void jmp(Label* label);
473
474  X86_64Assembler* lock();
475  void cmpxchgl(const Address& address, CpuRegister reg);
476
477  void mfence();
478
479  X86_64Assembler* gs();
480
481  void setcc(Condition condition, CpuRegister dst);
482
483  //
484  // Macros for High-level operations.
485  //
486
487  void AddImmediate(CpuRegister reg, const Immediate& imm);
488
489  void LoadDoubleConstant(XmmRegister dst, double value);
490
491  void DoubleNegate(XmmRegister d);
492  void FloatNegate(XmmRegister f);
493
494  void DoubleAbs(XmmRegister reg);
495
496  void LockCmpxchgl(const Address& address, CpuRegister reg) {
497    lock()->cmpxchgl(address, reg);
498  }
499
500  //
501  // Misc. functionality
502  //
503  int PreferredLoopAlignment() { return 16; }
504  void Align(int alignment, int offset);
505  void Bind(Label* label);
506
507  //
508  // Overridden common assembler high-level functionality
509  //
510
511  // Emit code that will create an activation on the stack
512  void BuildFrame(size_t frame_size, ManagedRegister method_reg,
513                  const std::vector<ManagedRegister>& callee_save_regs,
514                  const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
515
516  // Emit code that will remove an activation from the stack
517  void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
518      OVERRIDE;
519
520  void IncreaseFrameSize(size_t adjust) OVERRIDE;
521  void DecreaseFrameSize(size_t adjust) OVERRIDE;
522
523  // Store routines
524  void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
525  void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
526  void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
527
528  void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
529
530  void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister scratch)
531      OVERRIDE;
532
533  void StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs,
534                                  ManagedRegister scratch) OVERRIDE;
535
536  void StoreStackPointerToThread64(ThreadOffset<8> thr_offs) OVERRIDE;
537
538  void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
539                     ManagedRegister scratch) OVERRIDE;
540
541  // Load routines
542  void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
543
544  void LoadFromThread64(ManagedRegister dest, ThreadOffset<8> src, size_t size) OVERRIDE;
545
546  void LoadRef(ManagedRegister dest, FrameOffset  src) OVERRIDE;
547
548  void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
549
550  void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
551
552  void LoadRawPtrFromThread64(ManagedRegister dest, ThreadOffset<8> offs) OVERRIDE;
553
554  // Copying routines
555  void Move(ManagedRegister dest, ManagedRegister src, size_t size);
556
557  void CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> thr_offs,
558                              ManagedRegister scratch) OVERRIDE;
559
560  void CopyRawPtrToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
561      OVERRIDE;
562
563  void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
564
565  void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
566
567  void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
568            size_t size) OVERRIDE;
569
570  void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
571            size_t size) OVERRIDE;
572
573  void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
574            size_t size) OVERRIDE;
575
576  void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
577            ManagedRegister scratch, size_t size) OVERRIDE;
578
579  void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
580            ManagedRegister scratch, size_t size) OVERRIDE;
581
582  void MemoryBarrier(ManagedRegister) OVERRIDE;
583
584  // Sign extension
585  void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
586
587  // Zero extension
588  void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
589
590  // Exploit fast access in managed code to Thread::Current()
591  void GetCurrentThread(ManagedRegister tr) OVERRIDE;
592  void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
593
594  // Set up out_reg to hold a Object** into the handle scope, or to be NULL if the
595  // value is null and null_allowed. in_reg holds a possibly stale reference
596  // that can be used to avoid loading the handle scope entry to see if the value is
597  // NULL.
598  void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, ManagedRegister in_reg,
599                       bool null_allowed) OVERRIDE;
600
601  // Set up out_off to hold a Object** into the handle scope, or to be NULL if the
602  // value is null and null_allowed.
603  void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, ManagedRegister scratch,
604                       bool null_allowed) OVERRIDE;
605
606  // src holds a handle scope entry (Object**) load this into dst
607  virtual void LoadReferenceFromHandleScope(ManagedRegister dst,
608                                     ManagedRegister src);
609
610  // Heap::VerifyObject on src. In some cases (such as a reference to this) we
611  // know that src may not be null.
612  void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
613  void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
614
615  // Call to address held at [base+offset]
616  void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
617  void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
618  void CallFromThread64(ThreadOffset<8> offset, ManagedRegister scratch) OVERRIDE;
619
620  // Generate code to check if Thread::Current()->exception_ is non-null
621  // and branch to a ExceptionSlowPath if it is.
622  void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
623
624  void InitializeFrameDescriptionEntry() OVERRIDE;
625  void FinalizeFrameDescriptionEntry() OVERRIDE;
626  std::vector<uint8_t>* GetFrameDescriptionEntry() OVERRIDE {
627    return &cfi_info_;
628  }
629
630 private:
631  void EmitUint8(uint8_t value);
632  void EmitInt32(int32_t value);
633  void EmitInt64(int64_t value);
634  void EmitRegisterOperand(uint8_t rm, uint8_t reg);
635  void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg);
636  void EmitFixup(AssemblerFixup* fixup);
637  void EmitOperandSizeOverride();
638
639  void EmitOperand(uint8_t rm, const Operand& operand);
640  void EmitImmediate(const Immediate& imm);
641  void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate);
642  void EmitLabel(Label* label, int instruction_size);
643  void EmitLabelLink(Label* label);
644  void EmitNearLabelLink(Label* label);
645
646  void EmitGenericShift(bool wide, int rm, CpuRegister reg, const Immediate& imm);
647  void EmitGenericShift(int rm, CpuRegister operand, CpuRegister shifter);
648
649  // If any input is not false, output the necessary rex prefix.
650  void EmitOptionalRex(bool force, bool w, bool r, bool x, bool b);
651
652  // Emit a rex prefix byte if necessary for reg. ie if reg is a register in the range R8 to R15.
653  void EmitOptionalRex32(CpuRegister reg);
654  void EmitOptionalRex32(CpuRegister dst, CpuRegister src);
655  void EmitOptionalRex32(XmmRegister dst, XmmRegister src);
656  void EmitOptionalRex32(CpuRegister dst, XmmRegister src);
657  void EmitOptionalRex32(XmmRegister dst, CpuRegister src);
658  void EmitOptionalRex32(const Operand& operand);
659  void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
660  void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
661
662  // Emit a REX.W prefix plus necessary register bit encodings.
663  void EmitRex64(CpuRegister reg);
664  void EmitRex64(CpuRegister dst, CpuRegister src);
665  void EmitRex64(CpuRegister dst, const Operand& operand);
666  void EmitRex64(XmmRegister dst, CpuRegister src);
667
668  // Emit a REX prefix to normalize byte registers plus necessary register bit encodings.
669  void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src);
670  void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand);
671
672  std::vector<uint8_t> cfi_info_;
673  uint32_t cfi_cfa_offset_, cfi_pc_;
674
675  DISALLOW_COPY_AND_ASSIGN(X86_64Assembler);
676};
677
678inline void X86_64Assembler::EmitUint8(uint8_t value) {
679  buffer_.Emit<uint8_t>(value);
680}
681
682inline void X86_64Assembler::EmitInt32(int32_t value) {
683  buffer_.Emit<int32_t>(value);
684}
685
686inline void X86_64Assembler::EmitInt64(int64_t value) {
687  buffer_.Emit<int64_t>(value);
688}
689
690inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) {
691  CHECK_GE(rm, 0);
692  CHECK_LT(rm, 8);
693  buffer_.Emit<uint8_t>((0xC0 | (reg & 7)) + (rm << 3));
694}
695
696inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) {
697  EmitRegisterOperand(rm, static_cast<uint8_t>(reg.AsFloatRegister()));
698}
699
700inline void X86_64Assembler::EmitFixup(AssemblerFixup* fixup) {
701  buffer_.EmitFixup(fixup);
702}
703
704inline void X86_64Assembler::EmitOperandSizeOverride() {
705  EmitUint8(0x66);
706}
707
708}  // namespace x86_64
709}  // namespace art
710
711#endif  // ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
712