assembler_x86_64.h revision 851df20225593b10e698a760ac3cd5243620700b
1/* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_ 18#define ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_ 19 20#include <vector> 21#include "base/macros.h" 22#include "constants_x86_64.h" 23#include "globals.h" 24#include "managed_register_x86_64.h" 25#include "offsets.h" 26#include "utils/assembler.h" 27#include "utils.h" 28 29namespace art { 30namespace x86_64 { 31 32// Encodes an immediate value for operands. 33// 34// Note: Immediates can be 64b on x86-64 for certain instructions, but are often restricted 35// to 32b. 36// 37// Note: As we support cross-compilation, the value type must be int64_t. Please be aware of 38// conversion rules in expressions regarding negation, especially size_t on 32b. 39class Immediate : public ValueObject { 40 public: 41 explicit Immediate(int64_t value_in) : value_(value_in) {} 42 43 int64_t value() const { return value_; } 44 45 bool is_int8() const { return IsInt(8, value_); } 46 bool is_uint8() const { return IsUint(8, value_); } 47 bool is_int16() const { return IsInt(16, value_); } 48 bool is_uint16() const { return IsUint(16, value_); } 49 bool is_int32() const { 50 // This does not work on 32b machines: return IsInt(32, value_); 51 int64_t limit = static_cast<int64_t>(1) << 31; 52 return (-limit <= value_) && (value_ < limit); 53 } 54 55 private: 56 const int64_t value_; 57}; 58 59 60class Operand : public ValueObject { 61 public: 62 uint8_t mod() const { 63 return (encoding_at(0) >> 6) & 3; 64 } 65 66 Register rm() const { 67 return static_cast<Register>(encoding_at(0) & 7); 68 } 69 70 ScaleFactor scale() const { 71 return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3); 72 } 73 74 Register index() const { 75 return static_cast<Register>((encoding_at(1) >> 3) & 7); 76 } 77 78 Register base() const { 79 return static_cast<Register>(encoding_at(1) & 7); 80 } 81 82 uint8_t rex() const { 83 return rex_; 84 } 85 86 int8_t disp8() const { 87 CHECK_GE(length_, 2); 88 return static_cast<int8_t>(encoding_[length_ - 1]); 89 } 90 91 int32_t disp32() const { 92 CHECK_GE(length_, 5); 93 int32_t value; 94 memcpy(&value, &encoding_[length_ - 4], sizeof(value)); 95 return value; 96 } 97 98 bool IsRegister(CpuRegister reg) const { 99 return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only. 100 && ((encoding_[0] & 0x07) == reg.LowBits()) // Register codes match. 101 && (reg.NeedsRex() == ((rex_ & 1) != 0)); // REX.000B bits match. 102 } 103 104 protected: 105 // Operand can be sub classed (e.g: Address). 106 Operand() : rex_(0), length_(0) { } 107 108 void SetModRM(uint8_t mod_in, CpuRegister rm_in) { 109 CHECK_EQ(mod_in & ~3, 0); 110 if (rm_in.NeedsRex()) { 111 rex_ |= 0x41; // REX.000B 112 } 113 encoding_[0] = (mod_in << 6) | rm_in.LowBits(); 114 length_ = 1; 115 } 116 117 void SetSIB(ScaleFactor scale_in, CpuRegister index_in, CpuRegister base_in) { 118 CHECK_EQ(length_, 1); 119 CHECK_EQ(scale_in & ~3, 0); 120 if (base_in.NeedsRex()) { 121 rex_ |= 0x41; // REX.000B 122 } 123 if (index_in.NeedsRex()) { 124 rex_ |= 0x42; // REX.00X0 125 } 126 encoding_[1] = (scale_in << 6) | (static_cast<uint8_t>(index_in.LowBits()) << 3) | 127 static_cast<uint8_t>(base_in.LowBits()); 128 length_ = 2; 129 } 130 131 void SetDisp8(int8_t disp) { 132 CHECK(length_ == 1 || length_ == 2); 133 encoding_[length_++] = static_cast<uint8_t>(disp); 134 } 135 136 void SetDisp32(int32_t disp) { 137 CHECK(length_ == 1 || length_ == 2); 138 int disp_size = sizeof(disp); 139 memmove(&encoding_[length_], &disp, disp_size); 140 length_ += disp_size; 141 } 142 143 private: 144 uint8_t rex_; 145 uint8_t length_; 146 uint8_t encoding_[6]; 147 148 explicit Operand(CpuRegister reg) : rex_(0), length_(0) { SetModRM(3, reg); } 149 150 // Get the operand encoding byte at the given index. 151 uint8_t encoding_at(int index_in) const { 152 CHECK_GE(index_in, 0); 153 CHECK_LT(index_in, length_); 154 return encoding_[index_in]; 155 } 156 157 friend class X86_64Assembler; 158}; 159 160 161class Address : public Operand { 162 public: 163 Address(CpuRegister base_in, int32_t disp) { 164 Init(base_in, disp); 165 } 166 167 Address(CpuRegister base_in, Offset disp) { 168 Init(base_in, disp.Int32Value()); 169 } 170 171 Address(CpuRegister base_in, FrameOffset disp) { 172 CHECK_EQ(base_in.AsRegister(), RSP); 173 Init(CpuRegister(RSP), disp.Int32Value()); 174 } 175 176 Address(CpuRegister base_in, MemberOffset disp) { 177 Init(base_in, disp.Int32Value()); 178 } 179 180 void Init(CpuRegister base_in, int32_t disp) { 181 if (disp == 0 && base_in.AsRegister() != RBP) { 182 SetModRM(0, base_in); 183 if (base_in.AsRegister() == RSP) { 184 SetSIB(TIMES_1, CpuRegister(RSP), base_in); 185 } 186 } else if (disp >= -128 && disp <= 127) { 187 SetModRM(1, base_in); 188 if (base_in.AsRegister() == RSP) { 189 SetSIB(TIMES_1, CpuRegister(RSP), base_in); 190 } 191 SetDisp8(disp); 192 } else { 193 SetModRM(2, base_in); 194 if (base_in.AsRegister() == RSP) { 195 SetSIB(TIMES_1, CpuRegister(RSP), base_in); 196 } 197 SetDisp32(disp); 198 } 199 } 200 201 202 Address(CpuRegister index_in, ScaleFactor scale_in, int32_t disp) { 203 CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode. 204 SetModRM(0, CpuRegister(RSP)); 205 SetSIB(scale_in, index_in, CpuRegister(RBP)); 206 SetDisp32(disp); 207 } 208 209 Address(CpuRegister base_in, CpuRegister index_in, ScaleFactor scale_in, int32_t disp) { 210 CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode. 211 if (disp == 0 && base_in.AsRegister() != RBP) { 212 SetModRM(0, CpuRegister(RSP)); 213 SetSIB(scale_in, index_in, base_in); 214 } else if (disp >= -128 && disp <= 127) { 215 SetModRM(1, CpuRegister(RSP)); 216 SetSIB(scale_in, index_in, base_in); 217 SetDisp8(disp); 218 } else { 219 SetModRM(2, CpuRegister(RSP)); 220 SetSIB(scale_in, index_in, base_in); 221 SetDisp32(disp); 222 } 223 } 224 225 // If no_rip is true then the Absolute address isn't RIP relative. 226 static Address Absolute(uintptr_t addr, bool no_rip = false) { 227 Address result; 228 if (no_rip) { 229 result.SetModRM(0, CpuRegister(RSP)); 230 result.SetSIB(TIMES_1, CpuRegister(RSP), CpuRegister(RBP)); 231 result.SetDisp32(addr); 232 } else { 233 result.SetModRM(0, CpuRegister(RBP)); 234 result.SetDisp32(addr); 235 } 236 return result; 237 } 238 239 // If no_rip is true then the Absolute address isn't RIP relative. 240 static Address Absolute(ThreadOffset<8> addr, bool no_rip = false) { 241 return Absolute(addr.Int32Value(), no_rip); 242 } 243 244 private: 245 Address() {} 246}; 247 248 249class X86_64Assembler FINAL : public Assembler { 250 public: 251 X86_64Assembler() : cfi_cfa_offset_(0), cfi_pc_(0) {} 252 virtual ~X86_64Assembler() {} 253 254 /* 255 * Emit Machine Instructions. 256 */ 257 void call(CpuRegister reg); 258 void call(const Address& address); 259 void call(Label* label); 260 261 void pushq(CpuRegister reg); 262 void pushq(const Address& address); 263 void pushq(const Immediate& imm); 264 265 void popq(CpuRegister reg); 266 void popq(const Address& address); 267 268 void movq(CpuRegister dst, const Immediate& src); 269 void movl(CpuRegister dst, const Immediate& src); 270 void movq(CpuRegister dst, CpuRegister src); 271 void movl(CpuRegister dst, CpuRegister src); 272 273 void movq(CpuRegister dst, const Address& src); 274 void movl(CpuRegister dst, const Address& src); 275 void movq(const Address& dst, CpuRegister src); 276 void movl(const Address& dst, CpuRegister src); 277 void movl(const Address& dst, const Immediate& imm); 278 279 void movzxb(CpuRegister dst, CpuRegister src); 280 void movzxb(CpuRegister dst, const Address& src); 281 void movsxb(CpuRegister dst, CpuRegister src); 282 void movsxb(CpuRegister dst, const Address& src); 283 void movb(CpuRegister dst, const Address& src); 284 void movb(const Address& dst, CpuRegister src); 285 void movb(const Address& dst, const Immediate& imm); 286 287 void movzxw(CpuRegister dst, CpuRegister src); 288 void movzxw(CpuRegister dst, const Address& src); 289 void movsxw(CpuRegister dst, CpuRegister src); 290 void movsxw(CpuRegister dst, const Address& src); 291 void movw(CpuRegister dst, const Address& src); 292 void movw(const Address& dst, CpuRegister src); 293 void movw(const Address& dst, const Immediate& imm); 294 295 void leaq(CpuRegister dst, const Address& src); 296 297 void movaps(XmmRegister dst, XmmRegister src); 298 299 void movss(XmmRegister dst, const Address& src); 300 void movss(const Address& dst, XmmRegister src); 301 void movss(XmmRegister dst, XmmRegister src); 302 303 void movsxd(CpuRegister dst, CpuRegister src); 304 void movsxd(CpuRegister dst, const Address& src); 305 306 void movd(XmmRegister dst, CpuRegister src); 307 void movd(CpuRegister dst, XmmRegister src); 308 309 void addss(XmmRegister dst, XmmRegister src); 310 void addss(XmmRegister dst, const Address& src); 311 void subss(XmmRegister dst, XmmRegister src); 312 void subss(XmmRegister dst, const Address& src); 313 void mulss(XmmRegister dst, XmmRegister src); 314 void mulss(XmmRegister dst, const Address& src); 315 void divss(XmmRegister dst, XmmRegister src); 316 void divss(XmmRegister dst, const Address& src); 317 318 void movsd(XmmRegister dst, const Address& src); 319 void movsd(const Address& dst, XmmRegister src); 320 void movsd(XmmRegister dst, XmmRegister src); 321 322 void addsd(XmmRegister dst, XmmRegister src); 323 void addsd(XmmRegister dst, const Address& src); 324 void subsd(XmmRegister dst, XmmRegister src); 325 void subsd(XmmRegister dst, const Address& src); 326 void mulsd(XmmRegister dst, XmmRegister src); 327 void mulsd(XmmRegister dst, const Address& src); 328 void divsd(XmmRegister dst, XmmRegister src); 329 void divsd(XmmRegister dst, const Address& src); 330 331 void cvtsi2ss(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version. 332 void cvtsi2sd(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version. 333 334 void cvtss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version. 335 void cvtss2sd(XmmRegister dst, XmmRegister src); 336 337 void cvtsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version. 338 void cvtsd2ss(XmmRegister dst, XmmRegister src); 339 340 void cvttss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version. 341 void cvttsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version. 342 343 void cvtdq2pd(XmmRegister dst, XmmRegister src); 344 345 void comiss(XmmRegister a, XmmRegister b); 346 void comisd(XmmRegister a, XmmRegister b); 347 348 void sqrtsd(XmmRegister dst, XmmRegister src); 349 void sqrtss(XmmRegister dst, XmmRegister src); 350 351 void xorpd(XmmRegister dst, const Address& src); 352 void xorpd(XmmRegister dst, XmmRegister src); 353 void xorps(XmmRegister dst, const Address& src); 354 void xorps(XmmRegister dst, XmmRegister src); 355 356 void andpd(XmmRegister dst, const Address& src); 357 358 void flds(const Address& src); 359 void fstps(const Address& dst); 360 361 void fldl(const Address& src); 362 void fstpl(const Address& dst); 363 364 void fnstcw(const Address& dst); 365 void fldcw(const Address& src); 366 367 void fistpl(const Address& dst); 368 void fistps(const Address& dst); 369 void fildl(const Address& src); 370 371 void fincstp(); 372 void ffree(const Immediate& index); 373 374 void fsin(); 375 void fcos(); 376 void fptan(); 377 378 void xchgl(CpuRegister dst, CpuRegister src); 379 void xchgq(CpuRegister dst, CpuRegister src); 380 void xchgl(CpuRegister reg, const Address& address); 381 382 void cmpw(const Address& address, const Immediate& imm); 383 384 void cmpl(CpuRegister reg, const Immediate& imm); 385 void cmpl(CpuRegister reg0, CpuRegister reg1); 386 void cmpl(CpuRegister reg, const Address& address); 387 void cmpl(const Address& address, CpuRegister reg); 388 void cmpl(const Address& address, const Immediate& imm); 389 390 void cmpq(CpuRegister reg0, CpuRegister reg1); 391 void cmpq(CpuRegister reg0, const Immediate& imm); 392 void cmpq(CpuRegister reg0, const Address& address); 393 void cmpq(const Address& address, const Immediate& imm); 394 395 void testl(CpuRegister reg1, CpuRegister reg2); 396 void testl(CpuRegister reg, const Immediate& imm); 397 398 void testq(CpuRegister reg1, CpuRegister reg2); 399 void testq(CpuRegister reg, const Address& address); 400 401 void andl(CpuRegister dst, const Immediate& imm); 402 void andl(CpuRegister dst, CpuRegister src); 403 void andl(CpuRegister reg, const Address& address); 404 void andq(CpuRegister dst, const Immediate& imm); 405 void andq(CpuRegister dst, CpuRegister src); 406 407 void orl(CpuRegister dst, const Immediate& imm); 408 void orl(CpuRegister dst, CpuRegister src); 409 void orl(CpuRegister reg, const Address& address); 410 void orq(CpuRegister dst, CpuRegister src); 411 412 void xorl(CpuRegister dst, CpuRegister src); 413 void xorl(CpuRegister dst, const Immediate& imm); 414 void xorl(CpuRegister reg, const Address& address); 415 void xorq(CpuRegister dst, const Immediate& imm); 416 void xorq(CpuRegister dst, CpuRegister src); 417 418 void addl(CpuRegister dst, CpuRegister src); 419 void addl(CpuRegister reg, const Immediate& imm); 420 void addl(CpuRegister reg, const Address& address); 421 void addl(const Address& address, CpuRegister reg); 422 void addl(const Address& address, const Immediate& imm); 423 424 void addq(CpuRegister reg, const Immediate& imm); 425 void addq(CpuRegister dst, CpuRegister src); 426 void addq(CpuRegister dst, const Address& address); 427 428 void subl(CpuRegister dst, CpuRegister src); 429 void subl(CpuRegister reg, const Immediate& imm); 430 void subl(CpuRegister reg, const Address& address); 431 432 void subq(CpuRegister reg, const Immediate& imm); 433 void subq(CpuRegister dst, CpuRegister src); 434 void subq(CpuRegister dst, const Address& address); 435 436 void cdq(); 437 void cqo(); 438 439 void idivl(CpuRegister reg); 440 void idivq(CpuRegister reg); 441 442 void imull(CpuRegister dst, CpuRegister src); 443 void imull(CpuRegister reg, const Immediate& imm); 444 void imull(CpuRegister reg, const Address& address); 445 446 void imulq(CpuRegister dst, CpuRegister src); 447 void imulq(CpuRegister reg, const Immediate& imm); 448 void imulq(CpuRegister reg, const Address& address); 449 450 void imull(CpuRegister reg); 451 void imull(const Address& address); 452 453 void mull(CpuRegister reg); 454 void mull(const Address& address); 455 456 void shll(CpuRegister reg, const Immediate& imm); 457 void shll(CpuRegister operand, CpuRegister shifter); 458 void shrl(CpuRegister reg, const Immediate& imm); 459 void shrl(CpuRegister operand, CpuRegister shifter); 460 void sarl(CpuRegister reg, const Immediate& imm); 461 void sarl(CpuRegister operand, CpuRegister shifter); 462 463 void shrq(CpuRegister reg, const Immediate& imm); 464 465 void negl(CpuRegister reg); 466 void negq(CpuRegister reg); 467 468 void notl(CpuRegister reg); 469 void notq(CpuRegister reg); 470 471 void enter(const Immediate& imm); 472 void leave(); 473 474 void ret(); 475 void ret(const Immediate& imm); 476 477 void nop(); 478 void int3(); 479 void hlt(); 480 481 void j(Condition condition, Label* label); 482 483 void jmp(CpuRegister reg); 484 void jmp(const Address& address); 485 void jmp(Label* label); 486 487 X86_64Assembler* lock(); 488 void cmpxchgl(const Address& address, CpuRegister reg); 489 490 void mfence(); 491 492 X86_64Assembler* gs(); 493 494 void setcc(Condition condition, CpuRegister dst); 495 496 // 497 // Macros for High-level operations. 498 // 499 500 void AddImmediate(CpuRegister reg, const Immediate& imm); 501 502 void LoadDoubleConstant(XmmRegister dst, double value); 503 504 void DoubleNegate(XmmRegister d); 505 void FloatNegate(XmmRegister f); 506 507 void DoubleAbs(XmmRegister reg); 508 509 void LockCmpxchgl(const Address& address, CpuRegister reg) { 510 lock()->cmpxchgl(address, reg); 511 } 512 513 // 514 // Misc. functionality 515 // 516 int PreferredLoopAlignment() { return 16; } 517 void Align(int alignment, int offset); 518 void Bind(Label* label); 519 520 // 521 // Overridden common assembler high-level functionality 522 // 523 524 // Emit code that will create an activation on the stack 525 void BuildFrame(size_t frame_size, ManagedRegister method_reg, 526 const std::vector<ManagedRegister>& callee_save_regs, 527 const ManagedRegisterEntrySpills& entry_spills) OVERRIDE; 528 529 // Emit code that will remove an activation from the stack 530 void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs) 531 OVERRIDE; 532 533 void IncreaseFrameSize(size_t adjust) OVERRIDE; 534 void DecreaseFrameSize(size_t adjust) OVERRIDE; 535 536 // Store routines 537 void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE; 538 void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE; 539 void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE; 540 541 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE; 542 543 void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister scratch) 544 OVERRIDE; 545 546 void StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, 547 ManagedRegister scratch) OVERRIDE; 548 549 void StoreStackPointerToThread64(ThreadOffset<8> thr_offs) OVERRIDE; 550 551 void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off, 552 ManagedRegister scratch) OVERRIDE; 553 554 // Load routines 555 void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE; 556 557 void LoadFromThread64(ManagedRegister dest, ThreadOffset<8> src, size_t size) OVERRIDE; 558 559 void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE; 560 561 void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE; 562 563 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE; 564 565 void LoadRawPtrFromThread64(ManagedRegister dest, ThreadOffset<8> offs) OVERRIDE; 566 567 // Copying routines 568 void Move(ManagedRegister dest, ManagedRegister src, size_t size); 569 570 void CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> thr_offs, 571 ManagedRegister scratch) OVERRIDE; 572 573 void CopyRawPtrToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, ManagedRegister scratch) 574 OVERRIDE; 575 576 void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE; 577 578 void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE; 579 580 void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch, 581 size_t size) OVERRIDE; 582 583 void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch, 584 size_t size) OVERRIDE; 585 586 void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch, 587 size_t size) OVERRIDE; 588 589 void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset, 590 ManagedRegister scratch, size_t size) OVERRIDE; 591 592 void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset, 593 ManagedRegister scratch, size_t size) OVERRIDE; 594 595 void MemoryBarrier(ManagedRegister) OVERRIDE; 596 597 // Sign extension 598 void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE; 599 600 // Zero extension 601 void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE; 602 603 // Exploit fast access in managed code to Thread::Current() 604 void GetCurrentThread(ManagedRegister tr) OVERRIDE; 605 void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE; 606 607 // Set up out_reg to hold a Object** into the handle scope, or to be NULL if the 608 // value is null and null_allowed. in_reg holds a possibly stale reference 609 // that can be used to avoid loading the handle scope entry to see if the value is 610 // NULL. 611 void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, ManagedRegister in_reg, 612 bool null_allowed) OVERRIDE; 613 614 // Set up out_off to hold a Object** into the handle scope, or to be NULL if the 615 // value is null and null_allowed. 616 void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, ManagedRegister scratch, 617 bool null_allowed) OVERRIDE; 618 619 // src holds a handle scope entry (Object**) load this into dst 620 virtual void LoadReferenceFromHandleScope(ManagedRegister dst, 621 ManagedRegister src); 622 623 // Heap::VerifyObject on src. In some cases (such as a reference to this) we 624 // know that src may not be null. 625 void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE; 626 void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE; 627 628 // Call to address held at [base+offset] 629 void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE; 630 void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE; 631 void CallFromThread64(ThreadOffset<8> offset, ManagedRegister scratch) OVERRIDE; 632 633 // Generate code to check if Thread::Current()->exception_ is non-null 634 // and branch to a ExceptionSlowPath if it is. 635 void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE; 636 637 void InitializeFrameDescriptionEntry() OVERRIDE; 638 void FinalizeFrameDescriptionEntry() OVERRIDE; 639 std::vector<uint8_t>* GetFrameDescriptionEntry() OVERRIDE { 640 return &cfi_info_; 641 } 642 643 private: 644 void EmitUint8(uint8_t value); 645 void EmitInt32(int32_t value); 646 void EmitInt64(int64_t value); 647 void EmitRegisterOperand(uint8_t rm, uint8_t reg); 648 void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg); 649 void EmitFixup(AssemblerFixup* fixup); 650 void EmitOperandSizeOverride(); 651 652 void EmitOperand(uint8_t rm, const Operand& operand); 653 void EmitImmediate(const Immediate& imm); 654 void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate); 655 void EmitLabel(Label* label, int instruction_size); 656 void EmitLabelLink(Label* label); 657 void EmitNearLabelLink(Label* label); 658 659 void EmitGenericShift(bool wide, int rm, CpuRegister reg, const Immediate& imm); 660 void EmitGenericShift(int rm, CpuRegister operand, CpuRegister shifter); 661 662 // If any input is not false, output the necessary rex prefix. 663 void EmitOptionalRex(bool force, bool w, bool r, bool x, bool b); 664 665 // Emit a rex prefix byte if necessary for reg. ie if reg is a register in the range R8 to R15. 666 void EmitOptionalRex32(CpuRegister reg); 667 void EmitOptionalRex32(CpuRegister dst, CpuRegister src); 668 void EmitOptionalRex32(XmmRegister dst, XmmRegister src); 669 void EmitOptionalRex32(CpuRegister dst, XmmRegister src); 670 void EmitOptionalRex32(XmmRegister dst, CpuRegister src); 671 void EmitOptionalRex32(const Operand& operand); 672 void EmitOptionalRex32(CpuRegister dst, const Operand& operand); 673 void EmitOptionalRex32(XmmRegister dst, const Operand& operand); 674 675 // Emit a REX.W prefix plus necessary register bit encodings. 676 void EmitRex64(); 677 void EmitRex64(CpuRegister reg); 678 void EmitRex64(const Operand& operand); 679 void EmitRex64(CpuRegister dst, CpuRegister src); 680 void EmitRex64(CpuRegister dst, const Operand& operand); 681 void EmitRex64(XmmRegister dst, CpuRegister src); 682 683 // Emit a REX prefix to normalize byte registers plus necessary register bit encodings. 684 void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src); 685 void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand); 686 687 std::vector<uint8_t> cfi_info_; 688 uint32_t cfi_cfa_offset_, cfi_pc_; 689 690 DISALLOW_COPY_AND_ASSIGN(X86_64Assembler); 691}; 692 693inline void X86_64Assembler::EmitUint8(uint8_t value) { 694 buffer_.Emit<uint8_t>(value); 695} 696 697inline void X86_64Assembler::EmitInt32(int32_t value) { 698 buffer_.Emit<int32_t>(value); 699} 700 701inline void X86_64Assembler::EmitInt64(int64_t value) { 702 // Write this 64-bit value as two 32-bit words for alignment reasons 703 // (this is essentially when running on ARM, which does not allow 704 // 64-bit unaligned accesses). We assume little-endianness here. 705 EmitInt32(Low32Bits(value)); 706 EmitInt32(High32Bits(value)); 707} 708 709inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) { 710 CHECK_GE(rm, 0); 711 CHECK_LT(rm, 8); 712 buffer_.Emit<uint8_t>((0xC0 | (reg & 7)) + (rm << 3)); 713} 714 715inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) { 716 EmitRegisterOperand(rm, static_cast<uint8_t>(reg.AsFloatRegister())); 717} 718 719inline void X86_64Assembler::EmitFixup(AssemblerFixup* fixup) { 720 buffer_.EmitFixup(fixup); 721} 722 723inline void X86_64Assembler::EmitOperandSizeOverride() { 724 EmitUint8(0x66); 725} 726 727} // namespace x86_64 728} // namespace art 729 730#endif // ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_ 731