assembler_x86_64.h revision fca82208f7128fcda09b6a4743199308332558a2 
1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
18#define ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
19
20#include <vector>
21#include "base/macros.h"
22#include "constants_x86_64.h"
23#include "globals.h"
24#include "managed_register_x86_64.h"
25#include "offsets.h"
26#include "utils/assembler.h"
27#include "utils.h"
28
29namespace art {
30namespace x86_64 {
31
32class Immediate {
33 public:
34  explicit Immediate(int32_t value) : value_(value) {}
35
36  int32_t value() const { return value_; }
37
38  bool is_int8() const { return IsInt(8, value_); }
39  bool is_uint8() const { return IsUint(8, value_); }
40  bool is_uint16() const { return IsUint(16, value_); }
41
42 private:
43  const int32_t value_;
44
45  DISALLOW_COPY_AND_ASSIGN(Immediate);
46};
47
48
49class Operand {
50 public:
51  uint8_t mod() const {
52    return (encoding_at(0) >> 6) & 3;
53  }
54
55  Register rm() const {
56    return static_cast<Register>(encoding_at(0) & 7);
57  }
58
59  ScaleFactor scale() const {
60    return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
61  }
62
63  Register index() const {
64    return static_cast<Register>((encoding_at(1) >> 3) & 7);
65  }
66
67  Register base() const {
68    return static_cast<Register>(encoding_at(1) & 7);
69  }
70
71  int8_t disp8() const {
72    CHECK_GE(length_, 2);
73    return static_cast<int8_t>(encoding_[length_ - 1]);
74  }
75
76  int32_t disp32() const {
77    CHECK_GE(length_, 5);
78    int32_t value;
79    memcpy(&value, &encoding_[length_ - 4], sizeof(value));
80    return value;
81  }
82
83  bool IsRegister(Register reg) const {
84    return ((encoding_[0] & 0xF8) == 0xC0)  // Addressing mode is register only.
85        && ((encoding_[0] & 0x07) == reg);  // Register codes match.
86  }
87
88 protected:
89  // Operand can be sub classed (e.g: Address).
90  Operand() : length_(0) { }
91
92  void SetModRM(int mod, Register rm) {
93    CHECK_EQ(mod & ~3, 0);
94    encoding_[0] = (mod << 6) | rm;
95    length_ = 1;
96  }
97
98  void SetSIB(ScaleFactor scale, Register index, Register base) {
99    CHECK_EQ(length_, 1);
100    CHECK_EQ(scale & ~3, 0);
101    encoding_[1] = (scale << 6) | (index << 3) | base;
102    length_ = 2;
103  }
104
105  void SetDisp8(int8_t disp) {
106    CHECK(length_ == 1 || length_ == 2);
107    encoding_[length_++] = static_cast<uint8_t>(disp);
108  }
109
110  void SetDisp32(int32_t disp) {
111    CHECK(length_ == 1 || length_ == 2);
112    int disp_size = sizeof(disp);
113    memmove(&encoding_[length_], &disp, disp_size);
114    length_ += disp_size;
115  }
116
117 private:
118  byte length_;
119  byte encoding_[6];
120  byte padding_;
121
122  explicit Operand(Register reg) { SetModRM(3, reg); }
123
124  // Get the operand encoding byte at the given index.
125  uint8_t encoding_at(int index) const {
126    CHECK_GE(index, 0);
127    CHECK_LT(index, length_);
128    return encoding_[index];
129  }
130
131  friend class X86_64Assembler;
132
133  DISALLOW_COPY_AND_ASSIGN(Operand);
134};
135
136
137class Address : public Operand {
138 public:
139  Address(Register base, int32_t disp) {
140    Init(base, disp);
141  }
142
143  Address(Register base, Offset disp) {
144    Init(base, disp.Int32Value());
145  }
146
147  Address(Register base, FrameOffset disp) {
148    CHECK_EQ(base, RSP);
149    Init(RSP, disp.Int32Value());
150  }
151
152  Address(Register base, MemberOffset disp) {
153    Init(base, disp.Int32Value());
154  }
155
156  void Init(Register base, int32_t disp) {
157    if (disp == 0 && base != RBP) {
158      SetModRM(0, base);
159      if (base == RSP) SetSIB(TIMES_1, RSP, base);
160    } else if (disp >= -128 && disp <= 127) {
161      SetModRM(1, base);
162      if (base == RSP) SetSIB(TIMES_1, RSP, base);
163      SetDisp8(disp);
164    } else {
165      SetModRM(2, base);
166      if (base == RSP) SetSIB(TIMES_1, RSP, base);
167      SetDisp32(disp);
168    }
169  }
170
171
172  Address(Register index, ScaleFactor scale, int32_t disp) {
173    CHECK_NE(index, RSP);  // Illegal addressing mode.
174    SetModRM(0, RSP);
175    SetSIB(scale, index, RBP);
176    SetDisp32(disp);
177  }
178
179  Address(Register base, Register index, ScaleFactor scale, int32_t disp) {
180    CHECK_NE(index, RSP);  // Illegal addressing mode.
181    if (disp == 0 && base != RBP) {
182      SetModRM(0, RSP);
183      SetSIB(scale, index, base);
184    } else if (disp >= -128 && disp <= 127) {
185      SetModRM(1, RSP);
186      SetSIB(scale, index, base);
187      SetDisp8(disp);
188    } else {
189      SetModRM(2, RSP);
190      SetSIB(scale, index, base);
191      SetDisp32(disp);
192    }
193  }
194
195  static Address Absolute(uword addr, bool has_rip = false) {
196    Address result;
197    if (has_rip) {
198      result.SetModRM(0, RSP);
199      result.SetSIB(TIMES_1, RSP, RBP);
200      result.SetDisp32(addr);
201    } else {
202      result.SetModRM(0, RBP);
203      result.SetDisp32(addr);
204    }
205    return result;
206  }
207
208  static Address Absolute(ThreadOffset addr, bool has_rip = false) {
209    return Absolute(addr.Int32Value(), has_rip);
210  }
211
212 private:
213  Address() {}
214
215  DISALLOW_COPY_AND_ASSIGN(Address);
216};
217
218
219class X86_64Assembler : public Assembler {
220 public:
221  X86_64Assembler() {}
222  virtual ~X86_64Assembler() {}
223
224  /*
225   * Emit Machine Instructions.
226   */
227  void call(Register reg);
228  void call(const Address& address);
229  void call(Label* label);
230
231  void pushq(Register reg);
232  void pushq(const Address& address);
233  void pushq(const Immediate& imm);
234
235  void popq(Register reg);
236  void popq(const Address& address);
237
238  void movq(Register dst, const Immediate& src);
239  void movl(Register dst, const Immediate& src);
240  void movq(Register dst, Register src);
241  void movl(Register dst, Register src);
242
243  void movq(Register dst, const Address& src);
244  void movl(Register dst, const Address& src);
245  void movq(const Address& dst, Register src);
246  void movl(const Address& dst, Register src);
247  void movl(const Address& dst, const Immediate& imm);
248  void movl(const Address& dst, Label* lbl);
249
250  void movzxb(Register dst, ByteRegister src);
251  void movzxb(Register dst, const Address& src);
252  void movsxb(Register dst, ByteRegister src);
253  void movsxb(Register dst, const Address& src);
254  void movb(Register dst, const Address& src);
255  void movb(const Address& dst, ByteRegister src);
256  void movb(const Address& dst, const Immediate& imm);
257
258  void movzxw(Register dst, Register src);
259  void movzxw(Register dst, const Address& src);
260  void movsxw(Register dst, Register src);
261  void movsxw(Register dst, const Address& src);
262  void movw(Register dst, const Address& src);
263  void movw(const Address& dst, Register src);
264
265  void leaq(Register dst, const Address& src);
266
267  void cmovl(Condition condition, Register dst, Register src);
268
269  void setb(Condition condition, Register dst);
270
271  void movss(XmmRegister dst, const Address& src);
272  void movss(const Address& dst, XmmRegister src);
273  void movss(XmmRegister dst, XmmRegister src);
274
275  void movd(XmmRegister dst, Register src);
276  void movd(Register dst, XmmRegister src);
277
278  void addss(XmmRegister dst, XmmRegister src);
279  void addss(XmmRegister dst, const Address& src);
280  void subss(XmmRegister dst, XmmRegister src);
281  void subss(XmmRegister dst, const Address& src);
282  void mulss(XmmRegister dst, XmmRegister src);
283  void mulss(XmmRegister dst, const Address& src);
284  void divss(XmmRegister dst, XmmRegister src);
285  void divss(XmmRegister dst, const Address& src);
286
287  void movsd(XmmRegister dst, const Address& src);
288  void movsd(const Address& dst, XmmRegister src);
289  void movsd(XmmRegister dst, XmmRegister src);
290
291  void addsd(XmmRegister dst, XmmRegister src);
292  void addsd(XmmRegister dst, const Address& src);
293  void subsd(XmmRegister dst, XmmRegister src);
294  void subsd(XmmRegister dst, const Address& src);
295  void mulsd(XmmRegister dst, XmmRegister src);
296  void mulsd(XmmRegister dst, const Address& src);
297  void divsd(XmmRegister dst, XmmRegister src);
298  void divsd(XmmRegister dst, const Address& src);
299
300  void cvtsi2ss(XmmRegister dst, Register src);
301  void cvtsi2sd(XmmRegister dst, Register src);
302
303  void cvtss2si(Register dst, XmmRegister src);
304  void cvtss2sd(XmmRegister dst, XmmRegister src);
305
306  void cvtsd2si(Register dst, XmmRegister src);
307  void cvtsd2ss(XmmRegister dst, XmmRegister src);
308
309  void cvttss2si(Register dst, XmmRegister src);
310  void cvttsd2si(Register dst, XmmRegister src);
311
312  void cvtdq2pd(XmmRegister dst, XmmRegister src);
313
314  void comiss(XmmRegister a, XmmRegister b);
315  void comisd(XmmRegister a, XmmRegister b);
316
317  void sqrtsd(XmmRegister dst, XmmRegister src);
318  void sqrtss(XmmRegister dst, XmmRegister src);
319
320  void xorpd(XmmRegister dst, const Address& src);
321  void xorpd(XmmRegister dst, XmmRegister src);
322  void xorps(XmmRegister dst, const Address& src);
323  void xorps(XmmRegister dst, XmmRegister src);
324
325  void andpd(XmmRegister dst, const Address& src);
326
327  void flds(const Address& src);
328  void fstps(const Address& dst);
329
330  void fldl(const Address& src);
331  void fstpl(const Address& dst);
332
333  void fnstcw(const Address& dst);
334  void fldcw(const Address& src);
335
336  void fistpl(const Address& dst);
337  void fistps(const Address& dst);
338  void fildl(const Address& src);
339
340  void fincstp();
341  void ffree(const Immediate& index);
342
343  void fsin();
344  void fcos();
345  void fptan();
346
347  void xchgl(Register dst, Register src);
348  void xchgl(Register reg, const Address& address);
349
350  void cmpl(Register reg, const Immediate& imm);
351  void cmpl(Register reg0, Register reg1);
352  void cmpl(Register reg, const Address& address);
353
354  void cmpl(const Address& address, Register reg);
355  void cmpl(const Address& address, const Immediate& imm);
356
357  void testl(Register reg1, Register reg2);
358  void testl(Register reg, const Immediate& imm);
359
360  void andl(Register dst, const Immediate& imm);
361  void andl(Register dst, Register src);
362
363  void orl(Register dst, const Immediate& imm);
364  void orl(Register dst, Register src);
365
366  void xorl(Register dst, Register src);
367
368  void addl(Register dst, Register src);
369  void addq(Register reg, const Immediate& imm);
370  void addl(Register reg, const Immediate& imm);
371  void addl(Register reg, const Address& address);
372
373  void addl(const Address& address, Register reg);
374  void addl(const Address& address, const Immediate& imm);
375
376  void adcl(Register dst, Register src);
377  void adcl(Register reg, const Immediate& imm);
378  void adcl(Register dst, const Address& address);
379
380  void subl(Register dst, Register src);
381  void subl(Register reg, const Immediate& imm);
382  void subl(Register reg, const Address& address);
383
384  void cdq();
385
386  void idivl(Register reg);
387
388  void imull(Register dst, Register src);
389  void imull(Register reg, const Immediate& imm);
390  void imull(Register reg, const Address& address);
391
392  void imull(Register reg);
393  void imull(const Address& address);
394
395  void mull(Register reg);
396  void mull(const Address& address);
397
398  void sbbl(Register dst, Register src);
399  void sbbl(Register reg, const Immediate& imm);
400  void sbbl(Register reg, const Address& address);
401
402  void incl(Register reg);
403  void incl(const Address& address);
404
405  void decl(Register reg);
406  void decl(const Address& address);
407
408  void shll(Register reg, const Immediate& imm);
409  void shll(Register operand, Register shifter);
410  void shrl(Register reg, const Immediate& imm);
411  void shrl(Register operand, Register shifter);
412  void sarl(Register reg, const Immediate& imm);
413  void sarl(Register operand, Register shifter);
414  void shld(Register dst, Register src);
415
416  void negl(Register reg);
417  void notl(Register reg);
418
419  void enter(const Immediate& imm);
420  void leave();
421
422  void ret();
423  void ret(const Immediate& imm);
424
425  void nop();
426  void int3();
427  void hlt();
428
429  void j(Condition condition, Label* label);
430
431  void jmp(Register reg);
432  void jmp(const Address& address);
433  void jmp(Label* label);
434
435  X86_64Assembler* lock();
436  void cmpxchgl(const Address& address, Register reg);
437
438  void mfence();
439
440  X86_64Assembler* gs();
441
442  //
443  // Macros for High-level operations.
444  //
445
446  void AddImmediate(Register reg, const Immediate& imm);
447
448  void LoadDoubleConstant(XmmRegister dst, double value);
449
450  void DoubleNegate(XmmRegister d);
451  void FloatNegate(XmmRegister f);
452
453  void DoubleAbs(XmmRegister reg);
454
455  void LockCmpxchgl(const Address& address, Register reg) {
456    lock()->cmpxchgl(address, reg);
457  }
458
459  //
460  // Misc. functionality
461  //
462  int PreferredLoopAlignment() { return 16; }
463  void Align(int alignment, int offset);
464  void Bind(Label* label);
465
466  //
467  // Overridden common assembler high-level functionality
468  //
469
470  // Emit code that will create an activation on the stack
471  virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
472                          const std::vector<ManagedRegister>& callee_save_regs,
473                          const ManagedRegisterEntrySpills& entry_spills);
474
475  // Emit code that will remove an activation from the stack
476  virtual void RemoveFrame(size_t frame_size,
477                           const std::vector<ManagedRegister>& callee_save_regs);
478
479  virtual void IncreaseFrameSize(size_t adjust);
480  virtual void DecreaseFrameSize(size_t adjust);
481
482  // Store routines
483  virtual void Store(FrameOffset offs, ManagedRegister src, size_t size);
484  virtual void StoreRef(FrameOffset dest, ManagedRegister src);
485  virtual void StoreRawPtr(FrameOffset dest, ManagedRegister src);
486
487  virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
488                                     ManagedRegister scratch);
489
490  virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
491                                      ManagedRegister scratch);
492
493  virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
494                                        FrameOffset fr_offs,
495                                        ManagedRegister scratch);
496
497  virtual void StoreStackPointerToThread(ThreadOffset thr_offs);
498
499  void StoreLabelToThread(ThreadOffset thr_offs, Label* lbl);
500
501  virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
502                             FrameOffset in_off, ManagedRegister scratch);
503
504  // Load routines
505  virtual void Load(ManagedRegister dest, FrameOffset src, size_t size);
506
507  virtual void Load(ManagedRegister dest, ThreadOffset src, size_t size);
508
509  virtual void LoadRef(ManagedRegister dest, FrameOffset  src);
510
511  virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
512                       MemberOffset offs);
513
514  virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
515                          Offset offs);
516
517  virtual void LoadRawPtrFromThread(ManagedRegister dest,
518                                    ThreadOffset offs);
519
520  // Copying routines
521  virtual void Move(ManagedRegister dest, ManagedRegister src, size_t size);
522
523  virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
524                                    ManagedRegister scratch);
525
526  virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
527                                  ManagedRegister scratch);
528
529  virtual void CopyRef(FrameOffset dest, FrameOffset src,
530                       ManagedRegister scratch);
531
532  virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size);
533
534  virtual void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
535                    ManagedRegister scratch, size_t size);
536
537  virtual void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
538                    ManagedRegister scratch, size_t size);
539
540  virtual void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
541                    ManagedRegister scratch, size_t size);
542
543  virtual void Copy(ManagedRegister dest, Offset dest_offset,
544                    ManagedRegister src, Offset src_offset,
545                    ManagedRegister scratch, size_t size);
546
547  virtual void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
548                    ManagedRegister scratch, size_t size);
549
550  virtual void MemoryBarrier(ManagedRegister);
551
552  // Sign extension
553  virtual void SignExtend(ManagedRegister mreg, size_t size);
554
555  // Zero extension
556  virtual void ZeroExtend(ManagedRegister mreg, size_t size);
557
558  // Exploit fast access in managed code to Thread::Current()
559  virtual void GetCurrentThread(ManagedRegister tr);
560  virtual void GetCurrentThread(FrameOffset dest_offset,
561                                ManagedRegister scratch);
562
563  // Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
564  // value is null and null_allowed. in_reg holds a possibly stale reference
565  // that can be used to avoid loading the SIRT entry to see if the value is
566  // NULL.
567  virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
568                               ManagedRegister in_reg, bool null_allowed);
569
570  // Set up out_off to hold a Object** into the SIRT, or to be NULL if the
571  // value is null and null_allowed.
572  virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
573                               ManagedRegister scratch, bool null_allowed);
574
575  // src holds a SIRT entry (Object**) load this into dst
576  virtual void LoadReferenceFromSirt(ManagedRegister dst,
577                                     ManagedRegister src);
578
579  // Heap::VerifyObject on src. In some cases (such as a reference to this) we
580  // know that src may not be null.
581  virtual void VerifyObject(ManagedRegister src, bool could_be_null);
582  virtual void VerifyObject(FrameOffset src, bool could_be_null);
583
584  // Call to address held at [base+offset]
585  virtual void Call(ManagedRegister base, Offset offset,
586                    ManagedRegister scratch);
587  virtual void Call(FrameOffset base, Offset offset,
588                    ManagedRegister scratch);
589  virtual void Call(ThreadOffset offset, ManagedRegister scratch);
590
591  // Generate code to check if Thread::Current()->exception_ is non-null
592  // and branch to a ExceptionSlowPath if it is.
593  virtual void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust);
594
595 private:
596  inline void EmitUint8(uint8_t value);
597  inline void EmitInt32(int32_t value);
598  inline void EmitRegisterOperand(int rm, int reg);
599  inline void EmitXmmRegisterOperand(int rm, XmmRegister reg);
600  inline void EmitFixup(AssemblerFixup* fixup);
601  inline void EmitOperandSizeOverride();
602
603  void EmitOperand(int rm, const Operand& operand);
604  void EmitImmediate(const Immediate& imm);
605  void EmitComplex(int rm, const Operand& operand, const Immediate& immediate);
606  void EmitLabel(Label* label, int instruction_size);
607  void EmitLabelLink(Label* label);
608  void EmitNearLabelLink(Label* label);
609
610  void EmitGenericShift(int rm, Register reg, const Immediate& imm);
611  void EmitGenericShift(int rm, Register operand, Register shifter);
612  void rex(Register &dst, Register &src, size_t size = 4);
613  void rex_reg(Register &dst, size_t size = 4);
614  void rex_rm(Register &src, size_t size = 4);
615
616  DISALLOW_COPY_AND_ASSIGN(X86_64Assembler);
617};
618
619inline void X86_64Assembler::EmitUint8(uint8_t value) {
620  buffer_.Emit<uint8_t>(value);
621}
622
623inline void X86_64Assembler::EmitInt32(int32_t value) {
624  buffer_.Emit<int32_t>(value);
625}
626
627inline void X86_64Assembler::EmitRegisterOperand(int rm, int reg) {
628  CHECK_GE(rm, 0);
629  CHECK_LT(rm, 8);
630  buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
631}
632
633inline void X86_64Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
634  EmitRegisterOperand(rm, static_cast<Register>(reg));
635}
636
637inline void X86_64Assembler::EmitFixup(AssemblerFixup* fixup) {
638  buffer_.EmitFixup(fixup);
639}
640
641inline void X86_64Assembler::EmitOperandSizeOverride() {
642  EmitUint8(0x66);
643}
644
645// Slowpath entered when Thread::Current()->_exception is non-null
646class X86ExceptionSlowPath : public SlowPath {
647 public:
648  explicit X86ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
649  virtual void Emit(Assembler *sp_asm);
650 private:
651  const size_t stack_adjust_;
652};
653
654}  // namespace x86_64
655}  // namespace art
656
657#endif  // ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
658