1200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Signed 64-bit integer multiply. 3200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a1 a0 4200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * x a3 a2 5200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * ------------- 6200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a2a1 a2a0 7200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a3a0 8200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a3a1 (<= unused) 9200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * --------------- 10200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * v1 v0 11200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* mul-long vAA, vBB, vCC */ 13200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 14200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and t0, a0, 255 # a2 <- BB 15200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl t1, a0, 8 # a3 <- CC 16200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, t0) # t0 <- &fp[BB] 17200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 18200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 19200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, t1) # t0 <- &fp[CC] 20200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 21200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 22200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul v1, a3, a0 # v1= a3a0 23200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 24200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mulu v0, a2, a0 # v0= a2a0 25200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung muhu t1, a2, a0 26200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 27200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung multu a2, a0 28200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhi t1 29200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mflo v0 # v0= a2a0 30200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 31200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul t0, a2, a1 # t0= a2a1 32200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu v1, v1, t1 # v1+= hi(a2a0) 33200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu v1, v1, t0 # v1= a3a0 + a2a1; 34200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 35200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 36200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 37200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .L${opcode}_finish 38200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung%break 39200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 40200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L${opcode}_finish: 41200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 42200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, a0) # vAA::vAA+1 <- v0(low) :: v1(high) 43200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 44