MachineInstr.cpp revision 1015ba7018c87f48cc7bb45a564eb4a27241e76a 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/Metadata.h"
19#include "llvm/Type.h"
20#include "llvm/Value.h"
21#include "llvm/Assembly/Writer.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetInstrDesc.h"
31#include "llvm/Target/TargetRegisterInfo.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/DebugInfo.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/LeakDetector.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/ADT/FoldingSet.h"
40using namespace llvm;
41
42//===----------------------------------------------------------------------===//
43// MachineOperand Implementation
44//===----------------------------------------------------------------------===//
45
46/// AddRegOperandToRegInfo - Add this register operand to the specified
47/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
48/// explicitly nulled out.
49void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50  assert(isReg() && "Can only add reg operand to use lists");
51
52  // If the reginfo pointer is null, just explicitly null out or next/prev
53  // pointers, to ensure they are not garbage.
54  if (RegInfo == 0) {
55    Contents.Reg.Prev = 0;
56    Contents.Reg.Next = 0;
57    return;
58  }
59
60  // Otherwise, add this operand to the head of the registers use/def list.
61  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
62
63  // For SSA values, we prefer to keep the definition at the start of the list.
64  // we do this by skipping over the definition if it is at the head of the
65  // list.
66  if (*Head && (*Head)->isDef())
67    Head = &(*Head)->Contents.Reg.Next;
68
69  Contents.Reg.Next = *Head;
70  if (Contents.Reg.Next) {
71    assert(getReg() == Contents.Reg.Next->getReg() &&
72           "Different regs on the same list!");
73    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
74  }
75
76  Contents.Reg.Prev = Head;
77  *Head = this;
78}
79
80/// RemoveRegOperandFromRegInfo - Remove this register operand from the
81/// MachineRegisterInfo it is linked with.
82void MachineOperand::RemoveRegOperandFromRegInfo() {
83  assert(isOnRegUseList() && "Reg operand is not on a use list");
84  // Unlink this from the doubly linked list of operands.
85  MachineOperand *NextOp = Contents.Reg.Next;
86  *Contents.Reg.Prev = NextOp;
87  if (NextOp) {
88    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
90  }
91  Contents.Reg.Prev = 0;
92  Contents.Reg.Next = 0;
93}
94
95void MachineOperand::setReg(unsigned Reg) {
96  if (getReg() == Reg) return; // No change.
97
98  // Otherwise, we have to change the register.  If this operand is embedded
99  // into a machine function, we need to update the old and new register's
100  // use/def lists.
101  if (MachineInstr *MI = getParent())
102    if (MachineBasicBlock *MBB = MI->getParent())
103      if (MachineFunction *MF = MBB->getParent()) {
104        RemoveRegOperandFromRegInfo();
105        Contents.Reg.RegNo = Reg;
106        AddRegOperandToRegInfo(&MF->getRegInfo());
107        return;
108      }
109
110  // Otherwise, just change the register, no problem.  :)
111  Contents.Reg.RegNo = Reg;
112}
113
114/// ChangeToImmediate - Replace this operand with a new immediate operand of
115/// the specified value.  If an operand is known to be an immediate already,
116/// the setImm method should be used.
117void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
118  // If this operand is currently a register operand, and if this is in a
119  // function, deregister the operand from the register's use/def list.
120  if (isReg() && getParent() && getParent()->getParent() &&
121      getParent()->getParent()->getParent())
122    RemoveRegOperandFromRegInfo();
123
124  OpKind = MO_Immediate;
125  Contents.ImmVal = ImmVal;
126}
127
128/// ChangeToRegister - Replace this operand with a new register operand of
129/// the specified value.  If an operand is known to be an register already,
130/// the setReg method should be used.
131void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
132                                      bool isKill, bool isDead, bool isUndef,
133                                      bool isDebug) {
134  // If this operand is already a register operand, use setReg to update the
135  // register's use/def lists.
136  if (isReg()) {
137    assert(!isEarlyClobber());
138    setReg(Reg);
139  } else {
140    // Otherwise, change this to a register and set the reg#.
141    OpKind = MO_Register;
142    Contents.Reg.RegNo = Reg;
143
144    // If this operand is embedded in a function, add the operand to the
145    // register's use/def list.
146    if (MachineInstr *MI = getParent())
147      if (MachineBasicBlock *MBB = MI->getParent())
148        if (MachineFunction *MF = MBB->getParent())
149          AddRegOperandToRegInfo(&MF->getRegInfo());
150  }
151
152  IsDef = isDef;
153  IsImp = isImp;
154  IsKill = isKill;
155  IsDead = isDead;
156  IsUndef = isUndef;
157  IsEarlyClobber = false;
158  IsDebug = isDebug;
159  SubReg = 0;
160}
161
162/// isIdenticalTo - Return true if this operand is identical to the specified
163/// operand.
164bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
165  if (getType() != Other.getType() ||
166      getTargetFlags() != Other.getTargetFlags())
167    return false;
168
169  switch (getType()) {
170  default: llvm_unreachable("Unrecognized operand type");
171  case MachineOperand::MO_Register:
172    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
173           getSubReg() == Other.getSubReg();
174  case MachineOperand::MO_Immediate:
175    return getImm() == Other.getImm();
176  case MachineOperand::MO_FPImmediate:
177    return getFPImm() == Other.getFPImm();
178  case MachineOperand::MO_MachineBasicBlock:
179    return getMBB() == Other.getMBB();
180  case MachineOperand::MO_FrameIndex:
181    return getIndex() == Other.getIndex();
182  case MachineOperand::MO_ConstantPoolIndex:
183    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
184  case MachineOperand::MO_JumpTableIndex:
185    return getIndex() == Other.getIndex();
186  case MachineOperand::MO_GlobalAddress:
187    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
188  case MachineOperand::MO_ExternalSymbol:
189    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
190           getOffset() == Other.getOffset();
191  case MachineOperand::MO_BlockAddress:
192    return getBlockAddress() == Other.getBlockAddress();
193  case MachineOperand::MO_MCSymbol:
194    return getMCSymbol() == Other.getMCSymbol();
195  case MachineOperand::MO_Metadata:
196    return getMetadata() == Other.getMetadata();
197  }
198}
199
200/// print - Print the specified machine operand.
201///
202void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
203  // If the instruction is embedded into a basic block, we can find the
204  // target info for the instruction.
205  if (!TM)
206    if (const MachineInstr *MI = getParent())
207      if (const MachineBasicBlock *MBB = MI->getParent())
208        if (const MachineFunction *MF = MBB->getParent())
209          TM = &MF->getTarget();
210
211  switch (getType()) {
212  case MachineOperand::MO_Register:
213    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
214      OS << "%reg" << getReg();
215    } else {
216      if (TM)
217        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
218      else
219        OS << "%physreg" << getReg();
220    }
221
222    if (getSubReg() != 0)
223      OS << ':' << getSubReg();
224
225    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
226        isEarlyClobber()) {
227      OS << '<';
228      bool NeedComma = false;
229      if (isDef()) {
230        if (NeedComma) OS << ',';
231        if (isEarlyClobber())
232          OS << "earlyclobber,";
233        if (isImplicit())
234          OS << "imp-";
235        OS << "def";
236        NeedComma = true;
237      } else if (isImplicit()) {
238          OS << "imp-use";
239          NeedComma = true;
240      }
241
242      if (isKill() || isDead() || isUndef()) {
243        if (NeedComma) OS << ',';
244        if (isKill())  OS << "kill";
245        if (isDead())  OS << "dead";
246        if (isUndef()) {
247          if (isKill() || isDead())
248            OS << ',';
249          OS << "undef";
250        }
251      }
252      OS << '>';
253    }
254    break;
255  case MachineOperand::MO_Immediate:
256    OS << getImm();
257    break;
258  case MachineOperand::MO_FPImmediate:
259    if (getFPImm()->getType()->isFloatTy())
260      OS << getFPImm()->getValueAPF().convertToFloat();
261    else
262      OS << getFPImm()->getValueAPF().convertToDouble();
263    break;
264  case MachineOperand::MO_MachineBasicBlock:
265    OS << "<BB#" << getMBB()->getNumber() << ">";
266    break;
267  case MachineOperand::MO_FrameIndex:
268    OS << "<fi#" << getIndex() << '>';
269    break;
270  case MachineOperand::MO_ConstantPoolIndex:
271    OS << "<cp#" << getIndex();
272    if (getOffset()) OS << "+" << getOffset();
273    OS << '>';
274    break;
275  case MachineOperand::MO_JumpTableIndex:
276    OS << "<jt#" << getIndex() << '>';
277    break;
278  case MachineOperand::MO_GlobalAddress:
279    OS << "<ga:";
280    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
281    if (getOffset()) OS << "+" << getOffset();
282    OS << '>';
283    break;
284  case MachineOperand::MO_ExternalSymbol:
285    OS << "<es:" << getSymbolName();
286    if (getOffset()) OS << "+" << getOffset();
287    OS << '>';
288    break;
289  case MachineOperand::MO_BlockAddress:
290    OS << '<';
291    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
292    OS << '>';
293    break;
294  case MachineOperand::MO_Metadata:
295    OS << '<';
296    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
297    OS << '>';
298    break;
299  case MachineOperand::MO_MCSymbol:
300    OS << "<MCSym=" << *getMCSymbol() << '>';
301    break;
302  default:
303    llvm_unreachable("Unrecognized operand type");
304  }
305
306  if (unsigned TF = getTargetFlags())
307    OS << "[TF=" << TF << ']';
308}
309
310//===----------------------------------------------------------------------===//
311// MachineMemOperand Implementation
312//===----------------------------------------------------------------------===//
313
314MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
315                                     int64_t o, uint64_t s, unsigned int a)
316  : Offset(o), Size(s), V(v),
317    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
318  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
319  assert((isLoad() || isStore()) && "Not a load/store!");
320}
321
322/// Profile - Gather unique data for the object.
323///
324void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
325  ID.AddInteger(Offset);
326  ID.AddInteger(Size);
327  ID.AddPointer(V);
328  ID.AddInteger(Flags);
329}
330
331void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
332  // The Value and Offset may differ due to CSE. But the flags and size
333  // should be the same.
334  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
335  assert(MMO->getSize() == getSize() && "Size mismatch!");
336
337  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
338    // Update the alignment value.
339    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
340      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
341    // Also update the base and offset, because the new alignment may
342    // not be applicable with the old ones.
343    V = MMO->getValue();
344    Offset = MMO->getOffset();
345  }
346}
347
348/// getAlignment - Return the minimum known alignment in bytes of the
349/// actual memory reference.
350uint64_t MachineMemOperand::getAlignment() const {
351  return MinAlign(getBaseAlignment(), getOffset());
352}
353
354raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
355  assert((MMO.isLoad() || MMO.isStore()) &&
356         "SV has to be a load, store or both.");
357
358  if (MMO.isVolatile())
359    OS << "Volatile ";
360
361  if (MMO.isLoad())
362    OS << "LD";
363  if (MMO.isStore())
364    OS << "ST";
365  OS << MMO.getSize();
366
367  // Print the address information.
368  OS << "[";
369  if (!MMO.getValue())
370    OS << "<unknown>";
371  else
372    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
373
374  // If the alignment of the memory reference itself differs from the alignment
375  // of the base pointer, print the base alignment explicitly, next to the base
376  // pointer.
377  if (MMO.getBaseAlignment() != MMO.getAlignment())
378    OS << "(align=" << MMO.getBaseAlignment() << ")";
379
380  if (MMO.getOffset() != 0)
381    OS << "+" << MMO.getOffset();
382  OS << "]";
383
384  // Print the alignment of the reference.
385  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
386      MMO.getBaseAlignment() != MMO.getSize())
387    OS << "(align=" << MMO.getAlignment() << ")";
388
389  return OS;
390}
391
392//===----------------------------------------------------------------------===//
393// MachineInstr Implementation
394//===----------------------------------------------------------------------===//
395
396/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
397/// TID NULL and no operands.
398MachineInstr::MachineInstr()
399  : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
400    Parent(0) {
401  // Make sure that we get added to a machine basicblock
402  LeakDetector::addGarbageObject(this);
403}
404
405void MachineInstr::addImplicitDefUseOperands() {
406  if (TID->ImplicitDefs)
407    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
408      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
409  if (TID->ImplicitUses)
410    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
411      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
412}
413
414/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
415/// implicit operands. It reserves space for the number of operands specified by
416/// the TargetInstrDesc.
417MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
418  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
419    MemRefs(0), MemRefsEnd(0), Parent(0) {
420  if (!NoImp)
421    NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
422  Operands.reserve(NumImplicitOps + TID->getNumOperands());
423  if (!NoImp)
424    addImplicitDefUseOperands();
425  // Make sure that we get added to a machine basicblock
426  LeakDetector::addGarbageObject(this);
427}
428
429/// MachineInstr ctor - As above, but with a DebugLoc.
430MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
431                           bool NoImp)
432  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
433    Parent(0), debugLoc(dl) {
434  if (!NoImp)
435    NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
436  Operands.reserve(NumImplicitOps + TID->getNumOperands());
437  if (!NoImp)
438    addImplicitDefUseOperands();
439  // Make sure that we get added to a machine basicblock
440  LeakDetector::addGarbageObject(this);
441}
442
443/// MachineInstr ctor - Work exactly the same as the ctor two above, except
444/// that the MachineInstr is created and added to the end of the specified
445/// basic block.
446MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
447  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
448    MemRefs(0), MemRefsEnd(0), Parent(0) {
449  assert(MBB && "Cannot use inserting ctor with null basic block!");
450  NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
451  Operands.reserve(NumImplicitOps + TID->getNumOperands());
452  addImplicitDefUseOperands();
453  // Make sure that we get added to a machine basicblock
454  LeakDetector::addGarbageObject(this);
455  MBB->push_back(this);  // Add instruction to end of basic block!
456}
457
458/// MachineInstr ctor - As above, but with a DebugLoc.
459///
460MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
461                           const TargetInstrDesc &tid)
462  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
463    Parent(0), debugLoc(dl) {
464  assert(MBB && "Cannot use inserting ctor with null basic block!");
465  NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
466  Operands.reserve(NumImplicitOps + TID->getNumOperands());
467  addImplicitDefUseOperands();
468  // Make sure that we get added to a machine basicblock
469  LeakDetector::addGarbageObject(this);
470  MBB->push_back(this);  // Add instruction to end of basic block!
471}
472
473/// MachineInstr ctor - Copies MachineInstr arg exactly
474///
475MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
476  : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
477    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
478    Parent(0), debugLoc(MI.getDebugLoc()) {
479  Operands.reserve(MI.getNumOperands());
480
481  // Add operands
482  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
483    addOperand(MI.getOperand(i));
484  NumImplicitOps = MI.NumImplicitOps;
485
486  // Set parent to null.
487  Parent = 0;
488
489  LeakDetector::addGarbageObject(this);
490}
491
492MachineInstr::~MachineInstr() {
493  LeakDetector::removeGarbageObject(this);
494#ifndef NDEBUG
495  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
496    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
497    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
498           "Reg operand def/use list corrupted");
499  }
500#endif
501}
502
503/// getRegInfo - If this instruction is embedded into a MachineFunction,
504/// return the MachineRegisterInfo object for the current function, otherwise
505/// return null.
506MachineRegisterInfo *MachineInstr::getRegInfo() {
507  if (MachineBasicBlock *MBB = getParent())
508    return &MBB->getParent()->getRegInfo();
509  return 0;
510}
511
512/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
513/// this instruction from their respective use lists.  This requires that the
514/// operands already be on their use lists.
515void MachineInstr::RemoveRegOperandsFromUseLists() {
516  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
517    if (Operands[i].isReg())
518      Operands[i].RemoveRegOperandFromRegInfo();
519  }
520}
521
522/// AddRegOperandsToUseLists - Add all of the register operands in
523/// this instruction from their respective use lists.  This requires that the
524/// operands not be on their use lists yet.
525void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
526  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
527    if (Operands[i].isReg())
528      Operands[i].AddRegOperandToRegInfo(&RegInfo);
529  }
530}
531
532
533/// addOperand - Add the specified operand to the instruction.  If it is an
534/// implicit operand, it is added to the end of the operand list.  If it is
535/// an explicit operand it is added at the end of the explicit operand list
536/// (before the first implicit operand).
537void MachineInstr::addOperand(const MachineOperand &Op) {
538  bool isImpReg = Op.isReg() && Op.isImplicit();
539  assert((isImpReg || !OperandsComplete()) &&
540         "Trying to add an operand to a machine instr that is already done!");
541
542  MachineRegisterInfo *RegInfo = getRegInfo();
543
544  // If we are adding the operand to the end of the list, our job is simpler.
545  // This is true most of the time, so this is a reasonable optimization.
546  if (isImpReg || NumImplicitOps == 0) {
547    // We can only do this optimization if we know that the operand list won't
548    // reallocate.
549    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
550      Operands.push_back(Op);
551
552      // Set the parent of the operand.
553      Operands.back().ParentMI = this;
554
555      // If the operand is a register, update the operand's use list.
556      if (Op.isReg()) {
557        Operands.back().AddRegOperandToRegInfo(RegInfo);
558        // If the register operand is flagged as early, mark the operand as such
559        unsigned OpNo = Operands.size() - 1;
560        if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
561          Operands[OpNo].setIsEarlyClobber(true);
562      }
563      return;
564    }
565  }
566
567  // Otherwise, we have to insert a real operand before any implicit ones.
568  unsigned OpNo = Operands.size()-NumImplicitOps;
569
570  // If this instruction isn't embedded into a function, then we don't need to
571  // update any operand lists.
572  if (RegInfo == 0) {
573    // Simple insertion, no reginfo update needed for other register operands.
574    Operands.insert(Operands.begin()+OpNo, Op);
575    Operands[OpNo].ParentMI = this;
576
577    // Do explicitly set the reginfo for this operand though, to ensure the
578    // next/prev fields are properly nulled out.
579    if (Operands[OpNo].isReg()) {
580      Operands[OpNo].AddRegOperandToRegInfo(0);
581      // If the register operand is flagged as early, mark the operand as such
582      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
583        Operands[OpNo].setIsEarlyClobber(true);
584    }
585
586  } else if (Operands.size()+1 <= Operands.capacity()) {
587    // Otherwise, we have to remove register operands from their register use
588    // list, add the operand, then add the register operands back to their use
589    // list.  This also must handle the case when the operand list reallocates
590    // to somewhere else.
591
592    // If insertion of this operand won't cause reallocation of the operand
593    // list, just remove the implicit operands, add the operand, then re-add all
594    // the rest of the operands.
595    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
596      assert(Operands[i].isReg() && "Should only be an implicit reg!");
597      Operands[i].RemoveRegOperandFromRegInfo();
598    }
599
600    // Add the operand.  If it is a register, add it to the reg list.
601    Operands.insert(Operands.begin()+OpNo, Op);
602    Operands[OpNo].ParentMI = this;
603
604    if (Operands[OpNo].isReg()) {
605      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
606      // If the register operand is flagged as early, mark the operand as such
607      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
608        Operands[OpNo].setIsEarlyClobber(true);
609    }
610
611    // Re-add all the implicit ops.
612    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
613      assert(Operands[i].isReg() && "Should only be an implicit reg!");
614      Operands[i].AddRegOperandToRegInfo(RegInfo);
615    }
616  } else {
617    // Otherwise, we will be reallocating the operand list.  Remove all reg
618    // operands from their list, then readd them after the operand list is
619    // reallocated.
620    RemoveRegOperandsFromUseLists();
621
622    Operands.insert(Operands.begin()+OpNo, Op);
623    Operands[OpNo].ParentMI = this;
624
625    // Re-add all the operands.
626    AddRegOperandsToUseLists(*RegInfo);
627
628      // If the register operand is flagged as early, mark the operand as such
629    if (Operands[OpNo].isReg()
630        && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
631      Operands[OpNo].setIsEarlyClobber(true);
632  }
633}
634
635/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
636/// fewer operand than it started with.
637///
638void MachineInstr::RemoveOperand(unsigned OpNo) {
639  assert(OpNo < Operands.size() && "Invalid operand number");
640
641  // Special case removing the last one.
642  if (OpNo == Operands.size()-1) {
643    // If needed, remove from the reg def/use list.
644    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
645      Operands.back().RemoveRegOperandFromRegInfo();
646
647    Operands.pop_back();
648    return;
649  }
650
651  // Otherwise, we are removing an interior operand.  If we have reginfo to
652  // update, remove all operands that will be shifted down from their reg lists,
653  // move everything down, then re-add them.
654  MachineRegisterInfo *RegInfo = getRegInfo();
655  if (RegInfo) {
656    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
657      if (Operands[i].isReg())
658        Operands[i].RemoveRegOperandFromRegInfo();
659    }
660  }
661
662  Operands.erase(Operands.begin()+OpNo);
663
664  if (RegInfo) {
665    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
666      if (Operands[i].isReg())
667        Operands[i].AddRegOperandToRegInfo(RegInfo);
668    }
669  }
670}
671
672/// addMemOperand - Add a MachineMemOperand to the machine instruction.
673/// This function should be used only occasionally. The setMemRefs function
674/// is the primary method for setting up a MachineInstr's MemRefs list.
675void MachineInstr::addMemOperand(MachineFunction &MF,
676                                 MachineMemOperand *MO) {
677  mmo_iterator OldMemRefs = MemRefs;
678  mmo_iterator OldMemRefsEnd = MemRefsEnd;
679
680  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
681  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
682  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
683
684  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
685  NewMemRefs[NewNum - 1] = MO;
686
687  MemRefs = NewMemRefs;
688  MemRefsEnd = NewMemRefsEnd;
689}
690
691bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
692                                 MICheckType Check) const {
693  // If opcodes or number of operands are not the same then the two
694  // instructions are obviously not identical.
695  if (Other->getOpcode() != getOpcode() ||
696      Other->getNumOperands() != getNumOperands())
697    return false;
698
699  // Check operands to make sure they match.
700  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
701    const MachineOperand &MO = getOperand(i);
702    const MachineOperand &OMO = Other->getOperand(i);
703    // Clients may or may not want to ignore defs when testing for equality.
704    // For example, machine CSE pass only cares about finding common
705    // subexpressions, so it's safe to ignore virtual register defs.
706    if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
707      if (Check == IgnoreDefs)
708        continue;
709      // Check == IgnoreVRegDefs
710      if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
711          TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
712        if (MO.getReg() != OMO.getReg())
713          return false;
714    } else if (!MO.isIdenticalTo(OMO))
715      return false;
716  }
717  return true;
718}
719
720/// removeFromParent - This method unlinks 'this' from the containing basic
721/// block, and returns it, but does not delete it.
722MachineInstr *MachineInstr::removeFromParent() {
723  assert(getParent() && "Not embedded in a basic block!");
724  getParent()->remove(this);
725  return this;
726}
727
728
729/// eraseFromParent - This method unlinks 'this' from the containing basic
730/// block, and deletes it.
731void MachineInstr::eraseFromParent() {
732  assert(getParent() && "Not embedded in a basic block!");
733  getParent()->erase(this);
734}
735
736
737/// OperandComplete - Return true if it's illegal to add a new operand
738///
739bool MachineInstr::OperandsComplete() const {
740  unsigned short NumOperands = TID->getNumOperands();
741  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
742    return true;  // Broken: we have all the operands of this instruction!
743  return false;
744}
745
746/// getNumExplicitOperands - Returns the number of non-implicit operands.
747///
748unsigned MachineInstr::getNumExplicitOperands() const {
749  unsigned NumOperands = TID->getNumOperands();
750  if (!TID->isVariadic())
751    return NumOperands;
752
753  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
754    const MachineOperand &MO = getOperand(i);
755    if (!MO.isReg() || !MO.isImplicit())
756      NumOperands++;
757  }
758  return NumOperands;
759}
760
761
762/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
763/// the specific register or -1 if it is not found. It further tightens
764/// the search criteria to a use that kills the register if isKill is true.
765int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
766                                          const TargetRegisterInfo *TRI) const {
767  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
768    const MachineOperand &MO = getOperand(i);
769    if (!MO.isReg() || !MO.isUse())
770      continue;
771    unsigned MOReg = MO.getReg();
772    if (!MOReg)
773      continue;
774    if (MOReg == Reg ||
775        (TRI &&
776         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
777         TargetRegisterInfo::isPhysicalRegister(Reg) &&
778         TRI->isSubRegister(MOReg, Reg)))
779      if (!isKill || MO.isKill())
780        return i;
781  }
782  return -1;
783}
784
785/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
786/// indicating if this instruction reads or writes Reg. This also considers
787/// partial defines.
788std::pair<bool,bool>
789MachineInstr::readsWritesVirtualRegister(unsigned Reg,
790                                         SmallVectorImpl<unsigned> *Ops) const {
791  bool PartDef = false; // Partial redefine.
792  bool FullDef = false; // Full define.
793  bool Use = false;
794
795  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
796    const MachineOperand &MO = getOperand(i);
797    if (!MO.isReg() || MO.getReg() != Reg)
798      continue;
799    if (Ops)
800      Ops->push_back(i);
801    if (MO.isUse())
802      Use |= !MO.isUndef();
803    else if (MO.getSubReg())
804      PartDef = true;
805    else
806      FullDef = true;
807  }
808  // A partial redefine uses Reg unless there is also a full define.
809  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
810}
811
812/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
813/// the specified register or -1 if it is not found. If isDead is true, defs
814/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
815/// also checks if there is a def of a super-register.
816int
817MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
818                                        const TargetRegisterInfo *TRI) const {
819  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
820  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
821    const MachineOperand &MO = getOperand(i);
822    if (!MO.isReg() || !MO.isDef())
823      continue;
824    unsigned MOReg = MO.getReg();
825    bool Found = (MOReg == Reg);
826    if (!Found && TRI && isPhys &&
827        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
828      if (Overlap)
829        Found = TRI->regsOverlap(MOReg, Reg);
830      else
831        Found = TRI->isSubRegister(MOReg, Reg);
832    }
833    if (Found && (!isDead || MO.isDead()))
834      return i;
835  }
836  return -1;
837}
838
839/// findFirstPredOperandIdx() - Find the index of the first operand in the
840/// operand list that is used to represent the predicate. It returns -1 if
841/// none is found.
842int MachineInstr::findFirstPredOperandIdx() const {
843  const TargetInstrDesc &TID = getDesc();
844  if (TID.isPredicable()) {
845    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
846      if (TID.OpInfo[i].isPredicate())
847        return i;
848  }
849
850  return -1;
851}
852
853/// isRegTiedToUseOperand - Given the index of a register def operand,
854/// check if the register def is tied to a source operand, due to either
855/// two-address elimination or inline assembly constraints. Returns the
856/// first tied use operand index by reference is UseOpIdx is not null.
857bool MachineInstr::
858isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
859  if (isInlineAsm()) {
860    assert(DefOpIdx >= 2);
861    const MachineOperand &MO = getOperand(DefOpIdx);
862    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
863      return false;
864    // Determine the actual operand index that corresponds to this index.
865    unsigned DefNo = 0;
866    unsigned DefPart = 0;
867    for (unsigned i = 1, e = getNumOperands(); i < e; ) {
868      const MachineOperand &FMO = getOperand(i);
869      // After the normal asm operands there may be additional imp-def regs.
870      if (!FMO.isImm())
871        return false;
872      // Skip over this def.
873      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
874      unsigned PrevDef = i + 1;
875      i = PrevDef + NumOps;
876      if (i > DefOpIdx) {
877        DefPart = DefOpIdx - PrevDef;
878        break;
879      }
880      ++DefNo;
881    }
882    for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
883      const MachineOperand &FMO = getOperand(i);
884      if (!FMO.isImm())
885        continue;
886      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
887        continue;
888      unsigned Idx;
889      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
890          Idx == DefNo) {
891        if (UseOpIdx)
892          *UseOpIdx = (unsigned)i + 1 + DefPart;
893        return true;
894      }
895    }
896    return false;
897  }
898
899  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
900  const TargetInstrDesc &TID = getDesc();
901  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
902    const MachineOperand &MO = getOperand(i);
903    if (MO.isReg() && MO.isUse() &&
904        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
905      if (UseOpIdx)
906        *UseOpIdx = (unsigned)i;
907      return true;
908    }
909  }
910  return false;
911}
912
913/// isRegTiedToDefOperand - Return true if the operand of the specified index
914/// is a register use and it is tied to an def operand. It also returns the def
915/// operand index by reference.
916bool MachineInstr::
917isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
918  if (isInlineAsm()) {
919    const MachineOperand &MO = getOperand(UseOpIdx);
920    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
921      return false;
922
923    // Find the flag operand corresponding to UseOpIdx
924    unsigned FlagIdx, NumOps=0;
925    for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
926      const MachineOperand &UFMO = getOperand(FlagIdx);
927      // After the normal asm operands there may be additional imp-def regs.
928      if (!UFMO.isImm())
929        return false;
930      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
931      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
932      if (UseOpIdx < FlagIdx+NumOps+1)
933        break;
934    }
935    if (FlagIdx >= UseOpIdx)
936      return false;
937    const MachineOperand &UFMO = getOperand(FlagIdx);
938    unsigned DefNo;
939    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
940      if (!DefOpIdx)
941        return true;
942
943      unsigned DefIdx = 1;
944      // Remember to adjust the index. First operand is asm string, then there
945      // is a flag for each.
946      while (DefNo) {
947        const MachineOperand &FMO = getOperand(DefIdx);
948        assert(FMO.isImm());
949        // Skip over this def.
950        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
951        --DefNo;
952      }
953      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
954      return true;
955    }
956    return false;
957  }
958
959  const TargetInstrDesc &TID = getDesc();
960  if (UseOpIdx >= TID.getNumOperands())
961    return false;
962  const MachineOperand &MO = getOperand(UseOpIdx);
963  if (!MO.isReg() || !MO.isUse())
964    return false;
965  int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
966  if (DefIdx == -1)
967    return false;
968  if (DefOpIdx)
969    *DefOpIdx = (unsigned)DefIdx;
970  return true;
971}
972
973/// clearKillInfo - Clears kill flags on all operands.
974///
975void MachineInstr::clearKillInfo() {
976  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
977    MachineOperand &MO = getOperand(i);
978    if (MO.isReg() && MO.isUse())
979      MO.setIsKill(false);
980  }
981}
982
983/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
984///
985void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
986  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
987    const MachineOperand &MO = MI->getOperand(i);
988    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
989      continue;
990    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
991      MachineOperand &MOp = getOperand(j);
992      if (!MOp.isIdenticalTo(MO))
993        continue;
994      if (MO.isKill())
995        MOp.setIsKill();
996      else
997        MOp.setIsDead();
998      break;
999    }
1000  }
1001}
1002
1003/// copyPredicates - Copies predicate operand(s) from MI.
1004void MachineInstr::copyPredicates(const MachineInstr *MI) {
1005  const TargetInstrDesc &TID = MI->getDesc();
1006  if (!TID.isPredicable())
1007    return;
1008  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1009    if (TID.OpInfo[i].isPredicate()) {
1010      // Predicated operands must be last operands.
1011      addOperand(MI->getOperand(i));
1012    }
1013  }
1014}
1015
1016/// isSafeToMove - Return true if it is safe to move this instruction. If
1017/// SawStore is set to true, it means that there is a store (or call) between
1018/// the instruction's location and its intended destination.
1019bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1020                                AliasAnalysis *AA,
1021                                bool &SawStore) const {
1022  // Ignore stuff that we obviously can't move.
1023  if (TID->mayStore() || TID->isCall()) {
1024    SawStore = true;
1025    return false;
1026  }
1027  if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
1028    return false;
1029
1030  // See if this instruction does a load.  If so, we have to guarantee that the
1031  // loaded value doesn't change between the load and the its intended
1032  // destination. The check for isInvariantLoad gives the targe the chance to
1033  // classify the load as always returning a constant, e.g. a constant pool
1034  // load.
1035  if (TID->mayLoad() && !isInvariantLoad(AA))
1036    // Otherwise, this is a real load.  If there is a store between the load and
1037    // end of block, or if the load is volatile, we can't move it.
1038    return !SawStore && !hasVolatileMemoryRef();
1039
1040  return true;
1041}
1042
1043/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1044/// instruction which defined the specified register instead of copying it.
1045bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1046                                 AliasAnalysis *AA,
1047                                 unsigned DstReg) const {
1048  bool SawStore = false;
1049  if (!TII->isTriviallyReMaterializable(this, AA) ||
1050      !isSafeToMove(TII, AA, SawStore))
1051    return false;
1052  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1053    const MachineOperand &MO = getOperand(i);
1054    if (!MO.isReg())
1055      continue;
1056    // FIXME: For now, do not remat any instruction with register operands.
1057    // Later on, we can loosen the restriction is the register operands have
1058    // not been modified between the def and use. Note, this is different from
1059    // MachineSink because the code is no longer in two-address form (at least
1060    // partially).
1061    if (MO.isUse())
1062      return false;
1063    else if (!MO.isDead() && MO.getReg() != DstReg)
1064      return false;
1065  }
1066  return true;
1067}
1068
1069/// hasVolatileMemoryRef - Return true if this instruction may have a
1070/// volatile memory reference, or if the information describing the
1071/// memory reference is not available. Return false if it is known to
1072/// have no volatile memory references.
1073bool MachineInstr::hasVolatileMemoryRef() const {
1074  // An instruction known never to access memory won't have a volatile access.
1075  if (!TID->mayStore() &&
1076      !TID->mayLoad() &&
1077      !TID->isCall() &&
1078      !TID->hasUnmodeledSideEffects())
1079    return false;
1080
1081  // Otherwise, if the instruction has no memory reference information,
1082  // conservatively assume it wasn't preserved.
1083  if (memoperands_empty())
1084    return true;
1085
1086  // Check the memory reference information for volatile references.
1087  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1088    if ((*I)->isVolatile())
1089      return true;
1090
1091  return false;
1092}
1093
1094/// isInvariantLoad - Return true if this instruction is loading from a
1095/// location whose value is invariant across the function.  For example,
1096/// loading a value from the constant pool or from the argument area
1097/// of a function if it does not change.  This should only return true of
1098/// *all* loads the instruction does are invariant (if it does multiple loads).
1099bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1100  // If the instruction doesn't load at all, it isn't an invariant load.
1101  if (!TID->mayLoad())
1102    return false;
1103
1104  // If the instruction has lost its memoperands, conservatively assume that
1105  // it may not be an invariant load.
1106  if (memoperands_empty())
1107    return false;
1108
1109  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1110
1111  for (mmo_iterator I = memoperands_begin(),
1112       E = memoperands_end(); I != E; ++I) {
1113    if ((*I)->isVolatile()) return false;
1114    if ((*I)->isStore()) return false;
1115
1116    if (const Value *V = (*I)->getValue()) {
1117      // A load from a constant PseudoSourceValue is invariant.
1118      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1119        if (PSV->isConstant(MFI))
1120          continue;
1121      // If we have an AliasAnalysis, ask it whether the memory is constant.
1122      if (AA && AA->pointsToConstantMemory(V))
1123        continue;
1124    }
1125
1126    // Otherwise assume conservatively.
1127    return false;
1128  }
1129
1130  // Everything checks out.
1131  return true;
1132}
1133
1134/// isConstantValuePHI - If the specified instruction is a PHI that always
1135/// merges together the same virtual register, return the register, otherwise
1136/// return 0.
1137unsigned MachineInstr::isConstantValuePHI() const {
1138  if (!isPHI())
1139    return 0;
1140  assert(getNumOperands() >= 3 &&
1141         "It's illegal to have a PHI without source operands");
1142
1143  unsigned Reg = getOperand(1).getReg();
1144  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1145    if (getOperand(i).getReg() != Reg)
1146      return 0;
1147  return Reg;
1148}
1149
1150/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1151///
1152bool MachineInstr::allDefsAreDead() const {
1153  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1154    const MachineOperand &MO = getOperand(i);
1155    if (!MO.isReg() || MO.isUse())
1156      continue;
1157    if (!MO.isDead())
1158      return false;
1159  }
1160  return true;
1161}
1162
1163void MachineInstr::dump() const {
1164  dbgs() << "  " << *this;
1165}
1166
1167void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1168  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1169  const MachineFunction *MF = 0;
1170  if (const MachineBasicBlock *MBB = getParent()) {
1171    MF = MBB->getParent();
1172    if (!TM && MF)
1173      TM = &MF->getTarget();
1174  }
1175
1176  // Print explicitly defined operands on the left of an assignment syntax.
1177  unsigned StartOp = 0, e = getNumOperands();
1178  for (; StartOp < e && getOperand(StartOp).isReg() &&
1179         getOperand(StartOp).isDef() &&
1180         !getOperand(StartOp).isImplicit();
1181       ++StartOp) {
1182    if (StartOp != 0) OS << ", ";
1183    getOperand(StartOp).print(OS, TM);
1184  }
1185
1186  if (StartOp != 0)
1187    OS << " = ";
1188
1189  // Print the opcode name.
1190  OS << getDesc().getName();
1191
1192  // Print the rest of the operands.
1193  bool OmittedAnyCallClobbers = false;
1194  bool FirstOp = true;
1195  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1196    const MachineOperand &MO = getOperand(i);
1197
1198    // Omit call-clobbered registers which aren't used anywhere. This makes
1199    // call instructions much less noisy on targets where calls clobber lots
1200    // of registers. Don't rely on MO.isDead() because we may be called before
1201    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1202    if (MF && getDesc().isCall() &&
1203        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1204      unsigned Reg = MO.getReg();
1205      if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1206        const MachineRegisterInfo &MRI = MF->getRegInfo();
1207        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1208          bool HasAliasLive = false;
1209          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1210               unsigned AliasReg = *Alias; ++Alias)
1211            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1212              HasAliasLive = true;
1213              break;
1214            }
1215          if (!HasAliasLive) {
1216            OmittedAnyCallClobbers = true;
1217            continue;
1218          }
1219        }
1220      }
1221    }
1222
1223    if (FirstOp) FirstOp = false; else OS << ",";
1224    OS << " ";
1225    if (i < getDesc().NumOperands) {
1226      const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1227      if (TOI.isPredicate())
1228        OS << "pred:";
1229      if (TOI.isOptionalDef())
1230        OS << "opt:";
1231    }
1232    if (isDebugValue() && MO.isMetadata()) {
1233      // Pretty print DBG_VALUE instructions.
1234      const MDNode *MD = MO.getMetadata();
1235      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1236        OS << "!\"" << MDS->getString() << '\"';
1237      else
1238        MO.print(OS, TM);
1239    } else
1240      MO.print(OS, TM);
1241  }
1242
1243  // Briefly indicate whether any call clobbers were omitted.
1244  if (OmittedAnyCallClobbers) {
1245    if (!FirstOp) OS << ",";
1246    OS << " ...";
1247  }
1248
1249  bool HaveSemi = false;
1250  if (!memoperands_empty()) {
1251    if (!HaveSemi) OS << ";"; HaveSemi = true;
1252
1253    OS << " mem:";
1254    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1255         i != e; ++i) {
1256      OS << **i;
1257      if (next(i) != e)
1258        OS << " ";
1259    }
1260  }
1261
1262  if (!debugLoc.isUnknown() && MF) {
1263    if (!HaveSemi) OS << ";";
1264
1265    // TODO: print InlinedAtLoc information
1266
1267    DIScope Scope(debugLoc.getScope(MF->getFunction()->getContext()));
1268    OS << " dbg:";
1269    // Omit the directory, since it's usually long and uninteresting.
1270    if (Scope.Verify())
1271      OS << Scope.getFilename();
1272    else
1273      OS << "<unknown>";
1274    OS << ':' << debugLoc.getLine();
1275    if (debugLoc.getCol() != 0)
1276      OS << ':' << debugLoc.getCol();
1277  }
1278
1279  OS << "\n";
1280}
1281
1282bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1283                                     const TargetRegisterInfo *RegInfo,
1284                                     bool AddIfNotFound) {
1285  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1286  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1287  bool Found = false;
1288  SmallVector<unsigned,4> DeadOps;
1289  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1290    MachineOperand &MO = getOperand(i);
1291    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1292      continue;
1293    unsigned Reg = MO.getReg();
1294    if (!Reg)
1295      continue;
1296
1297    if (Reg == IncomingReg) {
1298      if (!Found) {
1299        if (MO.isKill())
1300          // The register is already marked kill.
1301          return true;
1302        if (isPhysReg && isRegTiedToDefOperand(i))
1303          // Two-address uses of physregs must not be marked kill.
1304          return true;
1305        MO.setIsKill();
1306        Found = true;
1307      }
1308    } else if (hasAliases && MO.isKill() &&
1309               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1310      // A super-register kill already exists.
1311      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1312        return true;
1313      if (RegInfo->isSubRegister(IncomingReg, Reg))
1314        DeadOps.push_back(i);
1315    }
1316  }
1317
1318  // Trim unneeded kill operands.
1319  while (!DeadOps.empty()) {
1320    unsigned OpIdx = DeadOps.back();
1321    if (getOperand(OpIdx).isImplicit())
1322      RemoveOperand(OpIdx);
1323    else
1324      getOperand(OpIdx).setIsKill(false);
1325    DeadOps.pop_back();
1326  }
1327
1328  // If not found, this means an alias of one of the operands is killed. Add a
1329  // new implicit operand if required.
1330  if (!Found && AddIfNotFound) {
1331    addOperand(MachineOperand::CreateReg(IncomingReg,
1332                                         false /*IsDef*/,
1333                                         true  /*IsImp*/,
1334                                         true  /*IsKill*/));
1335    return true;
1336  }
1337  return Found;
1338}
1339
1340bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1341                                   const TargetRegisterInfo *RegInfo,
1342                                   bool AddIfNotFound) {
1343  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1344  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1345  bool Found = false;
1346  SmallVector<unsigned,4> DeadOps;
1347  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1348    MachineOperand &MO = getOperand(i);
1349    if (!MO.isReg() || !MO.isDef())
1350      continue;
1351    unsigned Reg = MO.getReg();
1352    if (!Reg)
1353      continue;
1354
1355    if (Reg == IncomingReg) {
1356      if (!Found) {
1357        if (MO.isDead())
1358          // The register is already marked dead.
1359          return true;
1360        MO.setIsDead();
1361        Found = true;
1362      }
1363    } else if (hasAliases && MO.isDead() &&
1364               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1365      // There exists a super-register that's marked dead.
1366      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1367        return true;
1368      if (RegInfo->getSubRegisters(IncomingReg) &&
1369          RegInfo->getSuperRegisters(Reg) &&
1370          RegInfo->isSubRegister(IncomingReg, Reg))
1371        DeadOps.push_back(i);
1372    }
1373  }
1374
1375  // Trim unneeded dead operands.
1376  while (!DeadOps.empty()) {
1377    unsigned OpIdx = DeadOps.back();
1378    if (getOperand(OpIdx).isImplicit())
1379      RemoveOperand(OpIdx);
1380    else
1381      getOperand(OpIdx).setIsDead(false);
1382    DeadOps.pop_back();
1383  }
1384
1385  // If not found, this means an alias of one of the operands is dead. Add a
1386  // new implicit operand if required.
1387  if (Found || !AddIfNotFound)
1388    return Found;
1389
1390  addOperand(MachineOperand::CreateReg(IncomingReg,
1391                                       true  /*IsDef*/,
1392                                       true  /*IsImp*/,
1393                                       false /*IsKill*/,
1394                                       true  /*IsDead*/));
1395  return true;
1396}
1397
1398void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1399                                      const TargetRegisterInfo *RegInfo) {
1400  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1401    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1402    if (MO)
1403      return;
1404  } else {
1405    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1406      const MachineOperand &MO = getOperand(i);
1407      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1408          MO.getSubReg() == 0)
1409        return;
1410    }
1411  }
1412  addOperand(MachineOperand::CreateReg(IncomingReg,
1413                                       true  /*IsDef*/,
1414                                       true  /*IsImp*/));
1415}
1416
1417unsigned
1418MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1419  unsigned Hash = MI->getOpcode() * 37;
1420  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1421    const MachineOperand &MO = MI->getOperand(i);
1422    uint64_t Key = (uint64_t)MO.getType() << 32;
1423    switch (MO.getType()) {
1424    default: break;
1425    case MachineOperand::MO_Register:
1426      if (MO.isDef() && MO.getReg() &&
1427          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1428        continue;  // Skip virtual register defs.
1429      Key |= MO.getReg();
1430      break;
1431    case MachineOperand::MO_Immediate:
1432      Key |= MO.getImm();
1433      break;
1434    case MachineOperand::MO_FrameIndex:
1435    case MachineOperand::MO_ConstantPoolIndex:
1436    case MachineOperand::MO_JumpTableIndex:
1437      Key |= MO.getIndex();
1438      break;
1439    case MachineOperand::MO_MachineBasicBlock:
1440      Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1441      break;
1442    case MachineOperand::MO_GlobalAddress:
1443      Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1444      break;
1445    case MachineOperand::MO_BlockAddress:
1446      Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1447      break;
1448    case MachineOperand::MO_MCSymbol:
1449      Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1450      break;
1451    }
1452    Key += ~(Key << 32);
1453    Key ^= (Key >> 22);
1454    Key += ~(Key << 13);
1455    Key ^= (Key >> 8);
1456    Key += (Key << 3);
1457    Key ^= (Key >> 15);
1458    Key += ~(Key << 27);
1459    Key ^= (Key >> 31);
1460    Hash = (unsigned)Key + Hash * 37;
1461  }
1462  return Hash;
1463}
1464