MachineInstr.cpp revision 19f5f71bba08e690611fa213647ac6bae814756b
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/Constants.h" 16#include "llvm/Function.h" 17#include "llvm/InlineAsm.h" 18#include "llvm/Metadata.h" 19#include "llvm/Type.h" 20#include "llvm/Value.h" 21#include "llvm/Assembly/Writer.h" 22#include "llvm/CodeGen/MachineConstantPool.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineMemOperand.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/MC/MCSymbol.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetInstrDesc.h" 31#include "llvm/Target/TargetRegisterInfo.h" 32#include "llvm/Analysis/AliasAnalysis.h" 33#include "llvm/Analysis/DebugInfo.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/LeakDetector.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include "llvm/ADT/FoldingSet.h" 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43// MachineOperand Implementation 44//===----------------------------------------------------------------------===// 45 46/// AddRegOperandToRegInfo - Add this register operand to the specified 47/// MachineRegisterInfo. If it is null, then the next/prev fields should be 48/// explicitly nulled out. 49void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 50 assert(isReg() && "Can only add reg operand to use lists"); 51 52 // If the reginfo pointer is null, just explicitly null out or next/prev 53 // pointers, to ensure they are not garbage. 54 if (RegInfo == 0) { 55 Contents.Reg.Prev = 0; 56 Contents.Reg.Next = 0; 57 return; 58 } 59 60 // Otherwise, add this operand to the head of the registers use/def list. 61 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 62 63 // For SSA values, we prefer to keep the definition at the start of the list. 64 // we do this by skipping over the definition if it is at the head of the 65 // list. 66 if (*Head && (*Head)->isDef()) 67 Head = &(*Head)->Contents.Reg.Next; 68 69 Contents.Reg.Next = *Head; 70 if (Contents.Reg.Next) { 71 assert(getReg() == Contents.Reg.Next->getReg() && 72 "Different regs on the same list!"); 73 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 74 } 75 76 Contents.Reg.Prev = Head; 77 *Head = this; 78} 79 80/// RemoveRegOperandFromRegInfo - Remove this register operand from the 81/// MachineRegisterInfo it is linked with. 82void MachineOperand::RemoveRegOperandFromRegInfo() { 83 assert(isOnRegUseList() && "Reg operand is not on a use list"); 84 // Unlink this from the doubly linked list of operands. 85 MachineOperand *NextOp = Contents.Reg.Next; 86 *Contents.Reg.Prev = NextOp; 87 if (NextOp) { 88 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); 89 NextOp->Contents.Reg.Prev = Contents.Reg.Prev; 90 } 91 Contents.Reg.Prev = 0; 92 Contents.Reg.Next = 0; 93} 94 95void MachineOperand::setReg(unsigned Reg) { 96 if (getReg() == Reg) return; // No change. 97 98 // Otherwise, we have to change the register. If this operand is embedded 99 // into a machine function, we need to update the old and new register's 100 // use/def lists. 101 if (MachineInstr *MI = getParent()) 102 if (MachineBasicBlock *MBB = MI->getParent()) 103 if (MachineFunction *MF = MBB->getParent()) { 104 RemoveRegOperandFromRegInfo(); 105 Contents.Reg.RegNo = Reg; 106 AddRegOperandToRegInfo(&MF->getRegInfo()); 107 return; 108 } 109 110 // Otherwise, just change the register, no problem. :) 111 Contents.Reg.RegNo = Reg; 112} 113 114/// ChangeToImmediate - Replace this operand with a new immediate operand of 115/// the specified value. If an operand is known to be an immediate already, 116/// the setImm method should be used. 117void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 118 // If this operand is currently a register operand, and if this is in a 119 // function, deregister the operand from the register's use/def list. 120 if (isReg() && getParent() && getParent()->getParent() && 121 getParent()->getParent()->getParent()) 122 RemoveRegOperandFromRegInfo(); 123 124 OpKind = MO_Immediate; 125 Contents.ImmVal = ImmVal; 126} 127 128/// ChangeToRegister - Replace this operand with a new register operand of 129/// the specified value. If an operand is known to be an register already, 130/// the setReg method should be used. 131void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 132 bool isKill, bool isDead, bool isUndef, 133 bool isDebug) { 134 // If this operand is already a register operand, use setReg to update the 135 // register's use/def lists. 136 if (isReg()) { 137 assert(!isEarlyClobber()); 138 setReg(Reg); 139 } else { 140 // Otherwise, change this to a register and set the reg#. 141 OpKind = MO_Register; 142 Contents.Reg.RegNo = Reg; 143 144 // If this operand is embedded in a function, add the operand to the 145 // register's use/def list. 146 if (MachineInstr *MI = getParent()) 147 if (MachineBasicBlock *MBB = MI->getParent()) 148 if (MachineFunction *MF = MBB->getParent()) 149 AddRegOperandToRegInfo(&MF->getRegInfo()); 150 } 151 152 IsDef = isDef; 153 IsImp = isImp; 154 IsKill = isKill; 155 IsDead = isDead; 156 IsUndef = isUndef; 157 IsEarlyClobber = false; 158 IsDebug = isDebug; 159 SubReg = 0; 160} 161 162/// isIdenticalTo - Return true if this operand is identical to the specified 163/// operand. 164bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 165 if (getType() != Other.getType() || 166 getTargetFlags() != Other.getTargetFlags()) 167 return false; 168 169 switch (getType()) { 170 default: llvm_unreachable("Unrecognized operand type"); 171 case MachineOperand::MO_Register: 172 return getReg() == Other.getReg() && isDef() == Other.isDef() && 173 getSubReg() == Other.getSubReg(); 174 case MachineOperand::MO_Immediate: 175 return getImm() == Other.getImm(); 176 case MachineOperand::MO_FPImmediate: 177 return getFPImm() == Other.getFPImm(); 178 case MachineOperand::MO_MachineBasicBlock: 179 return getMBB() == Other.getMBB(); 180 case MachineOperand::MO_FrameIndex: 181 return getIndex() == Other.getIndex(); 182 case MachineOperand::MO_ConstantPoolIndex: 183 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 184 case MachineOperand::MO_JumpTableIndex: 185 return getIndex() == Other.getIndex(); 186 case MachineOperand::MO_GlobalAddress: 187 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 188 case MachineOperand::MO_ExternalSymbol: 189 return !strcmp(getSymbolName(), Other.getSymbolName()) && 190 getOffset() == Other.getOffset(); 191 case MachineOperand::MO_BlockAddress: 192 return getBlockAddress() == Other.getBlockAddress(); 193 case MachineOperand::MO_MCSymbol: 194 return getMCSymbol() == Other.getMCSymbol(); 195 case MachineOperand::MO_Metadata: 196 return getMetadata() == Other.getMetadata(); 197 } 198} 199 200/// print - Print the specified machine operand. 201/// 202void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 203 // If the instruction is embedded into a basic block, we can find the 204 // target info for the instruction. 205 if (!TM) 206 if (const MachineInstr *MI = getParent()) 207 if (const MachineBasicBlock *MBB = MI->getParent()) 208 if (const MachineFunction *MF = MBB->getParent()) 209 TM = &MF->getTarget(); 210 211 switch (getType()) { 212 case MachineOperand::MO_Register: 213 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { 214 OS << "%reg" << getReg(); 215 } else { 216 if (TM) 217 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 218 else 219 OS << "%physreg" << getReg(); 220 } 221 222 if (getSubReg() != 0) 223 OS << ':' << getSubReg(); 224 225 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 226 isEarlyClobber()) { 227 OS << '<'; 228 bool NeedComma = false; 229 if (isDef()) { 230 if (NeedComma) OS << ','; 231 if (isEarlyClobber()) 232 OS << "earlyclobber,"; 233 if (isImplicit()) 234 OS << "imp-"; 235 OS << "def"; 236 NeedComma = true; 237 } else if (isImplicit()) { 238 OS << "imp-use"; 239 NeedComma = true; 240 } 241 242 if (isKill() || isDead() || isUndef()) { 243 if (NeedComma) OS << ','; 244 if (isKill()) OS << "kill"; 245 if (isDead()) OS << "dead"; 246 if (isUndef()) { 247 if (isKill() || isDead()) 248 OS << ','; 249 OS << "undef"; 250 } 251 } 252 OS << '>'; 253 } 254 break; 255 case MachineOperand::MO_Immediate: 256 OS << getImm(); 257 break; 258 case MachineOperand::MO_FPImmediate: 259 if (getFPImm()->getType()->isFloatTy()) 260 OS << getFPImm()->getValueAPF().convertToFloat(); 261 else 262 OS << getFPImm()->getValueAPF().convertToDouble(); 263 break; 264 case MachineOperand::MO_MachineBasicBlock: 265 OS << "<BB#" << getMBB()->getNumber() << ">"; 266 break; 267 case MachineOperand::MO_FrameIndex: 268 OS << "<fi#" << getIndex() << '>'; 269 break; 270 case MachineOperand::MO_ConstantPoolIndex: 271 OS << "<cp#" << getIndex(); 272 if (getOffset()) OS << "+" << getOffset(); 273 OS << '>'; 274 break; 275 case MachineOperand::MO_JumpTableIndex: 276 OS << "<jt#" << getIndex() << '>'; 277 break; 278 case MachineOperand::MO_GlobalAddress: 279 OS << "<ga:"; 280 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 281 if (getOffset()) OS << "+" << getOffset(); 282 OS << '>'; 283 break; 284 case MachineOperand::MO_ExternalSymbol: 285 OS << "<es:" << getSymbolName(); 286 if (getOffset()) OS << "+" << getOffset(); 287 OS << '>'; 288 break; 289 case MachineOperand::MO_BlockAddress: 290 OS << '<'; 291 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 292 OS << '>'; 293 break; 294 case MachineOperand::MO_Metadata: 295 OS << '<'; 296 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 297 OS << '>'; 298 break; 299 case MachineOperand::MO_MCSymbol: 300 OS << "<MCSym=" << *getMCSymbol() << '>'; 301 break; 302 default: 303 llvm_unreachable("Unrecognized operand type"); 304 } 305 306 if (unsigned TF = getTargetFlags()) 307 OS << "[TF=" << TF << ']'; 308} 309 310//===----------------------------------------------------------------------===// 311// MachineMemOperand Implementation 312//===----------------------------------------------------------------------===// 313 314MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, 315 int64_t o, uint64_t s, unsigned int a) 316 : Offset(o), Size(s), V(v), 317 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) { 318 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 319 assert((isLoad() || isStore()) && "Not a load/store!"); 320} 321 322/// Profile - Gather unique data for the object. 323/// 324void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 325 ID.AddInteger(Offset); 326 ID.AddInteger(Size); 327 ID.AddPointer(V); 328 ID.AddInteger(Flags); 329} 330 331void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 332 // The Value and Offset may differ due to CSE. But the flags and size 333 // should be the same. 334 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 335 assert(MMO->getSize() == getSize() && "Size mismatch!"); 336 337 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 338 // Update the alignment value. 339 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 340 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 341 // Also update the base and offset, because the new alignment may 342 // not be applicable with the old ones. 343 V = MMO->getValue(); 344 Offset = MMO->getOffset(); 345 } 346} 347 348/// getAlignment - Return the minimum known alignment in bytes of the 349/// actual memory reference. 350uint64_t MachineMemOperand::getAlignment() const { 351 return MinAlign(getBaseAlignment(), getOffset()); 352} 353 354raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 355 assert((MMO.isLoad() || MMO.isStore()) && 356 "SV has to be a load, store or both."); 357 358 if (MMO.isVolatile()) 359 OS << "Volatile "; 360 361 if (MMO.isLoad()) 362 OS << "LD"; 363 if (MMO.isStore()) 364 OS << "ST"; 365 OS << MMO.getSize(); 366 367 // Print the address information. 368 OS << "["; 369 if (!MMO.getValue()) 370 OS << "<unknown>"; 371 else 372 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 373 374 // If the alignment of the memory reference itself differs from the alignment 375 // of the base pointer, print the base alignment explicitly, next to the base 376 // pointer. 377 if (MMO.getBaseAlignment() != MMO.getAlignment()) 378 OS << "(align=" << MMO.getBaseAlignment() << ")"; 379 380 if (MMO.getOffset() != 0) 381 OS << "+" << MMO.getOffset(); 382 OS << "]"; 383 384 // Print the alignment of the reference. 385 if (MMO.getBaseAlignment() != MMO.getAlignment() || 386 MMO.getBaseAlignment() != MMO.getSize()) 387 OS << "(align=" << MMO.getAlignment() << ")"; 388 389 return OS; 390} 391 392//===----------------------------------------------------------------------===// 393// MachineInstr Implementation 394//===----------------------------------------------------------------------===// 395 396/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 397/// TID NULL and no operands. 398MachineInstr::MachineInstr() 399 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 400 Parent(0) { 401 // Make sure that we get added to a machine basicblock 402 LeakDetector::addGarbageObject(this); 403} 404 405void MachineInstr::addImplicitDefUseOperands() { 406 if (TID->ImplicitDefs) 407 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 408 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 409 if (TID->ImplicitUses) 410 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 411 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 412} 413 414/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 415/// implicit operands. It reserves space for the number of operands specified by 416/// the TargetInstrDesc. 417MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 418 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), 419 MemRefs(0), MemRefsEnd(0), Parent(0) { 420 if (!NoImp) 421 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses(); 422 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 423 if (!NoImp) 424 addImplicitDefUseOperands(); 425 // Make sure that we get added to a machine basicblock 426 LeakDetector::addGarbageObject(this); 427} 428 429/// MachineInstr ctor - As above, but with a DebugLoc. 430MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, 431 bool NoImp) 432 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 433 Parent(0), debugLoc(dl) { 434 if (!NoImp) 435 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses(); 436 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 437 if (!NoImp) 438 addImplicitDefUseOperands(); 439 // Make sure that we get added to a machine basicblock 440 LeakDetector::addGarbageObject(this); 441} 442 443/// MachineInstr ctor - Work exactly the same as the ctor two above, except 444/// that the MachineInstr is created and added to the end of the specified 445/// basic block. 446MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) 447 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), 448 MemRefs(0), MemRefsEnd(0), Parent(0) { 449 assert(MBB && "Cannot use inserting ctor with null basic block!"); 450 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses(); 451 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 452 addImplicitDefUseOperands(); 453 // Make sure that we get added to a machine basicblock 454 LeakDetector::addGarbageObject(this); 455 MBB->push_back(this); // Add instruction to end of basic block! 456} 457 458/// MachineInstr ctor - As above, but with a DebugLoc. 459/// 460MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 461 const TargetInstrDesc &tid) 462 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 463 Parent(0), debugLoc(dl) { 464 assert(MBB && "Cannot use inserting ctor with null basic block!"); 465 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses(); 466 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 467 addImplicitDefUseOperands(); 468 // Make sure that we get added to a machine basicblock 469 LeakDetector::addGarbageObject(this); 470 MBB->push_back(this); // Add instruction to end of basic block! 471} 472 473/// MachineInstr ctor - Copies MachineInstr arg exactly 474/// 475MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 476 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0), 477 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), 478 Parent(0), debugLoc(MI.getDebugLoc()) { 479 Operands.reserve(MI.getNumOperands()); 480 481 // Add operands 482 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 483 addOperand(MI.getOperand(i)); 484 NumImplicitOps = MI.NumImplicitOps; 485 486 // Set parent to null. 487 Parent = 0; 488 489 LeakDetector::addGarbageObject(this); 490} 491 492MachineInstr::~MachineInstr() { 493 LeakDetector::removeGarbageObject(this); 494#ifndef NDEBUG 495 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 496 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 497 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 498 "Reg operand def/use list corrupted"); 499 } 500#endif 501} 502 503/// getRegInfo - If this instruction is embedded into a MachineFunction, 504/// return the MachineRegisterInfo object for the current function, otherwise 505/// return null. 506MachineRegisterInfo *MachineInstr::getRegInfo() { 507 if (MachineBasicBlock *MBB = getParent()) 508 return &MBB->getParent()->getRegInfo(); 509 return 0; 510} 511 512/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 513/// this instruction from their respective use lists. This requires that the 514/// operands already be on their use lists. 515void MachineInstr::RemoveRegOperandsFromUseLists() { 516 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 517 if (Operands[i].isReg()) 518 Operands[i].RemoveRegOperandFromRegInfo(); 519 } 520} 521 522/// AddRegOperandsToUseLists - Add all of the register operands in 523/// this instruction from their respective use lists. This requires that the 524/// operands not be on their use lists yet. 525void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 526 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 527 if (Operands[i].isReg()) 528 Operands[i].AddRegOperandToRegInfo(&RegInfo); 529 } 530} 531 532 533/// addOperand - Add the specified operand to the instruction. If it is an 534/// implicit operand, it is added to the end of the operand list. If it is 535/// an explicit operand it is added at the end of the explicit operand list 536/// (before the first implicit operand). 537void MachineInstr::addOperand(const MachineOperand &Op) { 538 bool isImpReg = Op.isReg() && Op.isImplicit(); 539 assert((isImpReg || !OperandsComplete()) && 540 "Trying to add an operand to a machine instr that is already done!"); 541 542 MachineRegisterInfo *RegInfo = getRegInfo(); 543 544 // If we are adding the operand to the end of the list, our job is simpler. 545 // This is true most of the time, so this is a reasonable optimization. 546 if (isImpReg || NumImplicitOps == 0) { 547 // We can only do this optimization if we know that the operand list won't 548 // reallocate. 549 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 550 Operands.push_back(Op); 551 552 // Set the parent of the operand. 553 Operands.back().ParentMI = this; 554 555 // If the operand is a register, update the operand's use list. 556 if (Op.isReg()) { 557 Operands.back().AddRegOperandToRegInfo(RegInfo); 558 // If the register operand is flagged as early, mark the operand as such 559 unsigned OpNo = Operands.size() - 1; 560 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 561 Operands[OpNo].setIsEarlyClobber(true); 562 } 563 return; 564 } 565 } 566 567 // Otherwise, we have to insert a real operand before any implicit ones. 568 unsigned OpNo = Operands.size()-NumImplicitOps; 569 570 // If this instruction isn't embedded into a function, then we don't need to 571 // update any operand lists. 572 if (RegInfo == 0) { 573 // Simple insertion, no reginfo update needed for other register operands. 574 Operands.insert(Operands.begin()+OpNo, Op); 575 Operands[OpNo].ParentMI = this; 576 577 // Do explicitly set the reginfo for this operand though, to ensure the 578 // next/prev fields are properly nulled out. 579 if (Operands[OpNo].isReg()) { 580 Operands[OpNo].AddRegOperandToRegInfo(0); 581 // If the register operand is flagged as early, mark the operand as such 582 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 583 Operands[OpNo].setIsEarlyClobber(true); 584 } 585 586 } else if (Operands.size()+1 <= Operands.capacity()) { 587 // Otherwise, we have to remove register operands from their register use 588 // list, add the operand, then add the register operands back to their use 589 // list. This also must handle the case when the operand list reallocates 590 // to somewhere else. 591 592 // If insertion of this operand won't cause reallocation of the operand 593 // list, just remove the implicit operands, add the operand, then re-add all 594 // the rest of the operands. 595 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 596 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 597 Operands[i].RemoveRegOperandFromRegInfo(); 598 } 599 600 // Add the operand. If it is a register, add it to the reg list. 601 Operands.insert(Operands.begin()+OpNo, Op); 602 Operands[OpNo].ParentMI = this; 603 604 if (Operands[OpNo].isReg()) { 605 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 606 // If the register operand is flagged as early, mark the operand as such 607 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 608 Operands[OpNo].setIsEarlyClobber(true); 609 } 610 611 // Re-add all the implicit ops. 612 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 613 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 614 Operands[i].AddRegOperandToRegInfo(RegInfo); 615 } 616 } else { 617 // Otherwise, we will be reallocating the operand list. Remove all reg 618 // operands from their list, then readd them after the operand list is 619 // reallocated. 620 RemoveRegOperandsFromUseLists(); 621 622 Operands.insert(Operands.begin()+OpNo, Op); 623 Operands[OpNo].ParentMI = this; 624 625 // Re-add all the operands. 626 AddRegOperandsToUseLists(*RegInfo); 627 628 // If the register operand is flagged as early, mark the operand as such 629 if (Operands[OpNo].isReg() 630 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 631 Operands[OpNo].setIsEarlyClobber(true); 632 } 633} 634 635/// RemoveOperand - Erase an operand from an instruction, leaving it with one 636/// fewer operand than it started with. 637/// 638void MachineInstr::RemoveOperand(unsigned OpNo) { 639 assert(OpNo < Operands.size() && "Invalid operand number"); 640 641 // Special case removing the last one. 642 if (OpNo == Operands.size()-1) { 643 // If needed, remove from the reg def/use list. 644 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 645 Operands.back().RemoveRegOperandFromRegInfo(); 646 647 Operands.pop_back(); 648 return; 649 } 650 651 // Otherwise, we are removing an interior operand. If we have reginfo to 652 // update, remove all operands that will be shifted down from their reg lists, 653 // move everything down, then re-add them. 654 MachineRegisterInfo *RegInfo = getRegInfo(); 655 if (RegInfo) { 656 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 657 if (Operands[i].isReg()) 658 Operands[i].RemoveRegOperandFromRegInfo(); 659 } 660 } 661 662 Operands.erase(Operands.begin()+OpNo); 663 664 if (RegInfo) { 665 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 666 if (Operands[i].isReg()) 667 Operands[i].AddRegOperandToRegInfo(RegInfo); 668 } 669 } 670} 671 672/// addMemOperand - Add a MachineMemOperand to the machine instruction. 673/// This function should be used only occasionally. The setMemRefs function 674/// is the primary method for setting up a MachineInstr's MemRefs list. 675void MachineInstr::addMemOperand(MachineFunction &MF, 676 MachineMemOperand *MO) { 677 mmo_iterator OldMemRefs = MemRefs; 678 mmo_iterator OldMemRefsEnd = MemRefsEnd; 679 680 size_t NewNum = (MemRefsEnd - MemRefs) + 1; 681 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 682 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum; 683 684 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs); 685 NewMemRefs[NewNum - 1] = MO; 686 687 MemRefs = NewMemRefs; 688 MemRefsEnd = NewMemRefsEnd; 689} 690 691bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 692 MICheckType Check) const { 693 // If opcodes or number of operands are not the same then the two 694 // instructions are obviously not identical. 695 if (Other->getOpcode() != getOpcode() || 696 Other->getNumOperands() != getNumOperands()) 697 return false; 698 699 // Check operands to make sure they match. 700 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 701 const MachineOperand &MO = getOperand(i); 702 const MachineOperand &OMO = Other->getOperand(i); 703 // Clients may or may not want to ignore defs when testing for equality. 704 // For example, machine CSE pass only cares about finding common 705 // subexpressions, so it's safe to ignore virtual register defs. 706 if (Check != CheckDefs && MO.isReg() && MO.isDef()) { 707 if (Check == IgnoreDefs) 708 continue; 709 // Check == IgnoreVRegDefs 710 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 711 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 712 if (MO.getReg() != OMO.getReg()) 713 return false; 714 } else if (!MO.isIdenticalTo(OMO)) 715 return false; 716 } 717 return true; 718} 719 720/// removeFromParent - This method unlinks 'this' from the containing basic 721/// block, and returns it, but does not delete it. 722MachineInstr *MachineInstr::removeFromParent() { 723 assert(getParent() && "Not embedded in a basic block!"); 724 getParent()->remove(this); 725 return this; 726} 727 728 729/// eraseFromParent - This method unlinks 'this' from the containing basic 730/// block, and deletes it. 731void MachineInstr::eraseFromParent() { 732 assert(getParent() && "Not embedded in a basic block!"); 733 getParent()->erase(this); 734} 735 736 737/// OperandComplete - Return true if it's illegal to add a new operand 738/// 739bool MachineInstr::OperandsComplete() const { 740 unsigned short NumOperands = TID->getNumOperands(); 741 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 742 return true; // Broken: we have all the operands of this instruction! 743 return false; 744} 745 746/// getNumExplicitOperands - Returns the number of non-implicit operands. 747/// 748unsigned MachineInstr::getNumExplicitOperands() const { 749 unsigned NumOperands = TID->getNumOperands(); 750 if (!TID->isVariadic()) 751 return NumOperands; 752 753 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 754 const MachineOperand &MO = getOperand(i); 755 if (!MO.isReg() || !MO.isImplicit()) 756 NumOperands++; 757 } 758 return NumOperands; 759} 760 761 762/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 763/// the specific register or -1 if it is not found. It further tightens 764/// the search criteria to a use that kills the register if isKill is true. 765int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 766 const TargetRegisterInfo *TRI) const { 767 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 768 const MachineOperand &MO = getOperand(i); 769 if (!MO.isReg() || !MO.isUse()) 770 continue; 771 unsigned MOReg = MO.getReg(); 772 if (!MOReg) 773 continue; 774 if (MOReg == Reg || 775 (TRI && 776 TargetRegisterInfo::isPhysicalRegister(MOReg) && 777 TargetRegisterInfo::isPhysicalRegister(Reg) && 778 TRI->isSubRegister(MOReg, Reg))) 779 if (!isKill || MO.isKill()) 780 return i; 781 } 782 return -1; 783} 784 785/// readsVirtualRegister - Return true if the MachineInstr reads the specified 786/// virtual register. Take into account that a partial define is a 787/// read-modify-write operation. 788bool MachineInstr::readsVirtualRegister(unsigned Reg) const { 789 bool PartDef = false; // Partial redefine 790 bool FullDef = false; // Full define 791 792 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 793 const MachineOperand &MO = getOperand(i); 794 if (!MO.isReg() || MO.getReg() != Reg) 795 continue; 796 if (MO.isUse()) 797 return true; 798 if (MO.getSubReg()) 799 PartDef = true; 800 else 801 FullDef = true; 802 } 803 // A partial register definition causes a read unless the full register is 804 // also defined. 805 return PartDef && !FullDef; 806} 807 808/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 809/// the specified register or -1 if it is not found. If isDead is true, defs 810/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 811/// also checks if there is a def of a super-register. 812int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, 813 const TargetRegisterInfo *TRI) const { 814 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 815 const MachineOperand &MO = getOperand(i); 816 if (!MO.isReg() || !MO.isDef()) 817 continue; 818 unsigned MOReg = MO.getReg(); 819 if (MOReg == Reg || 820 (TRI && 821 TargetRegisterInfo::isPhysicalRegister(MOReg) && 822 TargetRegisterInfo::isPhysicalRegister(Reg) && 823 TRI->isSubRegister(MOReg, Reg))) 824 if (!isDead || MO.isDead()) 825 return i; 826 } 827 return -1; 828} 829 830/// findFirstPredOperandIdx() - Find the index of the first operand in the 831/// operand list that is used to represent the predicate. It returns -1 if 832/// none is found. 833int MachineInstr::findFirstPredOperandIdx() const { 834 const TargetInstrDesc &TID = getDesc(); 835 if (TID.isPredicable()) { 836 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 837 if (TID.OpInfo[i].isPredicate()) 838 return i; 839 } 840 841 return -1; 842} 843 844/// isRegTiedToUseOperand - Given the index of a register def operand, 845/// check if the register def is tied to a source operand, due to either 846/// two-address elimination or inline assembly constraints. Returns the 847/// first tied use operand index by reference is UseOpIdx is not null. 848bool MachineInstr:: 849isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 850 if (isInlineAsm()) { 851 assert(DefOpIdx >= 2); 852 const MachineOperand &MO = getOperand(DefOpIdx); 853 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 854 return false; 855 // Determine the actual operand index that corresponds to this index. 856 unsigned DefNo = 0; 857 unsigned DefPart = 0; 858 for (unsigned i = 1, e = getNumOperands(); i < e; ) { 859 const MachineOperand &FMO = getOperand(i); 860 // After the normal asm operands there may be additional imp-def regs. 861 if (!FMO.isImm()) 862 return false; 863 // Skip over this def. 864 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm()); 865 unsigned PrevDef = i + 1; 866 i = PrevDef + NumOps; 867 if (i > DefOpIdx) { 868 DefPart = DefOpIdx - PrevDef; 869 break; 870 } 871 ++DefNo; 872 } 873 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) { 874 const MachineOperand &FMO = getOperand(i); 875 if (!FMO.isImm()) 876 continue; 877 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 878 continue; 879 unsigned Idx; 880 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 881 Idx == DefNo) { 882 if (UseOpIdx) 883 *UseOpIdx = (unsigned)i + 1 + DefPart; 884 return true; 885 } 886 } 887 return false; 888 } 889 890 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 891 const TargetInstrDesc &TID = getDesc(); 892 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 893 const MachineOperand &MO = getOperand(i); 894 if (MO.isReg() && MO.isUse() && 895 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) { 896 if (UseOpIdx) 897 *UseOpIdx = (unsigned)i; 898 return true; 899 } 900 } 901 return false; 902} 903 904/// isRegTiedToDefOperand - Return true if the operand of the specified index 905/// is a register use and it is tied to an def operand. It also returns the def 906/// operand index by reference. 907bool MachineInstr:: 908isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 909 if (isInlineAsm()) { 910 const MachineOperand &MO = getOperand(UseOpIdx); 911 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 912 return false; 913 914 // Find the flag operand corresponding to UseOpIdx 915 unsigned FlagIdx, NumOps=0; 916 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) { 917 const MachineOperand &UFMO = getOperand(FlagIdx); 918 // After the normal asm operands there may be additional imp-def regs. 919 if (!UFMO.isImm()) 920 return false; 921 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm()); 922 assert(NumOps < getNumOperands() && "Invalid inline asm flag"); 923 if (UseOpIdx < FlagIdx+NumOps+1) 924 break; 925 } 926 if (FlagIdx >= UseOpIdx) 927 return false; 928 const MachineOperand &UFMO = getOperand(FlagIdx); 929 unsigned DefNo; 930 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 931 if (!DefOpIdx) 932 return true; 933 934 unsigned DefIdx = 1; 935 // Remember to adjust the index. First operand is asm string, then there 936 // is a flag for each. 937 while (DefNo) { 938 const MachineOperand &FMO = getOperand(DefIdx); 939 assert(FMO.isImm()); 940 // Skip over this def. 941 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 942 --DefNo; 943 } 944 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 945 return true; 946 } 947 return false; 948 } 949 950 const TargetInstrDesc &TID = getDesc(); 951 if (UseOpIdx >= TID.getNumOperands()) 952 return false; 953 const MachineOperand &MO = getOperand(UseOpIdx); 954 if (!MO.isReg() || !MO.isUse()) 955 return false; 956 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO); 957 if (DefIdx == -1) 958 return false; 959 if (DefOpIdx) 960 *DefOpIdx = (unsigned)DefIdx; 961 return true; 962} 963 964/// clearKillInfo - Clears kill flags on all operands. 965/// 966void MachineInstr::clearKillInfo() { 967 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 968 MachineOperand &MO = getOperand(i); 969 if (MO.isReg() && MO.isUse()) 970 MO.setIsKill(false); 971 } 972} 973 974/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 975/// 976void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 977 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 978 const MachineOperand &MO = MI->getOperand(i); 979 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 980 continue; 981 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 982 MachineOperand &MOp = getOperand(j); 983 if (!MOp.isIdenticalTo(MO)) 984 continue; 985 if (MO.isKill()) 986 MOp.setIsKill(); 987 else 988 MOp.setIsDead(); 989 break; 990 } 991 } 992} 993 994/// copyPredicates - Copies predicate operand(s) from MI. 995void MachineInstr::copyPredicates(const MachineInstr *MI) { 996 const TargetInstrDesc &TID = MI->getDesc(); 997 if (!TID.isPredicable()) 998 return; 999 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1000 if (TID.OpInfo[i].isPredicate()) { 1001 // Predicated operands must be last operands. 1002 addOperand(MI->getOperand(i)); 1003 } 1004 } 1005} 1006 1007/// isSafeToMove - Return true if it is safe to move this instruction. If 1008/// SawStore is set to true, it means that there is a store (or call) between 1009/// the instruction's location and its intended destination. 1010bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1011 AliasAnalysis *AA, 1012 bool &SawStore) const { 1013 // Ignore stuff that we obviously can't move. 1014 if (TID->mayStore() || TID->isCall()) { 1015 SawStore = true; 1016 return false; 1017 } 1018 if (TID->isTerminator() || TID->hasUnmodeledSideEffects()) 1019 return false; 1020 1021 // See if this instruction does a load. If so, we have to guarantee that the 1022 // loaded value doesn't change between the load and the its intended 1023 // destination. The check for isInvariantLoad gives the targe the chance to 1024 // classify the load as always returning a constant, e.g. a constant pool 1025 // load. 1026 if (TID->mayLoad() && !isInvariantLoad(AA)) 1027 // Otherwise, this is a real load. If there is a store between the load and 1028 // end of block, or if the load is volatile, we can't move it. 1029 return !SawStore && !hasVolatileMemoryRef(); 1030 1031 return true; 1032} 1033 1034/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1035/// instruction which defined the specified register instead of copying it. 1036bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1037 AliasAnalysis *AA, 1038 unsigned DstReg) const { 1039 bool SawStore = false; 1040 if (!TII->isTriviallyReMaterializable(this, AA) || 1041 !isSafeToMove(TII, AA, SawStore)) 1042 return false; 1043 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1044 const MachineOperand &MO = getOperand(i); 1045 if (!MO.isReg()) 1046 continue; 1047 // FIXME: For now, do not remat any instruction with register operands. 1048 // Later on, we can loosen the restriction is the register operands have 1049 // not been modified between the def and use. Note, this is different from 1050 // MachineSink because the code is no longer in two-address form (at least 1051 // partially). 1052 if (MO.isUse()) 1053 return false; 1054 else if (!MO.isDead() && MO.getReg() != DstReg) 1055 return false; 1056 } 1057 return true; 1058} 1059 1060/// hasVolatileMemoryRef - Return true if this instruction may have a 1061/// volatile memory reference, or if the information describing the 1062/// memory reference is not available. Return false if it is known to 1063/// have no volatile memory references. 1064bool MachineInstr::hasVolatileMemoryRef() const { 1065 // An instruction known never to access memory won't have a volatile access. 1066 if (!TID->mayStore() && 1067 !TID->mayLoad() && 1068 !TID->isCall() && 1069 !TID->hasUnmodeledSideEffects()) 1070 return false; 1071 1072 // Otherwise, if the instruction has no memory reference information, 1073 // conservatively assume it wasn't preserved. 1074 if (memoperands_empty()) 1075 return true; 1076 1077 // Check the memory reference information for volatile references. 1078 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1079 if ((*I)->isVolatile()) 1080 return true; 1081 1082 return false; 1083} 1084 1085/// isInvariantLoad - Return true if this instruction is loading from a 1086/// location whose value is invariant across the function. For example, 1087/// loading a value from the constant pool or from the argument area 1088/// of a function if it does not change. This should only return true of 1089/// *all* loads the instruction does are invariant (if it does multiple loads). 1090bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1091 // If the instruction doesn't load at all, it isn't an invariant load. 1092 if (!TID->mayLoad()) 1093 return false; 1094 1095 // If the instruction has lost its memoperands, conservatively assume that 1096 // it may not be an invariant load. 1097 if (memoperands_empty()) 1098 return false; 1099 1100 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1101 1102 for (mmo_iterator I = memoperands_begin(), 1103 E = memoperands_end(); I != E; ++I) { 1104 if ((*I)->isVolatile()) return false; 1105 if ((*I)->isStore()) return false; 1106 1107 if (const Value *V = (*I)->getValue()) { 1108 // A load from a constant PseudoSourceValue is invariant. 1109 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1110 if (PSV->isConstant(MFI)) 1111 continue; 1112 // If we have an AliasAnalysis, ask it whether the memory is constant. 1113 if (AA && AA->pointsToConstantMemory(V)) 1114 continue; 1115 } 1116 1117 // Otherwise assume conservatively. 1118 return false; 1119 } 1120 1121 // Everything checks out. 1122 return true; 1123} 1124 1125/// isConstantValuePHI - If the specified instruction is a PHI that always 1126/// merges together the same virtual register, return the register, otherwise 1127/// return 0. 1128unsigned MachineInstr::isConstantValuePHI() const { 1129 if (!isPHI()) 1130 return 0; 1131 assert(getNumOperands() >= 3 && 1132 "It's illegal to have a PHI without source operands"); 1133 1134 unsigned Reg = getOperand(1).getReg(); 1135 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1136 if (getOperand(i).getReg() != Reg) 1137 return 0; 1138 return Reg; 1139} 1140 1141/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1142/// 1143bool MachineInstr::allDefsAreDead() const { 1144 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1145 const MachineOperand &MO = getOperand(i); 1146 if (!MO.isReg() || MO.isUse()) 1147 continue; 1148 if (!MO.isDead()) 1149 return false; 1150 } 1151 return true; 1152} 1153 1154void MachineInstr::dump() const { 1155 dbgs() << " " << *this; 1156} 1157 1158void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1159 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1160 const MachineFunction *MF = 0; 1161 if (const MachineBasicBlock *MBB = getParent()) { 1162 MF = MBB->getParent(); 1163 if (!TM && MF) 1164 TM = &MF->getTarget(); 1165 } 1166 1167 // Print explicitly defined operands on the left of an assignment syntax. 1168 unsigned StartOp = 0, e = getNumOperands(); 1169 for (; StartOp < e && getOperand(StartOp).isReg() && 1170 getOperand(StartOp).isDef() && 1171 !getOperand(StartOp).isImplicit(); 1172 ++StartOp) { 1173 if (StartOp != 0) OS << ", "; 1174 getOperand(StartOp).print(OS, TM); 1175 } 1176 1177 if (StartOp != 0) 1178 OS << " = "; 1179 1180 // Print the opcode name. 1181 OS << getDesc().getName(); 1182 1183 // Print the rest of the operands. 1184 bool OmittedAnyCallClobbers = false; 1185 bool FirstOp = true; 1186 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1187 const MachineOperand &MO = getOperand(i); 1188 1189 // Omit call-clobbered registers which aren't used anywhere. This makes 1190 // call instructions much less noisy on targets where calls clobber lots 1191 // of registers. Don't rely on MO.isDead() because we may be called before 1192 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1193 if (MF && getDesc().isCall() && 1194 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1195 unsigned Reg = MO.getReg(); 1196 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) { 1197 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1198 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1199 bool HasAliasLive = false; 1200 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg); 1201 unsigned AliasReg = *Alias; ++Alias) 1202 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1203 HasAliasLive = true; 1204 break; 1205 } 1206 if (!HasAliasLive) { 1207 OmittedAnyCallClobbers = true; 1208 continue; 1209 } 1210 } 1211 } 1212 } 1213 1214 if (FirstOp) FirstOp = false; else OS << ","; 1215 OS << " "; 1216 if (i < getDesc().NumOperands) { 1217 const TargetOperandInfo &TOI = getDesc().OpInfo[i]; 1218 if (TOI.isPredicate()) 1219 OS << "pred:"; 1220 if (TOI.isOptionalDef()) 1221 OS << "opt:"; 1222 } 1223 if (isDebugValue() && MO.isMetadata()) { 1224 // Pretty print DBG_VALUE instructions. 1225 const MDNode *MD = MO.getMetadata(); 1226 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1227 OS << "!\"" << MDS->getString() << '\"'; 1228 else 1229 MO.print(OS, TM); 1230 } else 1231 MO.print(OS, TM); 1232 } 1233 1234 // Briefly indicate whether any call clobbers were omitted. 1235 if (OmittedAnyCallClobbers) { 1236 if (!FirstOp) OS << ","; 1237 OS << " ..."; 1238 } 1239 1240 bool HaveSemi = false; 1241 if (!memoperands_empty()) { 1242 if (!HaveSemi) OS << ";"; HaveSemi = true; 1243 1244 OS << " mem:"; 1245 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1246 i != e; ++i) { 1247 OS << **i; 1248 if (next(i) != e) 1249 OS << " "; 1250 } 1251 } 1252 1253 if (!debugLoc.isUnknown() && MF) { 1254 if (!HaveSemi) OS << ";"; 1255 1256 // TODO: print InlinedAtLoc information 1257 1258 DIScope Scope(debugLoc.getScope(MF->getFunction()->getContext())); 1259 OS << " dbg:"; 1260 // Omit the directory, since it's usually long and uninteresting. 1261 if (Scope.Verify()) 1262 OS << Scope.getFilename(); 1263 else 1264 OS << "<unknown>"; 1265 OS << ':' << debugLoc.getLine(); 1266 if (debugLoc.getCol() != 0) 1267 OS << ':' << debugLoc.getCol(); 1268 } 1269 1270 OS << "\n"; 1271} 1272 1273bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1274 const TargetRegisterInfo *RegInfo, 1275 bool AddIfNotFound) { 1276 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1277 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1278 bool Found = false; 1279 SmallVector<unsigned,4> DeadOps; 1280 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1281 MachineOperand &MO = getOperand(i); 1282 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1283 continue; 1284 unsigned Reg = MO.getReg(); 1285 if (!Reg) 1286 continue; 1287 1288 if (Reg == IncomingReg) { 1289 if (!Found) { 1290 if (MO.isKill()) 1291 // The register is already marked kill. 1292 return true; 1293 if (isPhysReg && isRegTiedToDefOperand(i)) 1294 // Two-address uses of physregs must not be marked kill. 1295 return true; 1296 MO.setIsKill(); 1297 Found = true; 1298 } 1299 } else if (hasAliases && MO.isKill() && 1300 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1301 // A super-register kill already exists. 1302 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1303 return true; 1304 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1305 DeadOps.push_back(i); 1306 } 1307 } 1308 1309 // Trim unneeded kill operands. 1310 while (!DeadOps.empty()) { 1311 unsigned OpIdx = DeadOps.back(); 1312 if (getOperand(OpIdx).isImplicit()) 1313 RemoveOperand(OpIdx); 1314 else 1315 getOperand(OpIdx).setIsKill(false); 1316 DeadOps.pop_back(); 1317 } 1318 1319 // If not found, this means an alias of one of the operands is killed. Add a 1320 // new implicit operand if required. 1321 if (!Found && AddIfNotFound) { 1322 addOperand(MachineOperand::CreateReg(IncomingReg, 1323 false /*IsDef*/, 1324 true /*IsImp*/, 1325 true /*IsKill*/)); 1326 return true; 1327 } 1328 return Found; 1329} 1330 1331bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1332 const TargetRegisterInfo *RegInfo, 1333 bool AddIfNotFound) { 1334 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1335 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1336 bool Found = false; 1337 SmallVector<unsigned,4> DeadOps; 1338 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1339 MachineOperand &MO = getOperand(i); 1340 if (!MO.isReg() || !MO.isDef()) 1341 continue; 1342 unsigned Reg = MO.getReg(); 1343 if (!Reg) 1344 continue; 1345 1346 if (Reg == IncomingReg) { 1347 if (!Found) { 1348 if (MO.isDead()) 1349 // The register is already marked dead. 1350 return true; 1351 MO.setIsDead(); 1352 Found = true; 1353 } 1354 } else if (hasAliases && MO.isDead() && 1355 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1356 // There exists a super-register that's marked dead. 1357 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1358 return true; 1359 if (RegInfo->getSubRegisters(IncomingReg) && 1360 RegInfo->getSuperRegisters(Reg) && 1361 RegInfo->isSubRegister(IncomingReg, Reg)) 1362 DeadOps.push_back(i); 1363 } 1364 } 1365 1366 // Trim unneeded dead operands. 1367 while (!DeadOps.empty()) { 1368 unsigned OpIdx = DeadOps.back(); 1369 if (getOperand(OpIdx).isImplicit()) 1370 RemoveOperand(OpIdx); 1371 else 1372 getOperand(OpIdx).setIsDead(false); 1373 DeadOps.pop_back(); 1374 } 1375 1376 // If not found, this means an alias of one of the operands is dead. Add a 1377 // new implicit operand if required. 1378 if (Found || !AddIfNotFound) 1379 return Found; 1380 1381 addOperand(MachineOperand::CreateReg(IncomingReg, 1382 true /*IsDef*/, 1383 true /*IsImp*/, 1384 false /*IsKill*/, 1385 true /*IsDead*/)); 1386 return true; 1387} 1388 1389void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1390 const TargetRegisterInfo *RegInfo) { 1391 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1392 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1393 if (MO) 1394 return; 1395 } else { 1396 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1397 const MachineOperand &MO = getOperand(i); 1398 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1399 MO.getSubReg() == 0) 1400 return; 1401 } 1402 } 1403 addOperand(MachineOperand::CreateReg(IncomingReg, 1404 true /*IsDef*/, 1405 true /*IsImp*/)); 1406} 1407 1408unsigned 1409MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 1410 unsigned Hash = MI->getOpcode() * 37; 1411 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1412 const MachineOperand &MO = MI->getOperand(i); 1413 uint64_t Key = (uint64_t)MO.getType() << 32; 1414 switch (MO.getType()) { 1415 default: break; 1416 case MachineOperand::MO_Register: 1417 if (MO.isDef() && MO.getReg() && 1418 TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1419 continue; // Skip virtual register defs. 1420 Key |= MO.getReg(); 1421 break; 1422 case MachineOperand::MO_Immediate: 1423 Key |= MO.getImm(); 1424 break; 1425 case MachineOperand::MO_FrameIndex: 1426 case MachineOperand::MO_ConstantPoolIndex: 1427 case MachineOperand::MO_JumpTableIndex: 1428 Key |= MO.getIndex(); 1429 break; 1430 case MachineOperand::MO_MachineBasicBlock: 1431 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB()); 1432 break; 1433 case MachineOperand::MO_GlobalAddress: 1434 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal()); 1435 break; 1436 case MachineOperand::MO_BlockAddress: 1437 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress()); 1438 break; 1439 case MachineOperand::MO_MCSymbol: 1440 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol()); 1441 break; 1442 } 1443 Key += ~(Key << 32); 1444 Key ^= (Key >> 22); 1445 Key += ~(Key << 13); 1446 Key ^= (Key >> 8); 1447 Key += (Key << 3); 1448 Key ^= (Key >> 15); 1449 Key += ~(Key << 27); 1450 Key ^= (Key >> 31); 1451 Hash = (unsigned)Key + Hash * 37; 1452 } 1453 return Hash; 1454} 1455