MachineInstr.cpp revision 2f1d8154795ad82e500fda27d75ec1449e7a0648 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/DebugInfo.h"
17#include "llvm/Function.h"
18#include "llvm/InlineAsm.h"
19#include "llvm/LLVMContext.h"
20#include "llvm/Metadata.h"
21#include "llvm/Module.h"
22#include "llvm/Type.h"
23#include "llvm/Value.h"
24#include "llvm/Assembly/Writer.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/PseudoSourceValue.h"
31#include "llvm/MC/MCInstrDesc.h"
32#include "llvm/MC/MCSymbol.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetRegisterInfo.h"
36#include "llvm/Analysis/AliasAnalysis.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/LeakDetector.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/ADT/FoldingSet.h"
43#include "llvm/ADT/Hashing.h"
44using namespace llvm;
45
46//===----------------------------------------------------------------------===//
47// MachineOperand Implementation
48//===----------------------------------------------------------------------===//
49
50void MachineOperand::setReg(unsigned Reg) {
51  if (getReg() == Reg) return; // No change.
52
53  // Otherwise, we have to change the register.  If this operand is embedded
54  // into a machine function, we need to update the old and new register's
55  // use/def lists.
56  if (MachineInstr *MI = getParent())
57    if (MachineBasicBlock *MBB = MI->getParent())
58      if (MachineFunction *MF = MBB->getParent()) {
59        MachineRegisterInfo &MRI = MF->getRegInfo();
60        MRI.removeRegOperandFromUseList(this);
61        SmallContents.RegNo = Reg;
62        MRI.addRegOperandToUseList(this);
63        return;
64      }
65
66  // Otherwise, just change the register, no problem.  :)
67  SmallContents.RegNo = Reg;
68}
69
70void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71                                  const TargetRegisterInfo &TRI) {
72  assert(TargetRegisterInfo::isVirtualRegister(Reg));
73  if (SubIdx && getSubReg())
74    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
75  setReg(Reg);
76  if (SubIdx)
77    setSubReg(SubIdx);
78}
79
80void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
82  if (getSubReg()) {
83    Reg = TRI.getSubReg(Reg, getSubReg());
84    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85    // That won't happen in legal code.
86    setSubReg(0);
87  }
88  setReg(Reg);
89}
90
91/// Change a def to a use, or a use to a def.
92void MachineOperand::setIsDef(bool Val) {
93  assert(isReg() && "Wrong MachineOperand accessor");
94  assert((!Val || !isDebug()) && "Marking a debug operation as def");
95  if (IsDef == Val)
96    return;
97  // MRI may keep uses and defs in different list positions.
98  if (MachineInstr *MI = getParent())
99    if (MachineBasicBlock *MBB = MI->getParent())
100      if (MachineFunction *MF = MBB->getParent()) {
101        MachineRegisterInfo &MRI = MF->getRegInfo();
102        MRI.removeRegOperandFromUseList(this);
103        IsDef = Val;
104        MRI.addRegOperandToUseList(this);
105        return;
106      }
107  IsDef = Val;
108}
109
110/// ChangeToImmediate - Replace this operand with a new immediate operand of
111/// the specified value.  If an operand is known to be an immediate already,
112/// the setImm method should be used.
113void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
115  // If this operand is currently a register operand, and if this is in a
116  // function, deregister the operand from the register's use/def list.
117  if (isReg() && isOnRegUseList())
118    if (MachineInstr *MI = getParent())
119      if (MachineBasicBlock *MBB = MI->getParent())
120        if (MachineFunction *MF = MBB->getParent())
121          MF->getRegInfo().removeRegOperandFromUseList(this);
122
123  OpKind = MO_Immediate;
124  Contents.ImmVal = ImmVal;
125}
126
127/// ChangeToRegister - Replace this operand with a new register operand of
128/// the specified value.  If an operand is known to be an register already,
129/// the setReg method should be used.
130void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
131                                      bool isKill, bool isDead, bool isUndef,
132                                      bool isDebug) {
133  MachineRegisterInfo *RegInfo = 0;
134  if (MachineInstr *MI = getParent())
135    if (MachineBasicBlock *MBB = MI->getParent())
136      if (MachineFunction *MF = MBB->getParent())
137        RegInfo = &MF->getRegInfo();
138  // If this operand is already a register operand, remove it from the
139  // register's use/def lists.
140  bool WasReg = isReg();
141  if (RegInfo && WasReg)
142    RegInfo->removeRegOperandFromUseList(this);
143
144  // Change this to a register and set the reg#.
145  OpKind = MO_Register;
146  SmallContents.RegNo = Reg;
147  SubReg = 0;
148  IsDef = isDef;
149  IsImp = isImp;
150  IsKill = isKill;
151  IsDead = isDead;
152  IsUndef = isUndef;
153  IsInternalRead = false;
154  IsEarlyClobber = false;
155  IsDebug = isDebug;
156  // Ensure isOnRegUseList() returns false.
157  Contents.Reg.Prev = 0;
158  // Preserve the tie when the operand was already a register.
159  if (!WasReg)
160    TiedTo = 0;
161
162  // If this operand is embedded in a function, add the operand to the
163  // register's use/def list.
164  if (RegInfo)
165    RegInfo->addRegOperandToUseList(this);
166}
167
168/// isIdenticalTo - Return true if this operand is identical to the specified
169/// operand. Note that this should stay in sync with the hash_value overload
170/// below.
171bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
172  if (getType() != Other.getType() ||
173      getTargetFlags() != Other.getTargetFlags())
174    return false;
175
176  switch (getType()) {
177  case MachineOperand::MO_Register:
178    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
179           getSubReg() == Other.getSubReg();
180  case MachineOperand::MO_Immediate:
181    return getImm() == Other.getImm();
182  case MachineOperand::MO_CImmediate:
183    return getCImm() == Other.getCImm();
184  case MachineOperand::MO_FPImmediate:
185    return getFPImm() == Other.getFPImm();
186  case MachineOperand::MO_MachineBasicBlock:
187    return getMBB() == Other.getMBB();
188  case MachineOperand::MO_FrameIndex:
189    return getIndex() == Other.getIndex();
190  case MachineOperand::MO_ConstantPoolIndex:
191  case MachineOperand::MO_TargetIndex:
192    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
193  case MachineOperand::MO_JumpTableIndex:
194    return getIndex() == Other.getIndex();
195  case MachineOperand::MO_GlobalAddress:
196    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
197  case MachineOperand::MO_ExternalSymbol:
198    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
199           getOffset() == Other.getOffset();
200  case MachineOperand::MO_BlockAddress:
201    return getBlockAddress() == Other.getBlockAddress();
202  case MO_RegisterMask:
203    return getRegMask() == Other.getRegMask();
204  case MachineOperand::MO_MCSymbol:
205    return getMCSymbol() == Other.getMCSymbol();
206  case MachineOperand::MO_Metadata:
207    return getMetadata() == Other.getMetadata();
208  }
209  llvm_unreachable("Invalid machine operand type");
210}
211
212// Note: this must stay exactly in sync with isIdenticalTo above.
213hash_code llvm::hash_value(const MachineOperand &MO) {
214  switch (MO.getType()) {
215  case MachineOperand::MO_Register:
216    // Register operands don't have target flags.
217    return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
218  case MachineOperand::MO_Immediate:
219    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
220  case MachineOperand::MO_CImmediate:
221    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
222  case MachineOperand::MO_FPImmediate:
223    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
224  case MachineOperand::MO_MachineBasicBlock:
225    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
226  case MachineOperand::MO_FrameIndex:
227    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
228  case MachineOperand::MO_ConstantPoolIndex:
229  case MachineOperand::MO_TargetIndex:
230    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
231                        MO.getOffset());
232  case MachineOperand::MO_JumpTableIndex:
233    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
234  case MachineOperand::MO_ExternalSymbol:
235    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
236                        MO.getSymbolName());
237  case MachineOperand::MO_GlobalAddress:
238    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
239                        MO.getOffset());
240  case MachineOperand::MO_BlockAddress:
241    return hash_combine(MO.getType(), MO.getTargetFlags(),
242                        MO.getBlockAddress());
243  case MachineOperand::MO_RegisterMask:
244    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
245  case MachineOperand::MO_Metadata:
246    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
247  case MachineOperand::MO_MCSymbol:
248    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
249  }
250  llvm_unreachable("Invalid machine operand type");
251}
252
253/// print - Print the specified machine operand.
254///
255void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
256  // If the instruction is embedded into a basic block, we can find the
257  // target info for the instruction.
258  if (!TM)
259    if (const MachineInstr *MI = getParent())
260      if (const MachineBasicBlock *MBB = MI->getParent())
261        if (const MachineFunction *MF = MBB->getParent())
262          TM = &MF->getTarget();
263  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
264
265  switch (getType()) {
266  case MachineOperand::MO_Register:
267    OS << PrintReg(getReg(), TRI, getSubReg());
268
269    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
270        isInternalRead() || isEarlyClobber() || isTied()) {
271      OS << '<';
272      bool NeedComma = false;
273      if (isDef()) {
274        if (NeedComma) OS << ',';
275        if (isEarlyClobber())
276          OS << "earlyclobber,";
277        if (isImplicit())
278          OS << "imp-";
279        OS << "def";
280        NeedComma = true;
281        // <def,read-undef> only makes sense when getSubReg() is set.
282        // Don't clutter the output otherwise.
283        if (isUndef() && getSubReg())
284          OS << ",read-undef";
285      } else if (isImplicit()) {
286          OS << "imp-use";
287          NeedComma = true;
288      }
289
290      if (isKill()) {
291        if (NeedComma) OS << ',';
292        OS << "kill";
293        NeedComma = true;
294      }
295      if (isDead()) {
296        if (NeedComma) OS << ',';
297        OS << "dead";
298        NeedComma = true;
299      }
300      if (isUndef() && isUse()) {
301        if (NeedComma) OS << ',';
302        OS << "undef";
303        NeedComma = true;
304      }
305      if (isInternalRead()) {
306        if (NeedComma) OS << ',';
307        OS << "internal";
308        NeedComma = true;
309      }
310      if (isTied()) {
311        if (NeedComma) OS << ',';
312        OS << "tied";
313        if (TiedTo != 15)
314          OS << unsigned(TiedTo - 1);
315        NeedComma = true;
316      }
317      OS << '>';
318    }
319    break;
320  case MachineOperand::MO_Immediate:
321    OS << getImm();
322    break;
323  case MachineOperand::MO_CImmediate:
324    getCImm()->getValue().print(OS, false);
325    break;
326  case MachineOperand::MO_FPImmediate:
327    if (getFPImm()->getType()->isFloatTy())
328      OS << getFPImm()->getValueAPF().convertToFloat();
329    else
330      OS << getFPImm()->getValueAPF().convertToDouble();
331    break;
332  case MachineOperand::MO_MachineBasicBlock:
333    OS << "<BB#" << getMBB()->getNumber() << ">";
334    break;
335  case MachineOperand::MO_FrameIndex:
336    OS << "<fi#" << getIndex() << '>';
337    break;
338  case MachineOperand::MO_ConstantPoolIndex:
339    OS << "<cp#" << getIndex();
340    if (getOffset()) OS << "+" << getOffset();
341    OS << '>';
342    break;
343  case MachineOperand::MO_TargetIndex:
344    OS << "<ti#" << getIndex();
345    if (getOffset()) OS << "+" << getOffset();
346    OS << '>';
347    break;
348  case MachineOperand::MO_JumpTableIndex:
349    OS << "<jt#" << getIndex() << '>';
350    break;
351  case MachineOperand::MO_GlobalAddress:
352    OS << "<ga:";
353    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
354    if (getOffset()) OS << "+" << getOffset();
355    OS << '>';
356    break;
357  case MachineOperand::MO_ExternalSymbol:
358    OS << "<es:" << getSymbolName();
359    if (getOffset()) OS << "+" << getOffset();
360    OS << '>';
361    break;
362  case MachineOperand::MO_BlockAddress:
363    OS << '<';
364    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
365    OS << '>';
366    break;
367  case MachineOperand::MO_RegisterMask:
368    OS << "<regmask>";
369    break;
370  case MachineOperand::MO_Metadata:
371    OS << '<';
372    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
373    OS << '>';
374    break;
375  case MachineOperand::MO_MCSymbol:
376    OS << "<MCSym=" << *getMCSymbol() << '>';
377    break;
378  }
379
380  if (unsigned TF = getTargetFlags())
381    OS << "[TF=" << TF << ']';
382}
383
384//===----------------------------------------------------------------------===//
385// MachineMemOperand Implementation
386//===----------------------------------------------------------------------===//
387
388/// getAddrSpace - Return the LLVM IR address space number that this pointer
389/// points into.
390unsigned MachinePointerInfo::getAddrSpace() const {
391  if (V == 0) return 0;
392  return cast<PointerType>(V->getType())->getAddressSpace();
393}
394
395/// getConstantPool - Return a MachinePointerInfo record that refers to the
396/// constant pool.
397MachinePointerInfo MachinePointerInfo::getConstantPool() {
398  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
399}
400
401/// getFixedStack - Return a MachinePointerInfo record that refers to the
402/// the specified FrameIndex.
403MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
404  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
405}
406
407MachinePointerInfo MachinePointerInfo::getJumpTable() {
408  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
409}
410
411MachinePointerInfo MachinePointerInfo::getGOT() {
412  return MachinePointerInfo(PseudoSourceValue::getGOT());
413}
414
415MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
416  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
417}
418
419MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
420                                     uint64_t s, unsigned int a,
421                                     const MDNode *TBAAInfo,
422                                     const MDNode *Ranges)
423  : PtrInfo(ptrinfo), Size(s),
424    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
425    TBAAInfo(TBAAInfo), Ranges(Ranges) {
426  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
427         "invalid pointer value");
428  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
429  assert((isLoad() || isStore()) && "Not a load/store!");
430}
431
432/// Profile - Gather unique data for the object.
433///
434void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
435  ID.AddInteger(getOffset());
436  ID.AddInteger(Size);
437  ID.AddPointer(getValue());
438  ID.AddInteger(Flags);
439}
440
441void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
442  // The Value and Offset may differ due to CSE. But the flags and size
443  // should be the same.
444  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
445  assert(MMO->getSize() == getSize() && "Size mismatch!");
446
447  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
448    // Update the alignment value.
449    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
450      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
451    // Also update the base and offset, because the new alignment may
452    // not be applicable with the old ones.
453    PtrInfo = MMO->PtrInfo;
454  }
455}
456
457/// getAlignment - Return the minimum known alignment in bytes of the
458/// actual memory reference.
459uint64_t MachineMemOperand::getAlignment() const {
460  return MinAlign(getBaseAlignment(), getOffset());
461}
462
463raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
464  assert((MMO.isLoad() || MMO.isStore()) &&
465         "SV has to be a load, store or both.");
466
467  if (MMO.isVolatile())
468    OS << "Volatile ";
469
470  if (MMO.isLoad())
471    OS << "LD";
472  if (MMO.isStore())
473    OS << "ST";
474  OS << MMO.getSize();
475
476  // Print the address information.
477  OS << "[";
478  if (!MMO.getValue())
479    OS << "<unknown>";
480  else
481    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
482
483  // If the alignment of the memory reference itself differs from the alignment
484  // of the base pointer, print the base alignment explicitly, next to the base
485  // pointer.
486  if (MMO.getBaseAlignment() != MMO.getAlignment())
487    OS << "(align=" << MMO.getBaseAlignment() << ")";
488
489  if (MMO.getOffset() != 0)
490    OS << "+" << MMO.getOffset();
491  OS << "]";
492
493  // Print the alignment of the reference.
494  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
495      MMO.getBaseAlignment() != MMO.getSize())
496    OS << "(align=" << MMO.getAlignment() << ")";
497
498  // Print TBAA info.
499  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
500    OS << "(tbaa=";
501    if (TBAAInfo->getNumOperands() > 0)
502      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
503    else
504      OS << "<unknown>";
505    OS << ")";
506  }
507
508  // Print nontemporal info.
509  if (MMO.isNonTemporal())
510    OS << "(nontemporal)";
511
512  return OS;
513}
514
515//===----------------------------------------------------------------------===//
516// MachineInstr Implementation
517//===----------------------------------------------------------------------===//
518
519/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
520/// MCID NULL and no operands.
521MachineInstr::MachineInstr()
522  : MCID(0), Flags(0), AsmPrinterFlags(0),
523    NumMemRefs(0), MemRefs(0),
524    Parent(0) {
525  // Make sure that we get added to a machine basicblock
526  LeakDetector::addGarbageObject(this);
527}
528
529void MachineInstr::addImplicitDefUseOperands() {
530  if (MCID->ImplicitDefs)
531    for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
532      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
533  if (MCID->ImplicitUses)
534    for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
535      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
536}
537
538/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
539/// implicit operands. It reserves space for the number of operands specified by
540/// the MCInstrDesc.
541MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
542  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
543    NumMemRefs(0), MemRefs(0), Parent(0) {
544  unsigned NumImplicitOps = 0;
545  if (!NoImp)
546    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
547  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
548  if (!NoImp)
549    addImplicitDefUseOperands();
550  // Make sure that we get added to a machine basicblock
551  LeakDetector::addGarbageObject(this);
552}
553
554/// MachineInstr ctor - As above, but with a DebugLoc.
555MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
556                           bool NoImp)
557  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
558    NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
559  unsigned NumImplicitOps = 0;
560  if (!NoImp)
561    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
562  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
563  if (!NoImp)
564    addImplicitDefUseOperands();
565  // Make sure that we get added to a machine basicblock
566  LeakDetector::addGarbageObject(this);
567}
568
569/// MachineInstr ctor - Work exactly the same as the ctor two above, except
570/// that the MachineInstr is created and added to the end of the specified
571/// basic block.
572MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
573  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
574    NumMemRefs(0), MemRefs(0), Parent(0) {
575  assert(MBB && "Cannot use inserting ctor with null basic block!");
576  unsigned NumImplicitOps =
577    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
578  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
579  addImplicitDefUseOperands();
580  // Make sure that we get added to a machine basicblock
581  LeakDetector::addGarbageObject(this);
582  MBB->push_back(this);  // Add instruction to end of basic block!
583}
584
585/// MachineInstr ctor - As above, but with a DebugLoc.
586///
587MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
588                           const MCInstrDesc &tid)
589  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
590    NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
591  assert(MBB && "Cannot use inserting ctor with null basic block!");
592  unsigned NumImplicitOps =
593    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
594  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
595  addImplicitDefUseOperands();
596  // Make sure that we get added to a machine basicblock
597  LeakDetector::addGarbageObject(this);
598  MBB->push_back(this);  // Add instruction to end of basic block!
599}
600
601/// MachineInstr ctor - Copies MachineInstr arg exactly
602///
603MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
604  : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
605    NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
606    Parent(0), debugLoc(MI.getDebugLoc()) {
607  Operands.reserve(MI.getNumOperands());
608
609  // Add operands
610  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
611    addOperand(MI.getOperand(i));
612
613  // Copy all the flags.
614  Flags = MI.Flags;
615
616  // Set parent to null.
617  Parent = 0;
618
619  LeakDetector::addGarbageObject(this);
620}
621
622MachineInstr::~MachineInstr() {
623  LeakDetector::removeGarbageObject(this);
624#ifndef NDEBUG
625  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
626    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
627    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
628           "Reg operand def/use list corrupted");
629  }
630#endif
631}
632
633/// getRegInfo - If this instruction is embedded into a MachineFunction,
634/// return the MachineRegisterInfo object for the current function, otherwise
635/// return null.
636MachineRegisterInfo *MachineInstr::getRegInfo() {
637  if (MachineBasicBlock *MBB = getParent())
638    return &MBB->getParent()->getRegInfo();
639  return 0;
640}
641
642/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
643/// this instruction from their respective use lists.  This requires that the
644/// operands already be on their use lists.
645void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
646  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
647    if (Operands[i].isReg())
648      MRI.removeRegOperandFromUseList(&Operands[i]);
649}
650
651/// AddRegOperandsToUseLists - Add all of the register operands in
652/// this instruction from their respective use lists.  This requires that the
653/// operands not be on their use lists yet.
654void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
655  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
656    if (Operands[i].isReg())
657      MRI.addRegOperandToUseList(&Operands[i]);
658}
659
660/// addOperand - Add the specified operand to the instruction.  If it is an
661/// implicit operand, it is added to the end of the operand list.  If it is
662/// an explicit operand it is added at the end of the explicit operand list
663/// (before the first implicit operand).
664void MachineInstr::addOperand(const MachineOperand &Op) {
665  assert(MCID && "Cannot add operands before providing an instr descriptor");
666  bool isImpReg = Op.isReg() && Op.isImplicit();
667  MachineRegisterInfo *RegInfo = getRegInfo();
668
669  // If the Operands backing store is reallocated, all register operands must
670  // be removed and re-added to RegInfo.  It is storing pointers to operands.
671  bool Reallocate = RegInfo &&
672    !Operands.empty() && Operands.size() == Operands.capacity();
673
674  // Find the insert location for the new operand.  Implicit registers go at
675  // the end, everything goes before the implicit regs.
676  unsigned OpNo = Operands.size();
677
678  // Remove all the implicit operands from RegInfo if they need to be shifted.
679  // FIXME: Allow mixed explicit and implicit operands on inline asm.
680  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
681  // implicit-defs, but they must not be moved around.  See the FIXME in
682  // InstrEmitter.cpp.
683  if (!isImpReg && !isInlineAsm()) {
684    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
685      --OpNo;
686      assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
687      if (RegInfo)
688        RegInfo->removeRegOperandFromUseList(&Operands[OpNo]);
689    }
690  }
691
692  // OpNo now points as the desired insertion point.  Unless this is a variadic
693  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
694  // RegMask operands go between the explicit and implicit operands.
695  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
696          OpNo < MCID->getNumOperands()) &&
697         "Trying to add an operand to a machine instr that is already done!");
698
699  // All operands from OpNo have been removed from RegInfo.  If the Operands
700  // backing store needs to be reallocated, we also need to remove any other
701  // register operands.
702  if (Reallocate)
703    for (unsigned i = 0; i != OpNo; ++i)
704      if (Operands[i].isReg())
705        RegInfo->removeRegOperandFromUseList(&Operands[i]);
706
707  // Insert the new operand at OpNo.
708  Operands.insert(Operands.begin() + OpNo, Op);
709  Operands[OpNo].ParentMI = this;
710
711  // The Operands backing store has now been reallocated, so we can re-add the
712  // operands before OpNo.
713  if (Reallocate)
714    for (unsigned i = 0; i != OpNo; ++i)
715      if (Operands[i].isReg())
716        RegInfo->addRegOperandToUseList(&Operands[i]);
717
718  // When adding a register operand, tell RegInfo about it.
719  if (Operands[OpNo].isReg()) {
720    // Ensure isOnRegUseList() returns false, regardless of Op's status.
721    Operands[OpNo].Contents.Reg.Prev = 0;
722    // Ignore existing ties. This is not a property that can be copied.
723    Operands[OpNo].TiedTo = 0;
724    // Add the new operand to RegInfo.
725    if (RegInfo)
726      RegInfo->addRegOperandToUseList(&Operands[OpNo]);
727    // The MCID operand information isn't accurate until we start adding
728    // explicit operands. The implicit operands are added first, then the
729    // explicits are inserted before them.
730    if (!isImpReg) {
731      // Tie uses to defs as indicated in MCInstrDesc.
732      if (Operands[OpNo].isUse()) {
733        int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
734        if (DefIdx != -1)
735          tieOperands(DefIdx, OpNo);
736      }
737      // If the register operand is flagged as early, mark the operand as such.
738      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
739        Operands[OpNo].setIsEarlyClobber(true);
740    }
741  }
742
743  // Re-add all the implicit ops.
744  if (RegInfo) {
745    for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
746      assert(Operands[i].isReg() && "Should only be an implicit reg!");
747      RegInfo->addRegOperandToUseList(&Operands[i]);
748    }
749  }
750}
751
752/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
753/// fewer operand than it started with.
754///
755void MachineInstr::RemoveOperand(unsigned OpNo) {
756  assert(OpNo < Operands.size() && "Invalid operand number");
757  untieRegOperand(OpNo);
758  MachineRegisterInfo *RegInfo = getRegInfo();
759
760  // Special case removing the last one.
761  if (OpNo == Operands.size()-1) {
762    // If needed, remove from the reg def/use list.
763    if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList())
764      RegInfo->removeRegOperandFromUseList(&Operands.back());
765
766    Operands.pop_back();
767    return;
768  }
769
770  // Otherwise, we are removing an interior operand.  If we have reginfo to
771  // update, remove all operands that will be shifted down from their reg lists,
772  // move everything down, then re-add them.
773  if (RegInfo) {
774    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
775      if (Operands[i].isReg())
776        RegInfo->removeRegOperandFromUseList(&Operands[i]);
777    }
778  }
779
780#ifndef NDEBUG
781  // Moving tied operands would break the ties.
782  for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i)
783    if (Operands[i].isReg())
784      assert(!Operands[i].isTied() && "Cannot move tied operands");
785#endif
786
787  Operands.erase(Operands.begin()+OpNo);
788
789  if (RegInfo) {
790    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
791      if (Operands[i].isReg())
792        RegInfo->addRegOperandToUseList(&Operands[i]);
793    }
794  }
795}
796
797/// addMemOperand - Add a MachineMemOperand to the machine instruction.
798/// This function should be used only occasionally. The setMemRefs function
799/// is the primary method for setting up a MachineInstr's MemRefs list.
800void MachineInstr::addMemOperand(MachineFunction &MF,
801                                 MachineMemOperand *MO) {
802  mmo_iterator OldMemRefs = MemRefs;
803  uint16_t OldNumMemRefs = NumMemRefs;
804
805  uint16_t NewNum = NumMemRefs + 1;
806  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
807
808  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
809  NewMemRefs[NewNum - 1] = MO;
810
811  MemRefs = NewMemRefs;
812  NumMemRefs = NewNum;
813}
814
815bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
816  const MachineBasicBlock *MBB = getParent();
817  MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
818  while (MII != MBB->end() && MII->isInsideBundle()) {
819    if (MII->getDesc().getFlags() & Mask) {
820      if (Type == AnyInBundle)
821        return true;
822    } else {
823      if (Type == AllInBundle)
824        return false;
825    }
826    ++MII;
827  }
828
829  return Type == AllInBundle;
830}
831
832bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
833                                 MICheckType Check) const {
834  // If opcodes or number of operands are not the same then the two
835  // instructions are obviously not identical.
836  if (Other->getOpcode() != getOpcode() ||
837      Other->getNumOperands() != getNumOperands())
838    return false;
839
840  if (isBundle()) {
841    // Both instructions are bundles, compare MIs inside the bundle.
842    MachineBasicBlock::const_instr_iterator I1 = *this;
843    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
844    MachineBasicBlock::const_instr_iterator I2 = *Other;
845    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
846    while (++I1 != E1 && I1->isInsideBundle()) {
847      ++I2;
848      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
849        return false;
850    }
851  }
852
853  // Check operands to make sure they match.
854  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
855    const MachineOperand &MO = getOperand(i);
856    const MachineOperand &OMO = Other->getOperand(i);
857    if (!MO.isReg()) {
858      if (!MO.isIdenticalTo(OMO))
859        return false;
860      continue;
861    }
862
863    // Clients may or may not want to ignore defs when testing for equality.
864    // For example, machine CSE pass only cares about finding common
865    // subexpressions, so it's safe to ignore virtual register defs.
866    if (MO.isDef()) {
867      if (Check == IgnoreDefs)
868        continue;
869      else if (Check == IgnoreVRegDefs) {
870        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
871            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
872          if (MO.getReg() != OMO.getReg())
873            return false;
874      } else {
875        if (!MO.isIdenticalTo(OMO))
876          return false;
877        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
878          return false;
879      }
880    } else {
881      if (!MO.isIdenticalTo(OMO))
882        return false;
883      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
884        return false;
885    }
886  }
887  // If DebugLoc does not match then two dbg.values are not identical.
888  if (isDebugValue())
889    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
890        && getDebugLoc() != Other->getDebugLoc())
891      return false;
892  return true;
893}
894
895/// removeFromParent - This method unlinks 'this' from the containing basic
896/// block, and returns it, but does not delete it.
897MachineInstr *MachineInstr::removeFromParent() {
898  assert(getParent() && "Not embedded in a basic block!");
899
900  // If it's a bundle then remove the MIs inside the bundle as well.
901  if (isBundle()) {
902    MachineBasicBlock *MBB = getParent();
903    MachineBasicBlock::instr_iterator MII = *this; ++MII;
904    MachineBasicBlock::instr_iterator E = MBB->instr_end();
905    while (MII != E && MII->isInsideBundle()) {
906      MachineInstr *MI = &*MII;
907      ++MII;
908      MBB->remove(MI);
909    }
910  }
911  getParent()->remove(this);
912  return this;
913}
914
915
916/// eraseFromParent - This method unlinks 'this' from the containing basic
917/// block, and deletes it.
918void MachineInstr::eraseFromParent() {
919  assert(getParent() && "Not embedded in a basic block!");
920  // If it's a bundle then remove the MIs inside the bundle as well.
921  if (isBundle()) {
922    MachineBasicBlock *MBB = getParent();
923    MachineBasicBlock::instr_iterator MII = *this; ++MII;
924    MachineBasicBlock::instr_iterator E = MBB->instr_end();
925    while (MII != E && MII->isInsideBundle()) {
926      MachineInstr *MI = &*MII;
927      ++MII;
928      MBB->erase(MI);
929    }
930  }
931  // Erase the individual instruction, which may itself be inside a bundle.
932  getParent()->erase_instr(this);
933}
934
935
936/// getNumExplicitOperands - Returns the number of non-implicit operands.
937///
938unsigned MachineInstr::getNumExplicitOperands() const {
939  unsigned NumOperands = MCID->getNumOperands();
940  if (!MCID->isVariadic())
941    return NumOperands;
942
943  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
944    const MachineOperand &MO = getOperand(i);
945    if (!MO.isReg() || !MO.isImplicit())
946      NumOperands++;
947  }
948  return NumOperands;
949}
950
951/// isBundled - Return true if this instruction part of a bundle. This is true
952/// if either itself or its following instruction is marked "InsideBundle".
953bool MachineInstr::isBundled() const {
954  if (isInsideBundle())
955    return true;
956  MachineBasicBlock::const_instr_iterator nextMI = this;
957  ++nextMI;
958  return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
959}
960
961bool MachineInstr::isStackAligningInlineAsm() const {
962  if (isInlineAsm()) {
963    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
964    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
965      return true;
966  }
967  return false;
968}
969
970InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
971  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
972  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
973  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
974}
975
976int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
977                                       unsigned *GroupNo) const {
978  assert(isInlineAsm() && "Expected an inline asm instruction");
979  assert(OpIdx < getNumOperands() && "OpIdx out of range");
980
981  // Ignore queries about the initial operands.
982  if (OpIdx < InlineAsm::MIOp_FirstOperand)
983    return -1;
984
985  unsigned Group = 0;
986  unsigned NumOps;
987  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
988       i += NumOps) {
989    const MachineOperand &FlagMO = getOperand(i);
990    // If we reach the implicit register operands, stop looking.
991    if (!FlagMO.isImm())
992      return -1;
993    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
994    if (i + NumOps > OpIdx) {
995      if (GroupNo)
996        *GroupNo = Group;
997      return i;
998    }
999    ++Group;
1000  }
1001  return -1;
1002}
1003
1004const TargetRegisterClass*
1005MachineInstr::getRegClassConstraint(unsigned OpIdx,
1006                                    const TargetInstrInfo *TII,
1007                                    const TargetRegisterInfo *TRI) const {
1008  assert(getParent() && "Can't have an MBB reference here!");
1009  assert(getParent()->getParent() && "Can't have an MF reference here!");
1010  const MachineFunction &MF = *getParent()->getParent();
1011
1012  // Most opcodes have fixed constraints in their MCInstrDesc.
1013  if (!isInlineAsm())
1014    return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1015
1016  if (!getOperand(OpIdx).isReg())
1017    return NULL;
1018
1019  // For tied uses on inline asm, get the constraint from the def.
1020  unsigned DefIdx;
1021  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1022    OpIdx = DefIdx;
1023
1024  // Inline asm stores register class constraints in the flag word.
1025  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1026  if (FlagIdx < 0)
1027    return NULL;
1028
1029  unsigned Flag = getOperand(FlagIdx).getImm();
1030  unsigned RCID;
1031  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1032    return TRI->getRegClass(RCID);
1033
1034  // Assume that all registers in a memory operand are pointers.
1035  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1036    return TRI->getPointerRegClass(MF);
1037
1038  return NULL;
1039}
1040
1041/// getBundleSize - Return the number of instructions inside the MI bundle.
1042unsigned MachineInstr::getBundleSize() const {
1043  assert(isBundle() && "Expecting a bundle");
1044
1045  MachineBasicBlock::const_instr_iterator I = *this;
1046  unsigned Size = 0;
1047  while ((++I)->isInsideBundle()) {
1048    ++Size;
1049  }
1050  assert(Size > 1 && "Malformed bundle");
1051
1052  return Size;
1053}
1054
1055/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1056/// the specific register or -1 if it is not found. It further tightens
1057/// the search criteria to a use that kills the register if isKill is true.
1058int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1059                                          const TargetRegisterInfo *TRI) const {
1060  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1061    const MachineOperand &MO = getOperand(i);
1062    if (!MO.isReg() || !MO.isUse())
1063      continue;
1064    unsigned MOReg = MO.getReg();
1065    if (!MOReg)
1066      continue;
1067    if (MOReg == Reg ||
1068        (TRI &&
1069         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1070         TargetRegisterInfo::isPhysicalRegister(Reg) &&
1071         TRI->isSubRegister(MOReg, Reg)))
1072      if (!isKill || MO.isKill())
1073        return i;
1074  }
1075  return -1;
1076}
1077
1078/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1079/// indicating if this instruction reads or writes Reg. This also considers
1080/// partial defines.
1081std::pair<bool,bool>
1082MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1083                                         SmallVectorImpl<unsigned> *Ops) const {
1084  bool PartDef = false; // Partial redefine.
1085  bool FullDef = false; // Full define.
1086  bool Use = false;
1087
1088  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1089    const MachineOperand &MO = getOperand(i);
1090    if (!MO.isReg() || MO.getReg() != Reg)
1091      continue;
1092    if (Ops)
1093      Ops->push_back(i);
1094    if (MO.isUse())
1095      Use |= !MO.isUndef();
1096    else if (MO.getSubReg() && !MO.isUndef())
1097      // A partial <def,undef> doesn't count as reading the register.
1098      PartDef = true;
1099    else
1100      FullDef = true;
1101  }
1102  // A partial redefine uses Reg unless there is also a full define.
1103  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1104}
1105
1106/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1107/// the specified register or -1 if it is not found. If isDead is true, defs
1108/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1109/// also checks if there is a def of a super-register.
1110int
1111MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1112                                        const TargetRegisterInfo *TRI) const {
1113  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1114  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1115    const MachineOperand &MO = getOperand(i);
1116    // Accept regmask operands when Overlap is set.
1117    // Ignore them when looking for a specific def operand (Overlap == false).
1118    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1119      return i;
1120    if (!MO.isReg() || !MO.isDef())
1121      continue;
1122    unsigned MOReg = MO.getReg();
1123    bool Found = (MOReg == Reg);
1124    if (!Found && TRI && isPhys &&
1125        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1126      if (Overlap)
1127        Found = TRI->regsOverlap(MOReg, Reg);
1128      else
1129        Found = TRI->isSubRegister(MOReg, Reg);
1130    }
1131    if (Found && (!isDead || MO.isDead()))
1132      return i;
1133  }
1134  return -1;
1135}
1136
1137/// findFirstPredOperandIdx() - Find the index of the first operand in the
1138/// operand list that is used to represent the predicate. It returns -1 if
1139/// none is found.
1140int MachineInstr::findFirstPredOperandIdx() const {
1141  // Don't call MCID.findFirstPredOperandIdx() because this variant
1142  // is sometimes called on an instruction that's not yet complete, and
1143  // so the number of operands is less than the MCID indicates. In
1144  // particular, the PTX target does this.
1145  const MCInstrDesc &MCID = getDesc();
1146  if (MCID.isPredicable()) {
1147    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1148      if (MCID.OpInfo[i].isPredicate())
1149        return i;
1150  }
1151
1152  return -1;
1153}
1154
1155// MachineOperand::TiedTo is 4 bits wide.
1156const unsigned TiedMax = 15;
1157
1158/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1159///
1160/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1161/// field. TiedTo can have these values:
1162///
1163/// 0:              Operand is not tied to anything.
1164/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1165/// TiedMax:        Tied to an operand >= TiedMax-1.
1166///
1167/// The tied def must be one of the first TiedMax operands on a normal
1168/// instruction. INLINEASM instructions allow more tied defs.
1169///
1170void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1171  MachineOperand &DefMO = getOperand(DefIdx);
1172  MachineOperand &UseMO = getOperand(UseIdx);
1173  assert(DefMO.isDef() && "DefIdx must be a def operand");
1174  assert(UseMO.isUse() && "UseIdx must be a use operand");
1175  assert(!DefMO.isTied() && "Def is already tied to another use");
1176  assert(!UseMO.isTied() && "Use is already tied to another def");
1177
1178  if (DefIdx < TiedMax)
1179    UseMO.TiedTo = DefIdx + 1;
1180  else {
1181    // Inline asm can use the group descriptors to find tied operands, but on
1182    // normal instruction, the tied def must be within the first TiedMax
1183    // operands.
1184    assert(isInlineAsm() && "DefIdx out of range");
1185    UseMO.TiedTo = TiedMax;
1186  }
1187
1188  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1189  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1190}
1191
1192/// Given the index of a tied register operand, find the operand it is tied to.
1193/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1194/// which must exist.
1195unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1196  const MachineOperand &MO = getOperand(OpIdx);
1197  assert(MO.isTied() && "Operand isn't tied");
1198
1199  // Normally TiedTo is in range.
1200  if (MO.TiedTo < TiedMax)
1201    return MO.TiedTo - 1;
1202
1203  // Uses on normal instructions can be out of range.
1204  if (!isInlineAsm()) {
1205    // Normal tied defs must be in the 0..TiedMax-1 range.
1206    if (MO.isUse())
1207      return TiedMax - 1;
1208    // MO is a def. Search for the tied use.
1209    for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1210      const MachineOperand &UseMO = getOperand(i);
1211      if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1212        return i;
1213    }
1214    llvm_unreachable("Can't find tied use");
1215  }
1216
1217  // Now deal with inline asm by parsing the operand group descriptor flags.
1218  // Find the beginning of each operand group.
1219  SmallVector<unsigned, 8> GroupIdx;
1220  unsigned OpIdxGroup = ~0u;
1221  unsigned NumOps;
1222  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1223       i += NumOps) {
1224    const MachineOperand &FlagMO = getOperand(i);
1225    assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1226    unsigned CurGroup = GroupIdx.size();
1227    GroupIdx.push_back(i);
1228    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1229    // OpIdx belongs to this operand group.
1230    if (OpIdx > i && OpIdx < i + NumOps)
1231      OpIdxGroup = CurGroup;
1232    unsigned TiedGroup;
1233    if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1234      continue;
1235    // Operands in this group are tied to operands in TiedGroup which must be
1236    // earlier. Find the number of operands between the two groups.
1237    unsigned Delta = i - GroupIdx[TiedGroup];
1238
1239    // OpIdx is a use tied to TiedGroup.
1240    if (OpIdxGroup == CurGroup)
1241      return OpIdx - Delta;
1242
1243    // OpIdx is a def tied to this use group.
1244    if (OpIdxGroup == TiedGroup)
1245      return OpIdx + Delta;
1246  }
1247  llvm_unreachable("Invalid tied operand on inline asm");
1248}
1249
1250/// clearKillInfo - Clears kill flags on all operands.
1251///
1252void MachineInstr::clearKillInfo() {
1253  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1254    MachineOperand &MO = getOperand(i);
1255    if (MO.isReg() && MO.isUse())
1256      MO.setIsKill(false);
1257  }
1258}
1259
1260/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1261///
1262void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1263  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1264    const MachineOperand &MO = MI->getOperand(i);
1265    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1266      continue;
1267    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1268      MachineOperand &MOp = getOperand(j);
1269      if (!MOp.isIdenticalTo(MO))
1270        continue;
1271      if (MO.isKill())
1272        MOp.setIsKill();
1273      else
1274        MOp.setIsDead();
1275      break;
1276    }
1277  }
1278}
1279
1280/// copyPredicates - Copies predicate operand(s) from MI.
1281void MachineInstr::copyPredicates(const MachineInstr *MI) {
1282  assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1283
1284  const MCInstrDesc &MCID = MI->getDesc();
1285  if (!MCID.isPredicable())
1286    return;
1287  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1288    if (MCID.OpInfo[i].isPredicate()) {
1289      // Predicated operands must be last operands.
1290      addOperand(MI->getOperand(i));
1291    }
1292  }
1293}
1294
1295void MachineInstr::substituteRegister(unsigned FromReg,
1296                                      unsigned ToReg,
1297                                      unsigned SubIdx,
1298                                      const TargetRegisterInfo &RegInfo) {
1299  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1300    if (SubIdx)
1301      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1302    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1303      MachineOperand &MO = getOperand(i);
1304      if (!MO.isReg() || MO.getReg() != FromReg)
1305        continue;
1306      MO.substPhysReg(ToReg, RegInfo);
1307    }
1308  } else {
1309    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1310      MachineOperand &MO = getOperand(i);
1311      if (!MO.isReg() || MO.getReg() != FromReg)
1312        continue;
1313      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1314    }
1315  }
1316}
1317
1318/// isSafeToMove - Return true if it is safe to move this instruction. If
1319/// SawStore is set to true, it means that there is a store (or call) between
1320/// the instruction's location and its intended destination.
1321bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1322                                AliasAnalysis *AA,
1323                                bool &SawStore) const {
1324  // Ignore stuff that we obviously can't move.
1325  //
1326  // Treat volatile loads as stores. This is not strictly necessary for
1327  // volatiles, but it is required for atomic loads. It is not allowed to move
1328  // a load across an atomic load with Ordering > Monotonic.
1329  if (mayStore() || isCall() ||
1330      (mayLoad() && hasOrderedMemoryRef())) {
1331    SawStore = true;
1332    return false;
1333  }
1334
1335  if (isLabel() || isDebugValue() ||
1336      isTerminator() || hasUnmodeledSideEffects())
1337    return false;
1338
1339  // See if this instruction does a load.  If so, we have to guarantee that the
1340  // loaded value doesn't change between the load and the its intended
1341  // destination. The check for isInvariantLoad gives the targe the chance to
1342  // classify the load as always returning a constant, e.g. a constant pool
1343  // load.
1344  if (mayLoad() && !isInvariantLoad(AA))
1345    // Otherwise, this is a real load.  If there is a store between the load and
1346    // end of block, we can't move it.
1347    return !SawStore;
1348
1349  return true;
1350}
1351
1352/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1353/// instruction which defined the specified register instead of copying it.
1354bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1355                                 AliasAnalysis *AA,
1356                                 unsigned DstReg) const {
1357  bool SawStore = false;
1358  if (!TII->isTriviallyReMaterializable(this, AA) ||
1359      !isSafeToMove(TII, AA, SawStore))
1360    return false;
1361  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1362    const MachineOperand &MO = getOperand(i);
1363    if (!MO.isReg())
1364      continue;
1365    // FIXME: For now, do not remat any instruction with register operands.
1366    // Later on, we can loosen the restriction is the register operands have
1367    // not been modified between the def and use. Note, this is different from
1368    // MachineSink because the code is no longer in two-address form (at least
1369    // partially).
1370    if (MO.isUse())
1371      return false;
1372    else if (!MO.isDead() && MO.getReg() != DstReg)
1373      return false;
1374  }
1375  return true;
1376}
1377
1378/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1379/// or volatile memory reference, or if the information describing the memory
1380/// reference is not available. Return false if it is known to have no ordered
1381/// memory references.
1382bool MachineInstr::hasOrderedMemoryRef() const {
1383  // An instruction known never to access memory won't have a volatile access.
1384  if (!mayStore() &&
1385      !mayLoad() &&
1386      !isCall() &&
1387      !hasUnmodeledSideEffects())
1388    return false;
1389
1390  // Otherwise, if the instruction has no memory reference information,
1391  // conservatively assume it wasn't preserved.
1392  if (memoperands_empty())
1393    return true;
1394
1395  // Check the memory reference information for ordered references.
1396  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1397    if (!(*I)->isUnordered())
1398      return true;
1399
1400  return false;
1401}
1402
1403/// isInvariantLoad - Return true if this instruction is loading from a
1404/// location whose value is invariant across the function.  For example,
1405/// loading a value from the constant pool or from the argument area
1406/// of a function if it does not change.  This should only return true of
1407/// *all* loads the instruction does are invariant (if it does multiple loads).
1408bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1409  // If the instruction doesn't load at all, it isn't an invariant load.
1410  if (!mayLoad())
1411    return false;
1412
1413  // If the instruction has lost its memoperands, conservatively assume that
1414  // it may not be an invariant load.
1415  if (memoperands_empty())
1416    return false;
1417
1418  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1419
1420  for (mmo_iterator I = memoperands_begin(),
1421       E = memoperands_end(); I != E; ++I) {
1422    if ((*I)->isVolatile()) return false;
1423    if ((*I)->isStore()) return false;
1424    if ((*I)->isInvariant()) return true;
1425
1426    if (const Value *V = (*I)->getValue()) {
1427      // A load from a constant PseudoSourceValue is invariant.
1428      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1429        if (PSV->isConstant(MFI))
1430          continue;
1431      // If we have an AliasAnalysis, ask it whether the memory is constant.
1432      if (AA && AA->pointsToConstantMemory(
1433                      AliasAnalysis::Location(V, (*I)->getSize(),
1434                                              (*I)->getTBAAInfo())))
1435        continue;
1436    }
1437
1438    // Otherwise assume conservatively.
1439    return false;
1440  }
1441
1442  // Everything checks out.
1443  return true;
1444}
1445
1446/// isConstantValuePHI - If the specified instruction is a PHI that always
1447/// merges together the same virtual register, return the register, otherwise
1448/// return 0.
1449unsigned MachineInstr::isConstantValuePHI() const {
1450  if (!isPHI())
1451    return 0;
1452  assert(getNumOperands() >= 3 &&
1453         "It's illegal to have a PHI without source operands");
1454
1455  unsigned Reg = getOperand(1).getReg();
1456  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1457    if (getOperand(i).getReg() != Reg)
1458      return 0;
1459  return Reg;
1460}
1461
1462bool MachineInstr::hasUnmodeledSideEffects() const {
1463  if (hasProperty(MCID::UnmodeledSideEffects))
1464    return true;
1465  if (isInlineAsm()) {
1466    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1467    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1468      return true;
1469  }
1470
1471  return false;
1472}
1473
1474/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1475///
1476bool MachineInstr::allDefsAreDead() const {
1477  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1478    const MachineOperand &MO = getOperand(i);
1479    if (!MO.isReg() || MO.isUse())
1480      continue;
1481    if (!MO.isDead())
1482      return false;
1483  }
1484  return true;
1485}
1486
1487/// copyImplicitOps - Copy implicit register operands from specified
1488/// instruction to this instruction.
1489void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1490  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1491       i != e; ++i) {
1492    const MachineOperand &MO = MI->getOperand(i);
1493    if (MO.isReg() && MO.isImplicit())
1494      addOperand(MO);
1495  }
1496}
1497
1498void MachineInstr::dump() const {
1499  dbgs() << "  " << *this;
1500}
1501
1502static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1503                         raw_ostream &CommentOS) {
1504  const LLVMContext &Ctx = MF->getFunction()->getContext();
1505  if (!DL.isUnknown()) {          // Print source line info.
1506    DIScope Scope(DL.getScope(Ctx));
1507    // Omit the directory, because it's likely to be long and uninteresting.
1508    if (Scope.Verify())
1509      CommentOS << Scope.getFilename();
1510    else
1511      CommentOS << "<unknown>";
1512    CommentOS << ':' << DL.getLine();
1513    if (DL.getCol() != 0)
1514      CommentOS << ':' << DL.getCol();
1515    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1516    if (!InlinedAtDL.isUnknown()) {
1517      CommentOS << " @[ ";
1518      printDebugLoc(InlinedAtDL, MF, CommentOS);
1519      CommentOS << " ]";
1520    }
1521  }
1522}
1523
1524void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1525  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1526  const MachineFunction *MF = 0;
1527  const MachineRegisterInfo *MRI = 0;
1528  if (const MachineBasicBlock *MBB = getParent()) {
1529    MF = MBB->getParent();
1530    if (!TM && MF)
1531      TM = &MF->getTarget();
1532    if (MF)
1533      MRI = &MF->getRegInfo();
1534  }
1535
1536  // Save a list of virtual registers.
1537  SmallVector<unsigned, 8> VirtRegs;
1538
1539  // Print explicitly defined operands on the left of an assignment syntax.
1540  unsigned StartOp = 0, e = getNumOperands();
1541  for (; StartOp < e && getOperand(StartOp).isReg() &&
1542         getOperand(StartOp).isDef() &&
1543         !getOperand(StartOp).isImplicit();
1544       ++StartOp) {
1545    if (StartOp != 0) OS << ", ";
1546    getOperand(StartOp).print(OS, TM);
1547    unsigned Reg = getOperand(StartOp).getReg();
1548    if (TargetRegisterInfo::isVirtualRegister(Reg))
1549      VirtRegs.push_back(Reg);
1550  }
1551
1552  if (StartOp != 0)
1553    OS << " = ";
1554
1555  // Print the opcode name.
1556  if (TM && TM->getInstrInfo())
1557    OS << TM->getInstrInfo()->getName(getOpcode());
1558  else
1559    OS << "UNKNOWN";
1560
1561  // Print the rest of the operands.
1562  bool OmittedAnyCallClobbers = false;
1563  bool FirstOp = true;
1564  unsigned AsmDescOp = ~0u;
1565  unsigned AsmOpCount = 0;
1566
1567  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1568    // Print asm string.
1569    OS << " ";
1570    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1571
1572    // Print HasSideEffects, IsAlignStack
1573    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1574    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1575      OS << " [sideeffect]";
1576    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1577      OS << " [alignstack]";
1578    if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1579      OS << " [attdialect]";
1580    if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1581      OS << " [inteldialect]";
1582
1583    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1584    FirstOp = false;
1585  }
1586
1587
1588  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1589    const MachineOperand &MO = getOperand(i);
1590
1591    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1592      VirtRegs.push_back(MO.getReg());
1593
1594    // Omit call-clobbered registers which aren't used anywhere. This makes
1595    // call instructions much less noisy on targets where calls clobber lots
1596    // of registers. Don't rely on MO.isDead() because we may be called before
1597    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1598    if (MF && isCall() &&
1599        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1600      unsigned Reg = MO.getReg();
1601      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1602        const MachineRegisterInfo &MRI = MF->getRegInfo();
1603        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1604          bool HasAliasLive = false;
1605          for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1606               AI.isValid(); ++AI) {
1607            unsigned AliasReg = *AI;
1608            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1609              HasAliasLive = true;
1610              break;
1611            }
1612          }
1613          if (!HasAliasLive) {
1614            OmittedAnyCallClobbers = true;
1615            continue;
1616          }
1617        }
1618      }
1619    }
1620
1621    if (FirstOp) FirstOp = false; else OS << ",";
1622    OS << " ";
1623    if (i < getDesc().NumOperands) {
1624      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1625      if (MCOI.isPredicate())
1626        OS << "pred:";
1627      if (MCOI.isOptionalDef())
1628        OS << "opt:";
1629    }
1630    if (isDebugValue() && MO.isMetadata()) {
1631      // Pretty print DBG_VALUE instructions.
1632      const MDNode *MD = MO.getMetadata();
1633      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1634        OS << "!\"" << MDS->getString() << '\"';
1635      else
1636        MO.print(OS, TM);
1637    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1638      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1639    } else if (i == AsmDescOp && MO.isImm()) {
1640      // Pretty print the inline asm operand descriptor.
1641      OS << '$' << AsmOpCount++;
1642      unsigned Flag = MO.getImm();
1643      switch (InlineAsm::getKind(Flag)) {
1644      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1645      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1646      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1647      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1648      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1649      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1650      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1651      }
1652
1653      unsigned RCID = 0;
1654      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1655        if (TM)
1656          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1657        else
1658          OS << ":RC" << RCID;
1659      }
1660
1661      unsigned TiedTo = 0;
1662      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1663        OS << " tiedto:$" << TiedTo;
1664
1665      OS << ']';
1666
1667      // Compute the index of the next operand descriptor.
1668      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1669    } else
1670      MO.print(OS, TM);
1671  }
1672
1673  // Briefly indicate whether any call clobbers were omitted.
1674  if (OmittedAnyCallClobbers) {
1675    if (!FirstOp) OS << ",";
1676    OS << " ...";
1677  }
1678
1679  bool HaveSemi = false;
1680  if (Flags) {
1681    if (!HaveSemi) OS << ";"; HaveSemi = true;
1682    OS << " flags: ";
1683
1684    if (Flags & FrameSetup)
1685      OS << "FrameSetup";
1686  }
1687
1688  if (!memoperands_empty()) {
1689    if (!HaveSemi) OS << ";"; HaveSemi = true;
1690
1691    OS << " mem:";
1692    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1693         i != e; ++i) {
1694      OS << **i;
1695      if (llvm::next(i) != e)
1696        OS << " ";
1697    }
1698  }
1699
1700  // Print the regclass of any virtual registers encountered.
1701  if (MRI && !VirtRegs.empty()) {
1702    if (!HaveSemi) OS << ";"; HaveSemi = true;
1703    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1704      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1705      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1706      for (unsigned j = i+1; j != VirtRegs.size();) {
1707        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1708          ++j;
1709          continue;
1710        }
1711        if (VirtRegs[i] != VirtRegs[j])
1712          OS << "," << PrintReg(VirtRegs[j]);
1713        VirtRegs.erase(VirtRegs.begin()+j);
1714      }
1715    }
1716  }
1717
1718  // Print debug location information.
1719  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1720    if (!HaveSemi) OS << ";"; HaveSemi = true;
1721    DIVariable DV(getOperand(e - 1).getMetadata());
1722    OS << " line no:" <<  DV.getLineNumber();
1723    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1724      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1725      if (!InlinedAtDL.isUnknown()) {
1726        OS << " inlined @[ ";
1727        printDebugLoc(InlinedAtDL, MF, OS);
1728        OS << " ]";
1729      }
1730    }
1731  } else if (!debugLoc.isUnknown() && MF) {
1732    if (!HaveSemi) OS << ";"; HaveSemi = true;
1733    OS << " dbg:";
1734    printDebugLoc(debugLoc, MF, OS);
1735  }
1736
1737  OS << '\n';
1738}
1739
1740bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1741                                     const TargetRegisterInfo *RegInfo,
1742                                     bool AddIfNotFound) {
1743  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1744  bool hasAliases = isPhysReg &&
1745    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1746  bool Found = false;
1747  SmallVector<unsigned,4> DeadOps;
1748  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1749    MachineOperand &MO = getOperand(i);
1750    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1751      continue;
1752    unsigned Reg = MO.getReg();
1753    if (!Reg)
1754      continue;
1755
1756    if (Reg == IncomingReg) {
1757      if (!Found) {
1758        if (MO.isKill())
1759          // The register is already marked kill.
1760          return true;
1761        if (isPhysReg && isRegTiedToDefOperand(i))
1762          // Two-address uses of physregs must not be marked kill.
1763          return true;
1764        MO.setIsKill();
1765        Found = true;
1766      }
1767    } else if (hasAliases && MO.isKill() &&
1768               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1769      // A super-register kill already exists.
1770      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1771        return true;
1772      if (RegInfo->isSubRegister(IncomingReg, Reg))
1773        DeadOps.push_back(i);
1774    }
1775  }
1776
1777  // Trim unneeded kill operands.
1778  while (!DeadOps.empty()) {
1779    unsigned OpIdx = DeadOps.back();
1780    if (getOperand(OpIdx).isImplicit())
1781      RemoveOperand(OpIdx);
1782    else
1783      getOperand(OpIdx).setIsKill(false);
1784    DeadOps.pop_back();
1785  }
1786
1787  // If not found, this means an alias of one of the operands is killed. Add a
1788  // new implicit operand if required.
1789  if (!Found && AddIfNotFound) {
1790    addOperand(MachineOperand::CreateReg(IncomingReg,
1791                                         false /*IsDef*/,
1792                                         true  /*IsImp*/,
1793                                         true  /*IsKill*/));
1794    return true;
1795  }
1796  return Found;
1797}
1798
1799void MachineInstr::clearRegisterKills(unsigned Reg,
1800                                      const TargetRegisterInfo *RegInfo) {
1801  if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1802    RegInfo = 0;
1803  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1804    MachineOperand &MO = getOperand(i);
1805    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1806      continue;
1807    unsigned OpReg = MO.getReg();
1808    if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1809      MO.setIsKill(false);
1810  }
1811}
1812
1813bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1814                                   const TargetRegisterInfo *RegInfo,
1815                                   bool AddIfNotFound) {
1816  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1817  bool hasAliases = isPhysReg &&
1818    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1819  bool Found = false;
1820  SmallVector<unsigned,4> DeadOps;
1821  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1822    MachineOperand &MO = getOperand(i);
1823    if (!MO.isReg() || !MO.isDef())
1824      continue;
1825    unsigned Reg = MO.getReg();
1826    if (!Reg)
1827      continue;
1828
1829    if (Reg == IncomingReg) {
1830      MO.setIsDead();
1831      Found = true;
1832    } else if (hasAliases && MO.isDead() &&
1833               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1834      // There exists a super-register that's marked dead.
1835      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1836        return true;
1837      if (RegInfo->isSubRegister(IncomingReg, Reg))
1838        DeadOps.push_back(i);
1839    }
1840  }
1841
1842  // Trim unneeded dead operands.
1843  while (!DeadOps.empty()) {
1844    unsigned OpIdx = DeadOps.back();
1845    if (getOperand(OpIdx).isImplicit())
1846      RemoveOperand(OpIdx);
1847    else
1848      getOperand(OpIdx).setIsDead(false);
1849    DeadOps.pop_back();
1850  }
1851
1852  // If not found, this means an alias of one of the operands is dead. Add a
1853  // new implicit operand if required.
1854  if (Found || !AddIfNotFound)
1855    return Found;
1856
1857  addOperand(MachineOperand::CreateReg(IncomingReg,
1858                                       true  /*IsDef*/,
1859                                       true  /*IsImp*/,
1860                                       false /*IsKill*/,
1861                                       true  /*IsDead*/));
1862  return true;
1863}
1864
1865void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1866                                      const TargetRegisterInfo *RegInfo) {
1867  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1868    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1869    if (MO)
1870      return;
1871  } else {
1872    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1873      const MachineOperand &MO = getOperand(i);
1874      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1875          MO.getSubReg() == 0)
1876        return;
1877    }
1878  }
1879  addOperand(MachineOperand::CreateReg(IncomingReg,
1880                                       true  /*IsDef*/,
1881                                       true  /*IsImp*/));
1882}
1883
1884void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1885                                         const TargetRegisterInfo &TRI) {
1886  bool HasRegMask = false;
1887  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1888    MachineOperand &MO = getOperand(i);
1889    if (MO.isRegMask()) {
1890      HasRegMask = true;
1891      continue;
1892    }
1893    if (!MO.isReg() || !MO.isDef()) continue;
1894    unsigned Reg = MO.getReg();
1895    if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1896    bool Dead = true;
1897    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1898         I != E; ++I)
1899      if (TRI.regsOverlap(*I, Reg)) {
1900        Dead = false;
1901        break;
1902      }
1903    // If there are no uses, including partial uses, the def is dead.
1904    if (Dead) MO.setIsDead();
1905  }
1906
1907  // This is a call with a register mask operand.
1908  // Mask clobbers are always dead, so add defs for the non-dead defines.
1909  if (HasRegMask)
1910    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1911         I != E; ++I)
1912      addRegisterDefined(*I, &TRI);
1913}
1914
1915unsigned
1916MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1917  // Build up a buffer of hash code components.
1918  SmallVector<size_t, 8> HashComponents;
1919  HashComponents.reserve(MI->getNumOperands() + 1);
1920  HashComponents.push_back(MI->getOpcode());
1921  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1922    const MachineOperand &MO = MI->getOperand(i);
1923    if (MO.isReg() && MO.isDef() &&
1924        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1925      continue;  // Skip virtual register defs.
1926
1927    HashComponents.push_back(hash_value(MO));
1928  }
1929  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1930}
1931
1932void MachineInstr::emitError(StringRef Msg) const {
1933  // Find the source location cookie.
1934  unsigned LocCookie = 0;
1935  const MDNode *LocMD = 0;
1936  for (unsigned i = getNumOperands(); i != 0; --i) {
1937    if (getOperand(i-1).isMetadata() &&
1938        (LocMD = getOperand(i-1).getMetadata()) &&
1939        LocMD->getNumOperands() != 0) {
1940      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1941        LocCookie = CI->getZExtValue();
1942        break;
1943      }
1944    }
1945  }
1946
1947  if (const MachineBasicBlock *MBB = getParent())
1948    if (const MachineFunction *MF = MBB->getParent())
1949      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1950  report_fatal_error(Msg);
1951}
1952