MachineInstr.cpp revision 6dd97471c43805b3febf598d50498a09a02e93f4 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/Metadata.h"
19#include "llvm/Type.h"
20#include "llvm/Value.h"
21#include "llvm/Assembly/Writer.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetInstrDesc.h"
31#include "llvm/Target/TargetRegisterInfo.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/DebugInfo.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/LeakDetector.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/ADT/FoldingSet.h"
40using namespace llvm;
41
42//===----------------------------------------------------------------------===//
43// MachineOperand Implementation
44//===----------------------------------------------------------------------===//
45
46/// AddRegOperandToRegInfo - Add this register operand to the specified
47/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
48/// explicitly nulled out.
49void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50  assert(isReg() && "Can only add reg operand to use lists");
51
52  // If the reginfo pointer is null, just explicitly null out or next/prev
53  // pointers, to ensure they are not garbage.
54  if (RegInfo == 0) {
55    Contents.Reg.Prev = 0;
56    Contents.Reg.Next = 0;
57    return;
58  }
59
60  // Otherwise, add this operand to the head of the registers use/def list.
61  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
62
63  // For SSA values, we prefer to keep the definition at the start of the list.
64  // we do this by skipping over the definition if it is at the head of the
65  // list.
66  if (*Head && (*Head)->isDef())
67    Head = &(*Head)->Contents.Reg.Next;
68
69  Contents.Reg.Next = *Head;
70  if (Contents.Reg.Next) {
71    assert(getReg() == Contents.Reg.Next->getReg() &&
72           "Different regs on the same list!");
73    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
74  }
75
76  Contents.Reg.Prev = Head;
77  *Head = this;
78}
79
80/// RemoveRegOperandFromRegInfo - Remove this register operand from the
81/// MachineRegisterInfo it is linked with.
82void MachineOperand::RemoveRegOperandFromRegInfo() {
83  assert(isOnRegUseList() && "Reg operand is not on a use list");
84  // Unlink this from the doubly linked list of operands.
85  MachineOperand *NextOp = Contents.Reg.Next;
86  *Contents.Reg.Prev = NextOp;
87  if (NextOp) {
88    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
90  }
91  Contents.Reg.Prev = 0;
92  Contents.Reg.Next = 0;
93}
94
95void MachineOperand::setReg(unsigned Reg) {
96  if (getReg() == Reg) return; // No change.
97
98  // Otherwise, we have to change the register.  If this operand is embedded
99  // into a machine function, we need to update the old and new register's
100  // use/def lists.
101  if (MachineInstr *MI = getParent())
102    if (MachineBasicBlock *MBB = MI->getParent())
103      if (MachineFunction *MF = MBB->getParent()) {
104        RemoveRegOperandFromRegInfo();
105        SmallContents.RegNo = Reg;
106        AddRegOperandToRegInfo(&MF->getRegInfo());
107        return;
108      }
109
110  // Otherwise, just change the register, no problem.  :)
111  SmallContents.RegNo = Reg;
112}
113
114void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
115                                  const TargetRegisterInfo &TRI) {
116  assert(TargetRegisterInfo::isVirtualRegister(Reg));
117  if (SubIdx && getSubReg())
118    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
119  setReg(Reg);
120  if (SubIdx)
121    setSubReg(SubIdx);
122}
123
124void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
125  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
126  if (getSubReg()) {
127    Reg = TRI.getSubReg(Reg, getSubReg());
128    assert(Reg && "Invalid SubReg for physical register");
129    setSubReg(0);
130  }
131  setReg(Reg);
132}
133
134/// ChangeToImmediate - Replace this operand with a new immediate operand of
135/// the specified value.  If an operand is known to be an immediate already,
136/// the setImm method should be used.
137void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
138  // If this operand is currently a register operand, and if this is in a
139  // function, deregister the operand from the register's use/def list.
140  if (isReg() && getParent() && getParent()->getParent() &&
141      getParent()->getParent()->getParent())
142    RemoveRegOperandFromRegInfo();
143
144  OpKind = MO_Immediate;
145  Contents.ImmVal = ImmVal;
146}
147
148/// ChangeToRegister - Replace this operand with a new register operand of
149/// the specified value.  If an operand is known to be an register already,
150/// the setReg method should be used.
151void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
152                                      bool isKill, bool isDead, bool isUndef,
153                                      bool isDebug) {
154  // If this operand is already a register operand, use setReg to update the
155  // register's use/def lists.
156  if (isReg()) {
157    assert(!isEarlyClobber());
158    setReg(Reg);
159  } else {
160    // Otherwise, change this to a register and set the reg#.
161    OpKind = MO_Register;
162    SmallContents.RegNo = Reg;
163
164    // If this operand is embedded in a function, add the operand to the
165    // register's use/def list.
166    if (MachineInstr *MI = getParent())
167      if (MachineBasicBlock *MBB = MI->getParent())
168        if (MachineFunction *MF = MBB->getParent())
169          AddRegOperandToRegInfo(&MF->getRegInfo());
170  }
171
172  IsDef = isDef;
173  IsImp = isImp;
174  IsKill = isKill;
175  IsDead = isDead;
176  IsUndef = isUndef;
177  IsEarlyClobber = false;
178  IsDebug = isDebug;
179  SubReg = 0;
180}
181
182/// isIdenticalTo - Return true if this operand is identical to the specified
183/// operand.
184bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
185  if (getType() != Other.getType() ||
186      getTargetFlags() != Other.getTargetFlags())
187    return false;
188
189  switch (getType()) {
190  default: llvm_unreachable("Unrecognized operand type");
191  case MachineOperand::MO_Register:
192    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
193           getSubReg() == Other.getSubReg();
194  case MachineOperand::MO_Immediate:
195    return getImm() == Other.getImm();
196  case MachineOperand::MO_FPImmediate:
197    return getFPImm() == Other.getFPImm();
198  case MachineOperand::MO_MachineBasicBlock:
199    return getMBB() == Other.getMBB();
200  case MachineOperand::MO_FrameIndex:
201    return getIndex() == Other.getIndex();
202  case MachineOperand::MO_ConstantPoolIndex:
203    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
204  case MachineOperand::MO_JumpTableIndex:
205    return getIndex() == Other.getIndex();
206  case MachineOperand::MO_GlobalAddress:
207    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
208  case MachineOperand::MO_ExternalSymbol:
209    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
210           getOffset() == Other.getOffset();
211  case MachineOperand::MO_BlockAddress:
212    return getBlockAddress() == Other.getBlockAddress();
213  case MachineOperand::MO_MCSymbol:
214    return getMCSymbol() == Other.getMCSymbol();
215  case MachineOperand::MO_Metadata:
216    return getMetadata() == Other.getMetadata();
217  }
218}
219
220/// print - Print the specified machine operand.
221///
222void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
223  // If the instruction is embedded into a basic block, we can find the
224  // target info for the instruction.
225  if (!TM)
226    if (const MachineInstr *MI = getParent())
227      if (const MachineBasicBlock *MBB = MI->getParent())
228        if (const MachineFunction *MF = MBB->getParent())
229          TM = &MF->getTarget();
230  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
231
232  switch (getType()) {
233  case MachineOperand::MO_Register:
234    OS << PrintReg(getReg(), TRI, getSubReg());
235
236    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
237        isEarlyClobber()) {
238      OS << '<';
239      bool NeedComma = false;
240      if (isDef()) {
241        if (NeedComma) OS << ',';
242        if (isEarlyClobber())
243          OS << "earlyclobber,";
244        if (isImplicit())
245          OS << "imp-";
246        OS << "def";
247        NeedComma = true;
248      } else if (isImplicit()) {
249          OS << "imp-use";
250          NeedComma = true;
251      }
252
253      if (isKill() || isDead() || isUndef()) {
254        if (NeedComma) OS << ',';
255        if (isKill())  OS << "kill";
256        if (isDead())  OS << "dead";
257        if (isUndef()) {
258          if (isKill() || isDead())
259            OS << ',';
260          OS << "undef";
261        }
262      }
263      OS << '>';
264    }
265    break;
266  case MachineOperand::MO_Immediate:
267    OS << getImm();
268    break;
269  case MachineOperand::MO_FPImmediate:
270    if (getFPImm()->getType()->isFloatTy())
271      OS << getFPImm()->getValueAPF().convertToFloat();
272    else
273      OS << getFPImm()->getValueAPF().convertToDouble();
274    break;
275  case MachineOperand::MO_MachineBasicBlock:
276    OS << "<BB#" << getMBB()->getNumber() << ">";
277    break;
278  case MachineOperand::MO_FrameIndex:
279    OS << "<fi#" << getIndex() << '>';
280    break;
281  case MachineOperand::MO_ConstantPoolIndex:
282    OS << "<cp#" << getIndex();
283    if (getOffset()) OS << "+" << getOffset();
284    OS << '>';
285    break;
286  case MachineOperand::MO_JumpTableIndex:
287    OS << "<jt#" << getIndex() << '>';
288    break;
289  case MachineOperand::MO_GlobalAddress:
290    OS << "<ga:";
291    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
292    if (getOffset()) OS << "+" << getOffset();
293    OS << '>';
294    break;
295  case MachineOperand::MO_ExternalSymbol:
296    OS << "<es:" << getSymbolName();
297    if (getOffset()) OS << "+" << getOffset();
298    OS << '>';
299    break;
300  case MachineOperand::MO_BlockAddress:
301    OS << '<';
302    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
303    OS << '>';
304    break;
305  case MachineOperand::MO_Metadata:
306    OS << '<';
307    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
308    OS << '>';
309    break;
310  case MachineOperand::MO_MCSymbol:
311    OS << "<MCSym=" << *getMCSymbol() << '>';
312    break;
313  default:
314    llvm_unreachable("Unrecognized operand type");
315  }
316
317  if (unsigned TF = getTargetFlags())
318    OS << "[TF=" << TF << ']';
319}
320
321//===----------------------------------------------------------------------===//
322// MachineMemOperand Implementation
323//===----------------------------------------------------------------------===//
324
325/// getAddrSpace - Return the LLVM IR address space number that this pointer
326/// points into.
327unsigned MachinePointerInfo::getAddrSpace() const {
328  if (V == 0) return 0;
329  return cast<PointerType>(V->getType())->getAddressSpace();
330}
331
332/// getConstantPool - Return a MachinePointerInfo record that refers to the
333/// constant pool.
334MachinePointerInfo MachinePointerInfo::getConstantPool() {
335  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
336}
337
338/// getFixedStack - Return a MachinePointerInfo record that refers to the
339/// the specified FrameIndex.
340MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
341  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
342}
343
344MachinePointerInfo MachinePointerInfo::getJumpTable() {
345  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
346}
347
348MachinePointerInfo MachinePointerInfo::getGOT() {
349  return MachinePointerInfo(PseudoSourceValue::getGOT());
350}
351
352MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
353  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
354}
355
356MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
357                                     uint64_t s, unsigned int a,
358                                     const MDNode *TBAAInfo)
359  : PtrInfo(ptrinfo), Size(s),
360    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
361    TBAAInfo(TBAAInfo) {
362  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
363         "invalid pointer value");
364  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
365  assert((isLoad() || isStore()) && "Not a load/store!");
366}
367
368/// Profile - Gather unique data for the object.
369///
370void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
371  ID.AddInteger(getOffset());
372  ID.AddInteger(Size);
373  ID.AddPointer(getValue());
374  ID.AddInteger(Flags);
375}
376
377void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
378  // The Value and Offset may differ due to CSE. But the flags and size
379  // should be the same.
380  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
381  assert(MMO->getSize() == getSize() && "Size mismatch!");
382
383  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
384    // Update the alignment value.
385    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
386      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
387    // Also update the base and offset, because the new alignment may
388    // not be applicable with the old ones.
389    PtrInfo = MMO->PtrInfo;
390  }
391}
392
393/// getAlignment - Return the minimum known alignment in bytes of the
394/// actual memory reference.
395uint64_t MachineMemOperand::getAlignment() const {
396  return MinAlign(getBaseAlignment(), getOffset());
397}
398
399raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
400  assert((MMO.isLoad() || MMO.isStore()) &&
401         "SV has to be a load, store or both.");
402
403  if (MMO.isVolatile())
404    OS << "Volatile ";
405
406  if (MMO.isLoad())
407    OS << "LD";
408  if (MMO.isStore())
409    OS << "ST";
410  OS << MMO.getSize();
411
412  // Print the address information.
413  OS << "[";
414  if (!MMO.getValue())
415    OS << "<unknown>";
416  else
417    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
418
419  // If the alignment of the memory reference itself differs from the alignment
420  // of the base pointer, print the base alignment explicitly, next to the base
421  // pointer.
422  if (MMO.getBaseAlignment() != MMO.getAlignment())
423    OS << "(align=" << MMO.getBaseAlignment() << ")";
424
425  if (MMO.getOffset() != 0)
426    OS << "+" << MMO.getOffset();
427  OS << "]";
428
429  // Print the alignment of the reference.
430  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
431      MMO.getBaseAlignment() != MMO.getSize())
432    OS << "(align=" << MMO.getAlignment() << ")";
433
434  // Print TBAA info.
435  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
436    OS << "(tbaa=";
437    if (TBAAInfo->getNumOperands() > 0)
438      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
439    else
440      OS << "<unknown>";
441    OS << ")";
442  }
443
444  return OS;
445}
446
447//===----------------------------------------------------------------------===//
448// MachineInstr Implementation
449//===----------------------------------------------------------------------===//
450
451/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
452/// TID NULL and no operands.
453MachineInstr::MachineInstr()
454  : TID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
455    MemRefs(0), MemRefsEnd(0),
456    Parent(0) {
457  // Make sure that we get added to a machine basicblock
458  LeakDetector::addGarbageObject(this);
459}
460
461void MachineInstr::addImplicitDefUseOperands() {
462  if (TID->ImplicitDefs)
463    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
464      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
465  if (TID->ImplicitUses)
466    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
467      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
468}
469
470/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
471/// implicit operands. It reserves space for the number of operands specified by
472/// the TargetInstrDesc.
473MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
474  : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
475    MemRefs(0), MemRefsEnd(0), Parent(0) {
476  if (!NoImp)
477    NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
478  Operands.reserve(NumImplicitOps + TID->getNumOperands());
479  if (!NoImp)
480    addImplicitDefUseOperands();
481  // Make sure that we get added to a machine basicblock
482  LeakDetector::addGarbageObject(this);
483}
484
485/// MachineInstr ctor - As above, but with a DebugLoc.
486MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
487                           bool NoImp)
488  : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
489    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
490  if (!NoImp)
491    NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
492  Operands.reserve(NumImplicitOps + TID->getNumOperands());
493  if (!NoImp)
494    addImplicitDefUseOperands();
495  // Make sure that we get added to a machine basicblock
496  LeakDetector::addGarbageObject(this);
497}
498
499/// MachineInstr ctor - Work exactly the same as the ctor two above, except
500/// that the MachineInstr is created and added to the end of the specified
501/// basic block.
502MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
503  : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
504    MemRefs(0), MemRefsEnd(0), Parent(0) {
505  assert(MBB && "Cannot use inserting ctor with null basic block!");
506  NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
507  Operands.reserve(NumImplicitOps + TID->getNumOperands());
508  addImplicitDefUseOperands();
509  // Make sure that we get added to a machine basicblock
510  LeakDetector::addGarbageObject(this);
511  MBB->push_back(this);  // Add instruction to end of basic block!
512}
513
514/// MachineInstr ctor - As above, but with a DebugLoc.
515///
516MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
517                           const TargetInstrDesc &tid)
518  : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
519    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
520  assert(MBB && "Cannot use inserting ctor with null basic block!");
521  NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
522  Operands.reserve(NumImplicitOps + TID->getNumOperands());
523  addImplicitDefUseOperands();
524  // Make sure that we get added to a machine basicblock
525  LeakDetector::addGarbageObject(this);
526  MBB->push_back(this);  // Add instruction to end of basic block!
527}
528
529/// MachineInstr ctor - Copies MachineInstr arg exactly
530///
531MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
532  : TID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
533    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
534    Parent(0), debugLoc(MI.getDebugLoc()) {
535  Operands.reserve(MI.getNumOperands());
536
537  // Add operands
538  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
539    addOperand(MI.getOperand(i));
540  NumImplicitOps = MI.NumImplicitOps;
541
542  // Copy all the flags.
543  Flags = MI.Flags;
544
545  // Set parent to null.
546  Parent = 0;
547
548  LeakDetector::addGarbageObject(this);
549}
550
551MachineInstr::~MachineInstr() {
552  LeakDetector::removeGarbageObject(this);
553#ifndef NDEBUG
554  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
555    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
556    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
557           "Reg operand def/use list corrupted");
558  }
559#endif
560}
561
562/// getRegInfo - If this instruction is embedded into a MachineFunction,
563/// return the MachineRegisterInfo object for the current function, otherwise
564/// return null.
565MachineRegisterInfo *MachineInstr::getRegInfo() {
566  if (MachineBasicBlock *MBB = getParent())
567    return &MBB->getParent()->getRegInfo();
568  return 0;
569}
570
571/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
572/// this instruction from their respective use lists.  This requires that the
573/// operands already be on their use lists.
574void MachineInstr::RemoveRegOperandsFromUseLists() {
575  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
576    if (Operands[i].isReg())
577      Operands[i].RemoveRegOperandFromRegInfo();
578  }
579}
580
581/// AddRegOperandsToUseLists - Add all of the register operands in
582/// this instruction from their respective use lists.  This requires that the
583/// operands not be on their use lists yet.
584void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
585  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
586    if (Operands[i].isReg())
587      Operands[i].AddRegOperandToRegInfo(&RegInfo);
588  }
589}
590
591
592/// addOperand - Add the specified operand to the instruction.  If it is an
593/// implicit operand, it is added to the end of the operand list.  If it is
594/// an explicit operand it is added at the end of the explicit operand list
595/// (before the first implicit operand).
596void MachineInstr::addOperand(const MachineOperand &Op) {
597  bool isImpReg = Op.isReg() && Op.isImplicit();
598  assert((isImpReg || !OperandsComplete()) &&
599         "Trying to add an operand to a machine instr that is already done!");
600
601  MachineRegisterInfo *RegInfo = getRegInfo();
602
603  // If we are adding the operand to the end of the list, our job is simpler.
604  // This is true most of the time, so this is a reasonable optimization.
605  if (isImpReg || NumImplicitOps == 0) {
606    // We can only do this optimization if we know that the operand list won't
607    // reallocate.
608    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
609      Operands.push_back(Op);
610
611      // Set the parent of the operand.
612      Operands.back().ParentMI = this;
613
614      // If the operand is a register, update the operand's use list.
615      if (Op.isReg()) {
616        Operands.back().AddRegOperandToRegInfo(RegInfo);
617        // If the register operand is flagged as early, mark the operand as such
618        unsigned OpNo = Operands.size() - 1;
619        if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
620          Operands[OpNo].setIsEarlyClobber(true);
621      }
622      return;
623    }
624  }
625
626  // Otherwise, we have to insert a real operand before any implicit ones.
627  unsigned OpNo = Operands.size()-NumImplicitOps;
628
629  // If this instruction isn't embedded into a function, then we don't need to
630  // update any operand lists.
631  if (RegInfo == 0) {
632    // Simple insertion, no reginfo update needed for other register operands.
633    Operands.insert(Operands.begin()+OpNo, Op);
634    Operands[OpNo].ParentMI = this;
635
636    // Do explicitly set the reginfo for this operand though, to ensure the
637    // next/prev fields are properly nulled out.
638    if (Operands[OpNo].isReg()) {
639      Operands[OpNo].AddRegOperandToRegInfo(0);
640      // If the register operand is flagged as early, mark the operand as such
641      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
642        Operands[OpNo].setIsEarlyClobber(true);
643    }
644
645  } else if (Operands.size()+1 <= Operands.capacity()) {
646    // Otherwise, we have to remove register operands from their register use
647    // list, add the operand, then add the register operands back to their use
648    // list.  This also must handle the case when the operand list reallocates
649    // to somewhere else.
650
651    // If insertion of this operand won't cause reallocation of the operand
652    // list, just remove the implicit operands, add the operand, then re-add all
653    // the rest of the operands.
654    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
655      assert(Operands[i].isReg() && "Should only be an implicit reg!");
656      Operands[i].RemoveRegOperandFromRegInfo();
657    }
658
659    // Add the operand.  If it is a register, add it to the reg list.
660    Operands.insert(Operands.begin()+OpNo, Op);
661    Operands[OpNo].ParentMI = this;
662
663    if (Operands[OpNo].isReg()) {
664      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
665      // If the register operand is flagged as early, mark the operand as such
666      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
667        Operands[OpNo].setIsEarlyClobber(true);
668    }
669
670    // Re-add all the implicit ops.
671    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
672      assert(Operands[i].isReg() && "Should only be an implicit reg!");
673      Operands[i].AddRegOperandToRegInfo(RegInfo);
674    }
675  } else {
676    // Otherwise, we will be reallocating the operand list.  Remove all reg
677    // operands from their list, then readd them after the operand list is
678    // reallocated.
679    RemoveRegOperandsFromUseLists();
680
681    Operands.insert(Operands.begin()+OpNo, Op);
682    Operands[OpNo].ParentMI = this;
683
684    // Re-add all the operands.
685    AddRegOperandsToUseLists(*RegInfo);
686
687      // If the register operand is flagged as early, mark the operand as such
688    if (Operands[OpNo].isReg()
689        && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
690      Operands[OpNo].setIsEarlyClobber(true);
691  }
692}
693
694/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
695/// fewer operand than it started with.
696///
697void MachineInstr::RemoveOperand(unsigned OpNo) {
698  assert(OpNo < Operands.size() && "Invalid operand number");
699
700  // Special case removing the last one.
701  if (OpNo == Operands.size()-1) {
702    // If needed, remove from the reg def/use list.
703    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
704      Operands.back().RemoveRegOperandFromRegInfo();
705
706    Operands.pop_back();
707    return;
708  }
709
710  // Otherwise, we are removing an interior operand.  If we have reginfo to
711  // update, remove all operands that will be shifted down from their reg lists,
712  // move everything down, then re-add them.
713  MachineRegisterInfo *RegInfo = getRegInfo();
714  if (RegInfo) {
715    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
716      if (Operands[i].isReg())
717        Operands[i].RemoveRegOperandFromRegInfo();
718    }
719  }
720
721  Operands.erase(Operands.begin()+OpNo);
722
723  if (RegInfo) {
724    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
725      if (Operands[i].isReg())
726        Operands[i].AddRegOperandToRegInfo(RegInfo);
727    }
728  }
729}
730
731/// addMemOperand - Add a MachineMemOperand to the machine instruction.
732/// This function should be used only occasionally. The setMemRefs function
733/// is the primary method for setting up a MachineInstr's MemRefs list.
734void MachineInstr::addMemOperand(MachineFunction &MF,
735                                 MachineMemOperand *MO) {
736  mmo_iterator OldMemRefs = MemRefs;
737  mmo_iterator OldMemRefsEnd = MemRefsEnd;
738
739  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
740  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
741  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
742
743  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
744  NewMemRefs[NewNum - 1] = MO;
745
746  MemRefs = NewMemRefs;
747  MemRefsEnd = NewMemRefsEnd;
748}
749
750bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
751                                 MICheckType Check) const {
752  // If opcodes or number of operands are not the same then the two
753  // instructions are obviously not identical.
754  if (Other->getOpcode() != getOpcode() ||
755      Other->getNumOperands() != getNumOperands())
756    return false;
757
758  // Check operands to make sure they match.
759  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
760    const MachineOperand &MO = getOperand(i);
761    const MachineOperand &OMO = Other->getOperand(i);
762    // Clients may or may not want to ignore defs when testing for equality.
763    // For example, machine CSE pass only cares about finding common
764    // subexpressions, so it's safe to ignore virtual register defs.
765    if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
766      if (Check == IgnoreDefs)
767        continue;
768      // Check == IgnoreVRegDefs
769      if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
770          TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
771        if (MO.getReg() != OMO.getReg())
772          return false;
773    } else if (!MO.isIdenticalTo(OMO))
774      return false;
775  }
776  return true;
777}
778
779/// removeFromParent - This method unlinks 'this' from the containing basic
780/// block, and returns it, but does not delete it.
781MachineInstr *MachineInstr::removeFromParent() {
782  assert(getParent() && "Not embedded in a basic block!");
783  getParent()->remove(this);
784  return this;
785}
786
787
788/// eraseFromParent - This method unlinks 'this' from the containing basic
789/// block, and deletes it.
790void MachineInstr::eraseFromParent() {
791  assert(getParent() && "Not embedded in a basic block!");
792  getParent()->erase(this);
793}
794
795
796/// OperandComplete - Return true if it's illegal to add a new operand
797///
798bool MachineInstr::OperandsComplete() const {
799  unsigned short NumOperands = TID->getNumOperands();
800  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
801    return true;  // Broken: we have all the operands of this instruction!
802  return false;
803}
804
805/// getNumExplicitOperands - Returns the number of non-implicit operands.
806///
807unsigned MachineInstr::getNumExplicitOperands() const {
808  unsigned NumOperands = TID->getNumOperands();
809  if (!TID->isVariadic())
810    return NumOperands;
811
812  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
813    const MachineOperand &MO = getOperand(i);
814    if (!MO.isReg() || !MO.isImplicit())
815      NumOperands++;
816  }
817  return NumOperands;
818}
819
820bool MachineInstr::isStackAligningInlineAsm() const {
821  if (isInlineAsm()) {
822    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
823    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
824      return true;
825  }
826  return false;
827}
828
829/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
830/// the specific register or -1 if it is not found. It further tightens
831/// the search criteria to a use that kills the register if isKill is true.
832int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
833                                          const TargetRegisterInfo *TRI) const {
834  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
835    const MachineOperand &MO = getOperand(i);
836    if (!MO.isReg() || !MO.isUse())
837      continue;
838    unsigned MOReg = MO.getReg();
839    if (!MOReg)
840      continue;
841    if (MOReg == Reg ||
842        (TRI &&
843         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
844         TargetRegisterInfo::isPhysicalRegister(Reg) &&
845         TRI->isSubRegister(MOReg, Reg)))
846      if (!isKill || MO.isKill())
847        return i;
848  }
849  return -1;
850}
851
852/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
853/// indicating if this instruction reads or writes Reg. This also considers
854/// partial defines.
855std::pair<bool,bool>
856MachineInstr::readsWritesVirtualRegister(unsigned Reg,
857                                         SmallVectorImpl<unsigned> *Ops) const {
858  bool PartDef = false; // Partial redefine.
859  bool FullDef = false; // Full define.
860  bool Use = false;
861
862  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
863    const MachineOperand &MO = getOperand(i);
864    if (!MO.isReg() || MO.getReg() != Reg)
865      continue;
866    if (Ops)
867      Ops->push_back(i);
868    if (MO.isUse())
869      Use |= !MO.isUndef();
870    else if (MO.getSubReg())
871      PartDef = true;
872    else
873      FullDef = true;
874  }
875  // A partial redefine uses Reg unless there is also a full define.
876  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
877}
878
879/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
880/// the specified register or -1 if it is not found. If isDead is true, defs
881/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
882/// also checks if there is a def of a super-register.
883int
884MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
885                                        const TargetRegisterInfo *TRI) const {
886  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
887  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
888    const MachineOperand &MO = getOperand(i);
889    if (!MO.isReg() || !MO.isDef())
890      continue;
891    unsigned MOReg = MO.getReg();
892    bool Found = (MOReg == Reg);
893    if (!Found && TRI && isPhys &&
894        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
895      if (Overlap)
896        Found = TRI->regsOverlap(MOReg, Reg);
897      else
898        Found = TRI->isSubRegister(MOReg, Reg);
899    }
900    if (Found && (!isDead || MO.isDead()))
901      return i;
902  }
903  return -1;
904}
905
906/// findFirstPredOperandIdx() - Find the index of the first operand in the
907/// operand list that is used to represent the predicate. It returns -1 if
908/// none is found.
909int MachineInstr::findFirstPredOperandIdx() const {
910  const TargetInstrDesc &TID = getDesc();
911  if (TID.isPredicable()) {
912    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
913      if (TID.OpInfo[i].isPredicate())
914        return i;
915  }
916
917  return -1;
918}
919
920/// isRegTiedToUseOperand - Given the index of a register def operand,
921/// check if the register def is tied to a source operand, due to either
922/// two-address elimination or inline assembly constraints. Returns the
923/// first tied use operand index by reference is UseOpIdx is not null.
924bool MachineInstr::
925isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
926  if (isInlineAsm()) {
927    assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
928    const MachineOperand &MO = getOperand(DefOpIdx);
929    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
930      return false;
931    // Determine the actual operand index that corresponds to this index.
932    unsigned DefNo = 0;
933    unsigned DefPart = 0;
934    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
935         i < e; ) {
936      const MachineOperand &FMO = getOperand(i);
937      // After the normal asm operands there may be additional imp-def regs.
938      if (!FMO.isImm())
939        return false;
940      // Skip over this def.
941      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
942      unsigned PrevDef = i + 1;
943      i = PrevDef + NumOps;
944      if (i > DefOpIdx) {
945        DefPart = DefOpIdx - PrevDef;
946        break;
947      }
948      ++DefNo;
949    }
950    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
951         i != e; ++i) {
952      const MachineOperand &FMO = getOperand(i);
953      if (!FMO.isImm())
954        continue;
955      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
956        continue;
957      unsigned Idx;
958      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
959          Idx == DefNo) {
960        if (UseOpIdx)
961          *UseOpIdx = (unsigned)i + 1 + DefPart;
962        return true;
963      }
964    }
965    return false;
966  }
967
968  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
969  const TargetInstrDesc &TID = getDesc();
970  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
971    const MachineOperand &MO = getOperand(i);
972    if (MO.isReg() && MO.isUse() &&
973        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
974      if (UseOpIdx)
975        *UseOpIdx = (unsigned)i;
976      return true;
977    }
978  }
979  return false;
980}
981
982/// isRegTiedToDefOperand - Return true if the operand of the specified index
983/// is a register use and it is tied to an def operand. It also returns the def
984/// operand index by reference.
985bool MachineInstr::
986isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
987  if (isInlineAsm()) {
988    const MachineOperand &MO = getOperand(UseOpIdx);
989    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
990      return false;
991
992    // Find the flag operand corresponding to UseOpIdx
993    unsigned FlagIdx, NumOps=0;
994    for (FlagIdx = InlineAsm::MIOp_FirstOperand;
995         FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
996      const MachineOperand &UFMO = getOperand(FlagIdx);
997      // After the normal asm operands there may be additional imp-def regs.
998      if (!UFMO.isImm())
999        return false;
1000      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
1001      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
1002      if (UseOpIdx < FlagIdx+NumOps+1)
1003        break;
1004    }
1005    if (FlagIdx >= UseOpIdx)
1006      return false;
1007    const MachineOperand &UFMO = getOperand(FlagIdx);
1008    unsigned DefNo;
1009    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1010      if (!DefOpIdx)
1011        return true;
1012
1013      unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1014      // Remember to adjust the index. First operand is asm string, second is
1015      // the HasSideEffects and AlignStack bits, then there is a flag for each.
1016      while (DefNo) {
1017        const MachineOperand &FMO = getOperand(DefIdx);
1018        assert(FMO.isImm());
1019        // Skip over this def.
1020        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1021        --DefNo;
1022      }
1023      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1024      return true;
1025    }
1026    return false;
1027  }
1028
1029  const TargetInstrDesc &TID = getDesc();
1030  if (UseOpIdx >= TID.getNumOperands())
1031    return false;
1032  const MachineOperand &MO = getOperand(UseOpIdx);
1033  if (!MO.isReg() || !MO.isUse())
1034    return false;
1035  int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
1036  if (DefIdx == -1)
1037    return false;
1038  if (DefOpIdx)
1039    *DefOpIdx = (unsigned)DefIdx;
1040  return true;
1041}
1042
1043/// clearKillInfo - Clears kill flags on all operands.
1044///
1045void MachineInstr::clearKillInfo() {
1046  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1047    MachineOperand &MO = getOperand(i);
1048    if (MO.isReg() && MO.isUse())
1049      MO.setIsKill(false);
1050  }
1051}
1052
1053/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1054///
1055void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1056  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1057    const MachineOperand &MO = MI->getOperand(i);
1058    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1059      continue;
1060    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1061      MachineOperand &MOp = getOperand(j);
1062      if (!MOp.isIdenticalTo(MO))
1063        continue;
1064      if (MO.isKill())
1065        MOp.setIsKill();
1066      else
1067        MOp.setIsDead();
1068      break;
1069    }
1070  }
1071}
1072
1073/// copyPredicates - Copies predicate operand(s) from MI.
1074void MachineInstr::copyPredicates(const MachineInstr *MI) {
1075  const TargetInstrDesc &TID = MI->getDesc();
1076  if (!TID.isPredicable())
1077    return;
1078  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1079    if (TID.OpInfo[i].isPredicate()) {
1080      // Predicated operands must be last operands.
1081      addOperand(MI->getOperand(i));
1082    }
1083  }
1084}
1085
1086void MachineInstr::substituteRegister(unsigned FromReg,
1087                                      unsigned ToReg,
1088                                      unsigned SubIdx,
1089                                      const TargetRegisterInfo &RegInfo) {
1090  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1091    if (SubIdx)
1092      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1093    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1094      MachineOperand &MO = getOperand(i);
1095      if (!MO.isReg() || MO.getReg() != FromReg)
1096        continue;
1097      MO.substPhysReg(ToReg, RegInfo);
1098    }
1099  } else {
1100    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1101      MachineOperand &MO = getOperand(i);
1102      if (!MO.isReg() || MO.getReg() != FromReg)
1103        continue;
1104      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1105    }
1106  }
1107}
1108
1109/// isSafeToMove - Return true if it is safe to move this instruction. If
1110/// SawStore is set to true, it means that there is a store (or call) between
1111/// the instruction's location and its intended destination.
1112bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1113                                AliasAnalysis *AA,
1114                                bool &SawStore) const {
1115  // Ignore stuff that we obviously can't move.
1116  if (TID->mayStore() || TID->isCall()) {
1117    SawStore = true;
1118    return false;
1119  }
1120
1121  if (isLabel() || isDebugValue() ||
1122      TID->isTerminator() || hasUnmodeledSideEffects())
1123    return false;
1124
1125  // See if this instruction does a load.  If so, we have to guarantee that the
1126  // loaded value doesn't change between the load and the its intended
1127  // destination. The check for isInvariantLoad gives the targe the chance to
1128  // classify the load as always returning a constant, e.g. a constant pool
1129  // load.
1130  if (TID->mayLoad() && !isInvariantLoad(AA))
1131    // Otherwise, this is a real load.  If there is a store between the load and
1132    // end of block, or if the load is volatile, we can't move it.
1133    return !SawStore && !hasVolatileMemoryRef();
1134
1135  return true;
1136}
1137
1138/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1139/// instruction which defined the specified register instead of copying it.
1140bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1141                                 AliasAnalysis *AA,
1142                                 unsigned DstReg) const {
1143  bool SawStore = false;
1144  if (!TII->isTriviallyReMaterializable(this, AA) ||
1145      !isSafeToMove(TII, AA, SawStore))
1146    return false;
1147  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1148    const MachineOperand &MO = getOperand(i);
1149    if (!MO.isReg())
1150      continue;
1151    // FIXME: For now, do not remat any instruction with register operands.
1152    // Later on, we can loosen the restriction is the register operands have
1153    // not been modified between the def and use. Note, this is different from
1154    // MachineSink because the code is no longer in two-address form (at least
1155    // partially).
1156    if (MO.isUse())
1157      return false;
1158    else if (!MO.isDead() && MO.getReg() != DstReg)
1159      return false;
1160  }
1161  return true;
1162}
1163
1164/// hasVolatileMemoryRef - Return true if this instruction may have a
1165/// volatile memory reference, or if the information describing the
1166/// memory reference is not available. Return false if it is known to
1167/// have no volatile memory references.
1168bool MachineInstr::hasVolatileMemoryRef() const {
1169  // An instruction known never to access memory won't have a volatile access.
1170  if (!TID->mayStore() &&
1171      !TID->mayLoad() &&
1172      !TID->isCall() &&
1173      !hasUnmodeledSideEffects())
1174    return false;
1175
1176  // Otherwise, if the instruction has no memory reference information,
1177  // conservatively assume it wasn't preserved.
1178  if (memoperands_empty())
1179    return true;
1180
1181  // Check the memory reference information for volatile references.
1182  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1183    if ((*I)->isVolatile())
1184      return true;
1185
1186  return false;
1187}
1188
1189/// isInvariantLoad - Return true if this instruction is loading from a
1190/// location whose value is invariant across the function.  For example,
1191/// loading a value from the constant pool or from the argument area
1192/// of a function if it does not change.  This should only return true of
1193/// *all* loads the instruction does are invariant (if it does multiple loads).
1194bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1195  // If the instruction doesn't load at all, it isn't an invariant load.
1196  if (!TID->mayLoad())
1197    return false;
1198
1199  // If the instruction has lost its memoperands, conservatively assume that
1200  // it may not be an invariant load.
1201  if (memoperands_empty())
1202    return false;
1203
1204  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1205
1206  for (mmo_iterator I = memoperands_begin(),
1207       E = memoperands_end(); I != E; ++I) {
1208    if ((*I)->isVolatile()) return false;
1209    if ((*I)->isStore()) return false;
1210
1211    if (const Value *V = (*I)->getValue()) {
1212      // A load from a constant PseudoSourceValue is invariant.
1213      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1214        if (PSV->isConstant(MFI))
1215          continue;
1216      // If we have an AliasAnalysis, ask it whether the memory is constant.
1217      if (AA && AA->pointsToConstantMemory(
1218                      AliasAnalysis::Location(V, (*I)->getSize(),
1219                                              (*I)->getTBAAInfo())))
1220        continue;
1221    }
1222
1223    // Otherwise assume conservatively.
1224    return false;
1225  }
1226
1227  // Everything checks out.
1228  return true;
1229}
1230
1231/// isConstantValuePHI - If the specified instruction is a PHI that always
1232/// merges together the same virtual register, return the register, otherwise
1233/// return 0.
1234unsigned MachineInstr::isConstantValuePHI() const {
1235  if (!isPHI())
1236    return 0;
1237  assert(getNumOperands() >= 3 &&
1238         "It's illegal to have a PHI without source operands");
1239
1240  unsigned Reg = getOperand(1).getReg();
1241  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1242    if (getOperand(i).getReg() != Reg)
1243      return 0;
1244  return Reg;
1245}
1246
1247bool MachineInstr::hasUnmodeledSideEffects() const {
1248  if (getDesc().hasUnmodeledSideEffects())
1249    return true;
1250  if (isInlineAsm()) {
1251    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1252    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1253      return true;
1254  }
1255
1256  return false;
1257}
1258
1259/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1260///
1261bool MachineInstr::allDefsAreDead() const {
1262  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1263    const MachineOperand &MO = getOperand(i);
1264    if (!MO.isReg() || MO.isUse())
1265      continue;
1266    if (!MO.isDead())
1267      return false;
1268  }
1269  return true;
1270}
1271
1272/// copyImplicitOps - Copy implicit register operands from specified
1273/// instruction to this instruction.
1274void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1275  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1276       i != e; ++i) {
1277    const MachineOperand &MO = MI->getOperand(i);
1278    if (MO.isReg() && MO.isImplicit())
1279      addOperand(MO);
1280  }
1281}
1282
1283void MachineInstr::dump() const {
1284  dbgs() << "  " << *this;
1285}
1286
1287static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1288                         raw_ostream &CommentOS) {
1289  const LLVMContext &Ctx = MF->getFunction()->getContext();
1290  if (!DL.isUnknown()) {          // Print source line info.
1291    DIScope Scope(DL.getScope(Ctx));
1292    // Omit the directory, because it's likely to be long and uninteresting.
1293    if (Scope.Verify())
1294      CommentOS << Scope.getFilename();
1295    else
1296      CommentOS << "<unknown>";
1297    CommentOS << ':' << DL.getLine();
1298    if (DL.getCol() != 0)
1299      CommentOS << ':' << DL.getCol();
1300    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1301    if (!InlinedAtDL.isUnknown()) {
1302      CommentOS << " @[ ";
1303      printDebugLoc(InlinedAtDL, MF, CommentOS);
1304      CommentOS << " ]";
1305    }
1306  }
1307}
1308
1309void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1310  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1311  const MachineFunction *MF = 0;
1312  const MachineRegisterInfo *MRI = 0;
1313  if (const MachineBasicBlock *MBB = getParent()) {
1314    MF = MBB->getParent();
1315    if (!TM && MF)
1316      TM = &MF->getTarget();
1317    if (MF)
1318      MRI = &MF->getRegInfo();
1319  }
1320
1321  // Save a list of virtual registers.
1322  SmallVector<unsigned, 8> VirtRegs;
1323
1324  // Print explicitly defined operands on the left of an assignment syntax.
1325  unsigned StartOp = 0, e = getNumOperands();
1326  for (; StartOp < e && getOperand(StartOp).isReg() &&
1327         getOperand(StartOp).isDef() &&
1328         !getOperand(StartOp).isImplicit();
1329       ++StartOp) {
1330    if (StartOp != 0) OS << ", ";
1331    getOperand(StartOp).print(OS, TM);
1332    unsigned Reg = getOperand(StartOp).getReg();
1333    if (TargetRegisterInfo::isVirtualRegister(Reg))
1334      VirtRegs.push_back(Reg);
1335  }
1336
1337  if (StartOp != 0)
1338    OS << " = ";
1339
1340  // Print the opcode name.
1341  OS << getDesc().getName();
1342
1343  // Print the rest of the operands.
1344  bool OmittedAnyCallClobbers = false;
1345  bool FirstOp = true;
1346
1347  if (isInlineAsm()) {
1348    // Print asm string.
1349    OS << " ";
1350    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1351
1352    // Print HasSideEffects, IsAlignStack
1353    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1354    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1355      OS << " [sideeffect]";
1356    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1357      OS << " [alignstack]";
1358
1359    StartOp = InlineAsm::MIOp_FirstOperand;
1360    FirstOp = false;
1361  }
1362
1363
1364  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1365    const MachineOperand &MO = getOperand(i);
1366
1367    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1368      VirtRegs.push_back(MO.getReg());
1369
1370    // Omit call-clobbered registers which aren't used anywhere. This makes
1371    // call instructions much less noisy on targets where calls clobber lots
1372    // of registers. Don't rely on MO.isDead() because we may be called before
1373    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1374    if (MF && getDesc().isCall() &&
1375        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1376      unsigned Reg = MO.getReg();
1377      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1378        const MachineRegisterInfo &MRI = MF->getRegInfo();
1379        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1380          bool HasAliasLive = false;
1381          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1382               unsigned AliasReg = *Alias; ++Alias)
1383            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1384              HasAliasLive = true;
1385              break;
1386            }
1387          if (!HasAliasLive) {
1388            OmittedAnyCallClobbers = true;
1389            continue;
1390          }
1391        }
1392      }
1393    }
1394
1395    if (FirstOp) FirstOp = false; else OS << ",";
1396    OS << " ";
1397    if (i < getDesc().NumOperands) {
1398      const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1399      if (TOI.isPredicate())
1400        OS << "pred:";
1401      if (TOI.isOptionalDef())
1402        OS << "opt:";
1403    }
1404    if (isDebugValue() && MO.isMetadata()) {
1405      // Pretty print DBG_VALUE instructions.
1406      const MDNode *MD = MO.getMetadata();
1407      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1408        OS << "!\"" << MDS->getString() << '\"';
1409      else
1410        MO.print(OS, TM);
1411    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1412      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1413    } else
1414      MO.print(OS, TM);
1415  }
1416
1417  // Briefly indicate whether any call clobbers were omitted.
1418  if (OmittedAnyCallClobbers) {
1419    if (!FirstOp) OS << ",";
1420    OS << " ...";
1421  }
1422
1423  bool HaveSemi = false;
1424  if (Flags) {
1425    if (!HaveSemi) OS << ";"; HaveSemi = true;
1426    OS << " flags: ";
1427
1428    if (Flags & FrameSetup)
1429      OS << "FrameSetup";
1430  }
1431
1432  if (!memoperands_empty()) {
1433    if (!HaveSemi) OS << ";"; HaveSemi = true;
1434
1435    OS << " mem:";
1436    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1437         i != e; ++i) {
1438      OS << **i;
1439      if (llvm::next(i) != e)
1440        OS << " ";
1441    }
1442  }
1443
1444  // Print the regclass of any virtual registers encountered.
1445  if (MRI && !VirtRegs.empty()) {
1446    if (!HaveSemi) OS << ";"; HaveSemi = true;
1447    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1448      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1449      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1450      for (unsigned j = i+1; j != VirtRegs.size();) {
1451        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1452          ++j;
1453          continue;
1454        }
1455        if (VirtRegs[i] != VirtRegs[j])
1456          OS << "," << PrintReg(VirtRegs[j]);
1457        VirtRegs.erase(VirtRegs.begin()+j);
1458      }
1459    }
1460  }
1461
1462  // Print debug location information.
1463  if (!debugLoc.isUnknown() && MF) {
1464    if (!HaveSemi) OS << ";"; HaveSemi = true;
1465    OS << " dbg:";
1466    printDebugLoc(debugLoc, MF, OS);
1467  }
1468
1469  OS << '\n';
1470}
1471
1472bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1473                                     const TargetRegisterInfo *RegInfo,
1474                                     bool AddIfNotFound) {
1475  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1476  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1477  bool Found = false;
1478  SmallVector<unsigned,4> DeadOps;
1479  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1480    MachineOperand &MO = getOperand(i);
1481    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1482      continue;
1483    unsigned Reg = MO.getReg();
1484    if (!Reg)
1485      continue;
1486
1487    if (Reg == IncomingReg) {
1488      if (!Found) {
1489        if (MO.isKill())
1490          // The register is already marked kill.
1491          return true;
1492        if (isPhysReg && isRegTiedToDefOperand(i))
1493          // Two-address uses of physregs must not be marked kill.
1494          return true;
1495        MO.setIsKill();
1496        Found = true;
1497      }
1498    } else if (hasAliases && MO.isKill() &&
1499               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1500      // A super-register kill already exists.
1501      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1502        return true;
1503      if (RegInfo->isSubRegister(IncomingReg, Reg))
1504        DeadOps.push_back(i);
1505    }
1506  }
1507
1508  // Trim unneeded kill operands.
1509  while (!DeadOps.empty()) {
1510    unsigned OpIdx = DeadOps.back();
1511    if (getOperand(OpIdx).isImplicit())
1512      RemoveOperand(OpIdx);
1513    else
1514      getOperand(OpIdx).setIsKill(false);
1515    DeadOps.pop_back();
1516  }
1517
1518  // If not found, this means an alias of one of the operands is killed. Add a
1519  // new implicit operand if required.
1520  if (!Found && AddIfNotFound) {
1521    addOperand(MachineOperand::CreateReg(IncomingReg,
1522                                         false /*IsDef*/,
1523                                         true  /*IsImp*/,
1524                                         true  /*IsKill*/));
1525    return true;
1526  }
1527  return Found;
1528}
1529
1530bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1531                                   const TargetRegisterInfo *RegInfo,
1532                                   bool AddIfNotFound) {
1533  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1534  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1535  bool Found = false;
1536  SmallVector<unsigned,4> DeadOps;
1537  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1538    MachineOperand &MO = getOperand(i);
1539    if (!MO.isReg() || !MO.isDef())
1540      continue;
1541    unsigned Reg = MO.getReg();
1542    if (!Reg)
1543      continue;
1544
1545    if (Reg == IncomingReg) {
1546      if (!Found) {
1547        if (MO.isDead())
1548          // The register is already marked dead.
1549          return true;
1550        MO.setIsDead();
1551        Found = true;
1552      }
1553    } else if (hasAliases && MO.isDead() &&
1554               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1555      // There exists a super-register that's marked dead.
1556      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1557        return true;
1558      if (RegInfo->getSubRegisters(IncomingReg) &&
1559          RegInfo->getSuperRegisters(Reg) &&
1560          RegInfo->isSubRegister(IncomingReg, Reg))
1561        DeadOps.push_back(i);
1562    }
1563  }
1564
1565  // Trim unneeded dead operands.
1566  while (!DeadOps.empty()) {
1567    unsigned OpIdx = DeadOps.back();
1568    if (getOperand(OpIdx).isImplicit())
1569      RemoveOperand(OpIdx);
1570    else
1571      getOperand(OpIdx).setIsDead(false);
1572    DeadOps.pop_back();
1573  }
1574
1575  // If not found, this means an alias of one of the operands is dead. Add a
1576  // new implicit operand if required.
1577  if (Found || !AddIfNotFound)
1578    return Found;
1579
1580  addOperand(MachineOperand::CreateReg(IncomingReg,
1581                                       true  /*IsDef*/,
1582                                       true  /*IsImp*/,
1583                                       false /*IsKill*/,
1584                                       true  /*IsDead*/));
1585  return true;
1586}
1587
1588void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1589                                      const TargetRegisterInfo *RegInfo) {
1590  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1591    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1592    if (MO)
1593      return;
1594  } else {
1595    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1596      const MachineOperand &MO = getOperand(i);
1597      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1598          MO.getSubReg() == 0)
1599        return;
1600    }
1601  }
1602  addOperand(MachineOperand::CreateReg(IncomingReg,
1603                                       true  /*IsDef*/,
1604                                       true  /*IsImp*/));
1605}
1606
1607void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1608                                         const TargetRegisterInfo &TRI) {
1609  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1610    MachineOperand &MO = getOperand(i);
1611    if (!MO.isReg() || !MO.isDef()) continue;
1612    unsigned Reg = MO.getReg();
1613    if (Reg == 0) continue;
1614    bool Dead = true;
1615    for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1616         E = UsedRegs.end(); I != E; ++I)
1617      if (TRI.regsOverlap(*I, Reg)) {
1618        Dead = false;
1619        break;
1620      }
1621    // If there are no uses, including partial uses, the def is dead.
1622    if (Dead) MO.setIsDead();
1623  }
1624}
1625
1626unsigned
1627MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1628  unsigned Hash = MI->getOpcode() * 37;
1629  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1630    const MachineOperand &MO = MI->getOperand(i);
1631    uint64_t Key = (uint64_t)MO.getType() << 32;
1632    switch (MO.getType()) {
1633    default: break;
1634    case MachineOperand::MO_Register:
1635      if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1636        continue;  // Skip virtual register defs.
1637      Key |= MO.getReg();
1638      break;
1639    case MachineOperand::MO_Immediate:
1640      Key |= MO.getImm();
1641      break;
1642    case MachineOperand::MO_FrameIndex:
1643    case MachineOperand::MO_ConstantPoolIndex:
1644    case MachineOperand::MO_JumpTableIndex:
1645      Key |= MO.getIndex();
1646      break;
1647    case MachineOperand::MO_MachineBasicBlock:
1648      Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1649      break;
1650    case MachineOperand::MO_GlobalAddress:
1651      Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1652      break;
1653    case MachineOperand::MO_BlockAddress:
1654      Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1655      break;
1656    case MachineOperand::MO_MCSymbol:
1657      Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1658      break;
1659    }
1660    Key += ~(Key << 32);
1661    Key ^= (Key >> 22);
1662    Key += ~(Key << 13);
1663    Key ^= (Key >> 8);
1664    Key += (Key << 3);
1665    Key ^= (Key >> 15);
1666    Key += ~(Key << 27);
1667    Key ^= (Key >> 31);
1668    Hash = (unsigned)Key + Hash * 37;
1669  }
1670  return Hash;
1671}
1672