MachineInstr.cpp revision 9b6d7b9fb36b5cf87d291881dfcea399796f7826 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Constants.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/Value.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/PseudoSourceValue.h"
20#include "llvm/CodeGen/SelectionDAGNodes.h"
21#include "llvm/Target/TargetMachine.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Target/TargetInstrDesc.h"
24#include "llvm/Target/TargetRegisterInfo.h"
25#include "llvm/Support/LeakDetector.h"
26#include "llvm/Support/Streams.h"
27#include <ostream>
28using namespace llvm;
29
30//===----------------------------------------------------------------------===//
31// MachineOperand Implementation
32//===----------------------------------------------------------------------===//
33
34/// AddRegOperandToRegInfo - Add this register operand to the specified
35/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
36/// explicitly nulled out.
37void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
38  assert(isReg() && "Can only add reg operand to use lists");
39
40  // If the reginfo pointer is null, just explicitly null out or next/prev
41  // pointers, to ensure they are not garbage.
42  if (RegInfo == 0) {
43    Contents.Reg.Prev = 0;
44    Contents.Reg.Next = 0;
45    return;
46  }
47
48  // Otherwise, add this operand to the head of the registers use/def list.
49  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
50
51  // For SSA values, we prefer to keep the definition at the start of the list.
52  // we do this by skipping over the definition if it is at the head of the
53  // list.
54  if (*Head && (*Head)->isDef())
55    Head = &(*Head)->Contents.Reg.Next;
56
57  Contents.Reg.Next = *Head;
58  if (Contents.Reg.Next) {
59    assert(getReg() == Contents.Reg.Next->getReg() &&
60           "Different regs on the same list!");
61    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
62  }
63
64  Contents.Reg.Prev = Head;
65  *Head = this;
66}
67
68void MachineOperand::setReg(unsigned Reg) {
69  if (getReg() == Reg) return; // No change.
70
71  // Otherwise, we have to change the register.  If this operand is embedded
72  // into a machine function, we need to update the old and new register's
73  // use/def lists.
74  if (MachineInstr *MI = getParent())
75    if (MachineBasicBlock *MBB = MI->getParent())
76      if (MachineFunction *MF = MBB->getParent()) {
77        RemoveRegOperandFromRegInfo();
78        Contents.Reg.RegNo = Reg;
79        AddRegOperandToRegInfo(&MF->getRegInfo());
80        return;
81      }
82
83  // Otherwise, just change the register, no problem.  :)
84  Contents.Reg.RegNo = Reg;
85}
86
87/// ChangeToImmediate - Replace this operand with a new immediate operand of
88/// the specified value.  If an operand is known to be an immediate already,
89/// the setImm method should be used.
90void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
91  // If this operand is currently a register operand, and if this is in a
92  // function, deregister the operand from the register's use/def list.
93  if (isReg() && getParent() && getParent()->getParent() &&
94      getParent()->getParent()->getParent())
95    RemoveRegOperandFromRegInfo();
96
97  OpKind = MO_Immediate;
98  Contents.ImmVal = ImmVal;
99}
100
101/// ChangeToRegister - Replace this operand with a new register operand of
102/// the specified value.  If an operand is known to be an register already,
103/// the setReg method should be used.
104void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
105                                      bool isKill, bool isDead) {
106  // If this operand is already a register operand, use setReg to update the
107  // register's use/def lists.
108  if (isReg()) {
109    setReg(Reg);
110  } else {
111    // Otherwise, change this to a register and set the reg#.
112    OpKind = MO_Register;
113    Contents.Reg.RegNo = Reg;
114
115    // If this operand is embedded in a function, add the operand to the
116    // register's use/def list.
117    if (MachineInstr *MI = getParent())
118      if (MachineBasicBlock *MBB = MI->getParent())
119        if (MachineFunction *MF = MBB->getParent())
120          AddRegOperandToRegInfo(&MF->getRegInfo());
121  }
122
123  IsDef = isDef;
124  IsImp = isImp;
125  IsKill = isKill;
126  IsDead = isDead;
127  SubReg = 0;
128}
129
130/// isIdenticalTo - Return true if this operand is identical to the specified
131/// operand.
132bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
133  if (getType() != Other.getType()) return false;
134
135  switch (getType()) {
136  default: assert(0 && "Unrecognized operand type");
137  case MachineOperand::MO_Register:
138    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
139           getSubReg() == Other.getSubReg();
140  case MachineOperand::MO_Immediate:
141    return getImm() == Other.getImm();
142  case MachineOperand::MO_FPImmediate:
143    return getFPImm() == Other.getFPImm();
144  case MachineOperand::MO_MachineBasicBlock:
145    return getMBB() == Other.getMBB();
146  case MachineOperand::MO_FrameIndex:
147    return getIndex() == Other.getIndex();
148  case MachineOperand::MO_ConstantPoolIndex:
149    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
150  case MachineOperand::MO_JumpTableIndex:
151    return getIndex() == Other.getIndex();
152  case MachineOperand::MO_GlobalAddress:
153    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
154  case MachineOperand::MO_ExternalSymbol:
155    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
156           getOffset() == Other.getOffset();
157  }
158}
159
160/// print - Print the specified machine operand.
161///
162void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
163  switch (getType()) {
164  case MachineOperand::MO_Register:
165    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
166      OS << "%reg" << getReg();
167    } else {
168      // If the instruction is embedded into a basic block, we can find the
169      // target info for the instruction.
170      if (TM == 0)
171        if (const MachineInstr *MI = getParent())
172          if (const MachineBasicBlock *MBB = MI->getParent())
173            if (const MachineFunction *MF = MBB->getParent())
174              TM = &MF->getTarget();
175
176      if (TM)
177        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
178      else
179        OS << "%mreg" << getReg();
180    }
181
182    if (isDef() || isKill() || isDead() || isImplicit()) {
183      OS << "<";
184      bool NeedComma = false;
185      if (isImplicit()) {
186        OS << (isDef() ? "imp-def" : "imp-use");
187        NeedComma = true;
188      } else if (isDef()) {
189        OS << "def";
190        NeedComma = true;
191      }
192      if (isKill() || isDead()) {
193        if (NeedComma) OS << ",";
194        if (isKill())  OS << "kill";
195        if (isDead())  OS << "dead";
196      }
197      OS << ">";
198    }
199    break;
200  case MachineOperand::MO_Immediate:
201    OS << getImm();
202    break;
203  case MachineOperand::MO_FPImmediate:
204    if (getFPImm()->getType() == Type::FloatTy) {
205      OS << getFPImm()->getValueAPF().convertToFloat();
206    } else {
207      OS << getFPImm()->getValueAPF().convertToDouble();
208    }
209    break;
210  case MachineOperand::MO_MachineBasicBlock:
211    OS << "mbb<"
212       << ((Value*)getMBB()->getBasicBlock())->getName()
213       << "," << (void*)getMBB() << ">";
214    break;
215  case MachineOperand::MO_FrameIndex:
216    OS << "<fi#" << getIndex() << ">";
217    break;
218  case MachineOperand::MO_ConstantPoolIndex:
219    OS << "<cp#" << getIndex();
220    if (getOffset()) OS << "+" << getOffset();
221    OS << ">";
222    break;
223  case MachineOperand::MO_JumpTableIndex:
224    OS << "<jt#" << getIndex() << ">";
225    break;
226  case MachineOperand::MO_GlobalAddress:
227    OS << "<ga:" << ((Value*)getGlobal())->getName();
228    if (getOffset()) OS << "+" << getOffset();
229    OS << ">";
230    break;
231  case MachineOperand::MO_ExternalSymbol:
232    OS << "<es:" << getSymbolName();
233    if (getOffset()) OS << "+" << getOffset();
234    OS << ">";
235    break;
236  default:
237    assert(0 && "Unrecognized operand type");
238  }
239}
240
241//===----------------------------------------------------------------------===//
242// MachineInstr Implementation
243//===----------------------------------------------------------------------===//
244
245/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
246/// TID NULL and no operands.
247MachineInstr::MachineInstr()
248  : TID(0), NumImplicitOps(0), Parent(0) {
249  // Make sure that we get added to a machine basicblock
250  LeakDetector::addGarbageObject(this);
251}
252
253void MachineInstr::addImplicitDefUseOperands() {
254  if (TID->ImplicitDefs)
255    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
256      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
257  if (TID->ImplicitUses)
258    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
259      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
260}
261
262/// MachineInstr ctor - This constructor create a MachineInstr and add the
263/// implicit operands. It reserves space for number of operands specified by
264/// TargetInstrDesc or the numOperands if it is not zero. (for
265/// instructions with variable number of operands).
266MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
267  : TID(&tid), NumImplicitOps(0), Parent(0) {
268  if (!NoImp && TID->getImplicitDefs())
269    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
270      NumImplicitOps++;
271  if (!NoImp && TID->getImplicitUses())
272    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
273      NumImplicitOps++;
274  Operands.reserve(NumImplicitOps + TID->getNumOperands());
275  if (!NoImp)
276    addImplicitDefUseOperands();
277  // Make sure that we get added to a machine basicblock
278  LeakDetector::addGarbageObject(this);
279}
280
281/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
282/// MachineInstr is created and added to the end of the specified basic block.
283///
284MachineInstr::MachineInstr(MachineBasicBlock *MBB,
285                           const TargetInstrDesc &tid)
286  : TID(&tid), NumImplicitOps(0), Parent(0) {
287  assert(MBB && "Cannot use inserting ctor with null basic block!");
288  if (TID->ImplicitDefs)
289    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
290      NumImplicitOps++;
291  if (TID->ImplicitUses)
292    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
293      NumImplicitOps++;
294  Operands.reserve(NumImplicitOps + TID->getNumOperands());
295  addImplicitDefUseOperands();
296  // Make sure that we get added to a machine basicblock
297  LeakDetector::addGarbageObject(this);
298  MBB->push_back(this);  // Add instruction to end of basic block!
299}
300
301/// MachineInstr ctor - Copies MachineInstr arg exactly
302///
303MachineInstr::MachineInstr(const MachineInstr &MI) {
304  TID = &MI.getDesc();
305  NumImplicitOps = MI.NumImplicitOps;
306  Operands.reserve(MI.getNumOperands());
307  MemOperands = MI.MemOperands;
308
309  // Add operands
310  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
311    Operands.push_back(MI.getOperand(i));
312    Operands.back().ParentMI = this;
313  }
314
315  // Set parent, next, and prev to null
316  Parent = 0;
317  Prev = 0;
318  Next = 0;
319}
320
321
322MachineInstr::~MachineInstr() {
323  LeakDetector::removeGarbageObject(this);
324#ifndef NDEBUG
325  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
326    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
327    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
328           "Reg operand def/use list corrupted");
329  }
330#endif
331}
332
333/// getOpcode - Returns the opcode of this MachineInstr.
334///
335int MachineInstr::getOpcode() const {
336  return TID->Opcode;
337}
338
339/// getRegInfo - If this instruction is embedded into a MachineFunction,
340/// return the MachineRegisterInfo object for the current function, otherwise
341/// return null.
342MachineRegisterInfo *MachineInstr::getRegInfo() {
343  if (MachineBasicBlock *MBB = getParent())
344    if (MachineFunction *MF = MBB->getParent())
345      return &MF->getRegInfo();
346  return 0;
347}
348
349/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
350/// this instruction from their respective use lists.  This requires that the
351/// operands already be on their use lists.
352void MachineInstr::RemoveRegOperandsFromUseLists() {
353  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
354    if (Operands[i].isReg())
355      Operands[i].RemoveRegOperandFromRegInfo();
356  }
357}
358
359/// AddRegOperandsToUseLists - Add all of the register operands in
360/// this instruction from their respective use lists.  This requires that the
361/// operands not be on their use lists yet.
362void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
363  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
364    if (Operands[i].isReg())
365      Operands[i].AddRegOperandToRegInfo(&RegInfo);
366  }
367}
368
369
370/// addOperand - Add the specified operand to the instruction.  If it is an
371/// implicit operand, it is added to the end of the operand list.  If it is
372/// an explicit operand it is added at the end of the explicit operand list
373/// (before the first implicit operand).
374void MachineInstr::addOperand(const MachineOperand &Op) {
375  bool isImpReg = Op.isReg() && Op.isImplicit();
376  assert((isImpReg || !OperandsComplete()) &&
377         "Trying to add an operand to a machine instr that is already done!");
378
379  // If we are adding the operand to the end of the list, our job is simpler.
380  // This is true most of the time, so this is a reasonable optimization.
381  if (isImpReg || NumImplicitOps == 0) {
382    // We can only do this optimization if we know that the operand list won't
383    // reallocate.
384    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
385      Operands.push_back(Op);
386
387      // Set the parent of the operand.
388      Operands.back().ParentMI = this;
389
390      // If the operand is a register, update the operand's use list.
391      if (Op.isReg())
392        Operands.back().AddRegOperandToRegInfo(getRegInfo());
393      return;
394    }
395  }
396
397  // Otherwise, we have to insert a real operand before any implicit ones.
398  unsigned OpNo = Operands.size()-NumImplicitOps;
399
400  MachineRegisterInfo *RegInfo = getRegInfo();
401
402  // If this instruction isn't embedded into a function, then we don't need to
403  // update any operand lists.
404  if (RegInfo == 0) {
405    // Simple insertion, no reginfo update needed for other register operands.
406    Operands.insert(Operands.begin()+OpNo, Op);
407    Operands[OpNo].ParentMI = this;
408
409    // Do explicitly set the reginfo for this operand though, to ensure the
410    // next/prev fields are properly nulled out.
411    if (Operands[OpNo].isReg())
412      Operands[OpNo].AddRegOperandToRegInfo(0);
413
414  } else if (Operands.size()+1 <= Operands.capacity()) {
415    // Otherwise, we have to remove register operands from their register use
416    // list, add the operand, then add the register operands back to their use
417    // list.  This also must handle the case when the operand list reallocates
418    // to somewhere else.
419
420    // If insertion of this operand won't cause reallocation of the operand
421    // list, just remove the implicit operands, add the operand, then re-add all
422    // the rest of the operands.
423    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
424      assert(Operands[i].isReg() && "Should only be an implicit reg!");
425      Operands[i].RemoveRegOperandFromRegInfo();
426    }
427
428    // Add the operand.  If it is a register, add it to the reg list.
429    Operands.insert(Operands.begin()+OpNo, Op);
430    Operands[OpNo].ParentMI = this;
431
432    if (Operands[OpNo].isReg())
433      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
434
435    // Re-add all the implicit ops.
436    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
437      assert(Operands[i].isReg() && "Should only be an implicit reg!");
438      Operands[i].AddRegOperandToRegInfo(RegInfo);
439    }
440  } else {
441    // Otherwise, we will be reallocating the operand list.  Remove all reg
442    // operands from their list, then readd them after the operand list is
443    // reallocated.
444    RemoveRegOperandsFromUseLists();
445
446    Operands.insert(Operands.begin()+OpNo, Op);
447    Operands[OpNo].ParentMI = this;
448
449    // Re-add all the operands.
450    AddRegOperandsToUseLists(*RegInfo);
451  }
452}
453
454/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
455/// fewer operand than it started with.
456///
457void MachineInstr::RemoveOperand(unsigned OpNo) {
458  assert(OpNo < Operands.size() && "Invalid operand number");
459
460  // Special case removing the last one.
461  if (OpNo == Operands.size()-1) {
462    // If needed, remove from the reg def/use list.
463    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
464      Operands.back().RemoveRegOperandFromRegInfo();
465
466    Operands.pop_back();
467    return;
468  }
469
470  // Otherwise, we are removing an interior operand.  If we have reginfo to
471  // update, remove all operands that will be shifted down from their reg lists,
472  // move everything down, then re-add them.
473  MachineRegisterInfo *RegInfo = getRegInfo();
474  if (RegInfo) {
475    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
476      if (Operands[i].isReg())
477        Operands[i].RemoveRegOperandFromRegInfo();
478    }
479  }
480
481  Operands.erase(Operands.begin()+OpNo);
482
483  if (RegInfo) {
484    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
485      if (Operands[i].isReg())
486        Operands[i].AddRegOperandToRegInfo(RegInfo);
487    }
488  }
489}
490
491
492/// removeFromParent - This method unlinks 'this' from the containing basic
493/// block, and returns it, but does not delete it.
494MachineInstr *MachineInstr::removeFromParent() {
495  assert(getParent() && "Not embedded in a basic block!");
496  getParent()->remove(this);
497  return this;
498}
499
500
501/// OperandComplete - Return true if it's illegal to add a new operand
502///
503bool MachineInstr::OperandsComplete() const {
504  unsigned short NumOperands = TID->getNumOperands();
505  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
506    return true;  // Broken: we have all the operands of this instruction!
507  return false;
508}
509
510/// getNumExplicitOperands - Returns the number of non-implicit operands.
511///
512unsigned MachineInstr::getNumExplicitOperands() const {
513  unsigned NumOperands = TID->getNumOperands();
514  if (!TID->isVariadic())
515    return NumOperands;
516
517  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
518    const MachineOperand &MO = getOperand(NumOperands);
519    if (!MO.isRegister() || !MO.isImplicit())
520      NumOperands++;
521  }
522  return NumOperands;
523}
524
525
526/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
527///
528bool MachineInstr::isDebugLabel() const {
529  return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0;
530}
531
532/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
533/// the specific register or -1 if it is not found. It further tightening
534/// the search criteria to a use that kills the register if isKill is true.
535int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
536                                          const TargetRegisterInfo *TRI) const {
537  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
538    const MachineOperand &MO = getOperand(i);
539    if (!MO.isRegister() || !MO.isUse())
540      continue;
541    unsigned MOReg = MO.getReg();
542    if (!MOReg)
543      continue;
544    if (MOReg == Reg ||
545        (TRI &&
546         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
547         TargetRegisterInfo::isPhysicalRegister(Reg) &&
548         TRI->isSubRegister(MOReg, Reg)))
549      if (!isKill || MO.isKill())
550        return i;
551  }
552  return -1;
553}
554
555/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
556/// the specific register or -1 if it is not found. It further tightening
557  /// the search criteria to a def that is dead the register if isDead is true.
558int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
559                                          const TargetRegisterInfo *TRI) const {
560  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
561    const MachineOperand &MO = getOperand(i);
562    if (!MO.isRegister() || !MO.isDef())
563      continue;
564    unsigned MOReg = MO.getReg();
565    if (MOReg == Reg ||
566        (TRI &&
567         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
568         TargetRegisterInfo::isPhysicalRegister(Reg) &&
569         TRI->isSubRegister(MOReg, Reg)))
570      if (!isDead || MO.isDead())
571        return i;
572  }
573  return -1;
574}
575
576/// findFirstPredOperandIdx() - Find the index of the first operand in the
577/// operand list that is used to represent the predicate. It returns -1 if
578/// none is found.
579int MachineInstr::findFirstPredOperandIdx() const {
580  const TargetInstrDesc &TID = getDesc();
581  if (TID.isPredicable()) {
582    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
583      if (TID.OpInfo[i].isPredicate())
584        return i;
585  }
586
587  return -1;
588}
589
590/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
591/// to two addr elimination.
592bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
593  const TargetInstrDesc &TID = getDesc();
594  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
595    const MachineOperand &MO1 = getOperand(i);
596    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
597      for (unsigned j = i+1; j < e; ++j) {
598        const MachineOperand &MO2 = getOperand(j);
599        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
600            TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
601          return true;
602      }
603    }
604  }
605  return false;
606}
607
608/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
609///
610void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
611  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
612    const MachineOperand &MO = MI->getOperand(i);
613    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
614      continue;
615    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
616      MachineOperand &MOp = getOperand(j);
617      if (!MOp.isIdenticalTo(MO))
618        continue;
619      if (MO.isKill())
620        MOp.setIsKill();
621      else
622        MOp.setIsDead();
623      break;
624    }
625  }
626}
627
628/// copyPredicates - Copies predicate operand(s) from MI.
629void MachineInstr::copyPredicates(const MachineInstr *MI) {
630  const TargetInstrDesc &TID = MI->getDesc();
631  if (!TID.isPredicable())
632    return;
633  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
634    if (TID.OpInfo[i].isPredicate()) {
635      // Predicated operands must be last operands.
636      addOperand(MI->getOperand(i));
637    }
638  }
639}
640
641/// isSafeToMove - Return true if it is safe to this instruction. If SawStore
642/// true, it means there is a store (or call) between the instruction the
643/// localtion and its intended destination.
644bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
645  // Ignore stuff that we obviously can't move.
646  if (TID->mayStore() || TID->isCall()) {
647    SawStore = true;
648    return false;
649  }
650  if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
651    return false;
652
653  // See if this instruction does a load.  If so, we have to guarantee that the
654  // loaded value doesn't change between the load and the its intended
655  // destination. The check for isInvariantLoad gives the targe the chance to
656  // classify the load as always returning a constant, e.g. a constant pool
657  // load.
658  if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
659    // Otherwise, this is a real load.  If there is a store between the load and
660    // end of block, we can't sink the load.
661    //
662    // FIXME: we can't do this transformation until we know that the load is
663    // not volatile, and machineinstrs don't keep this info. :(
664    //
665    //if (SawStore)
666    return false;
667  }
668  return true;
669}
670
671void MachineInstr::dump() const {
672  cerr << "  " << *this;
673}
674
675void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
676  // Specialize printing if op#0 is definition
677  unsigned StartOp = 0;
678  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
679    getOperand(0).print(OS, TM);
680    OS << " = ";
681    ++StartOp;   // Don't print this operand again!
682  }
683
684  OS << getDesc().getName();
685
686  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
687    if (i != StartOp)
688      OS << ",";
689    OS << " ";
690    getOperand(i).print(OS, TM);
691  }
692
693  if (getNumMemOperands() > 0) {
694    OS << ", Mem:";
695    for (unsigned i = 0; i < getNumMemOperands(); i++) {
696      const MachineMemOperand &MRO = getMemOperand(i);
697      const Value *V = MRO.getValue();
698
699      assert((MRO.isLoad() || MRO.isStore()) &&
700             "SV has to be a load, store or both.");
701
702      if (MRO.isVolatile())
703        OS << "Volatile ";
704
705      if (MRO.isLoad())
706        OS << "LD";
707      if (MRO.isStore())
708        OS << "ST";
709
710      OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
711
712      if (!V)
713        OS << "<unknown>";
714      else if (!V->getName().empty())
715        OS << V->getName();
716      else if (isa<PseudoSourceValue>(V))
717        OS << *V;
718      else
719        OS << V;
720
721      OS << " + " << MRO.getOffset() << "]";
722    }
723  }
724
725  OS << "\n";
726}
727
728bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
729                                     const TargetRegisterInfo *RegInfo,
730                                     bool AddIfNotFound) {
731  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
732  bool Found = false;
733  SmallVector<unsigned,4> DeadOps;
734  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
735    MachineOperand &MO = getOperand(i);
736    if (!MO.isRegister() || !MO.isUse())
737      continue;
738    unsigned Reg = MO.getReg();
739    if (!Reg)
740      continue;
741
742    if (Reg == IncomingReg) {
743      if (!Found)  // One kill of reg per instruction.
744        MO.setIsKill();
745      Found = true;
746    } else if (isPhysReg && MO.isKill() &&
747               TargetRegisterInfo::isPhysicalRegister(Reg)) {
748      // A super-register kill already exists.
749      if (RegInfo->isSuperRegister(IncomingReg, Reg))
750        Found = true;
751      else if (RegInfo->isSubRegister(IncomingReg, Reg))
752        DeadOps.push_back(i);
753    }
754  }
755
756  // Trim unneeded kill operands.
757  while (!DeadOps.empty()) {
758    unsigned OpIdx = DeadOps.back();
759    if (getOperand(OpIdx).isImplicit())
760      RemoveOperand(OpIdx);
761    else
762      getOperand(OpIdx).setIsKill(false);
763    DeadOps.pop_back();
764  }
765
766  // If not found, this means an alias of one of the operands is killed. Add a
767  // new implicit operand if required.
768  if (!Found && AddIfNotFound) {
769    addOperand(MachineOperand::CreateReg(IncomingReg,
770                                         false /*IsDef*/,
771                                         true  /*IsImp*/,
772                                         true  /*IsKill*/));
773    return true;
774  }
775  return Found;
776}
777
778bool MachineInstr::addRegisterDead(unsigned IncomingReg,
779                                   const TargetRegisterInfo *RegInfo,
780                                   bool AddIfNotFound) {
781  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
782  bool Found = false;
783  SmallVector<unsigned,4> DeadOps;
784  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
785    MachineOperand &MO = getOperand(i);
786    if (!MO.isRegister() || !MO.isDef())
787      continue;
788    unsigned Reg = MO.getReg();
789    if (Reg == IncomingReg) {
790      MO.setIsDead();
791      Found = true;
792    } else if (isPhysReg && MO.isDead() &&
793        TargetRegisterInfo::isPhysicalRegister(Reg)) {
794      // There exists a super-register that's marked dead.
795      if (RegInfo->isSuperRegister(IncomingReg, Reg))
796        Found = true;
797      else if (RegInfo->isSubRegister(IncomingReg, Reg))
798        DeadOps.push_back(i);
799    }
800  }
801
802  // Trim unneeded dead operands.
803  while (!DeadOps.empty()) {
804    unsigned OpIdx = DeadOps.back();
805    if (getOperand(OpIdx).isImplicit())
806      RemoveOperand(OpIdx);
807    else
808      getOperand(OpIdx).setIsDead(false);
809    DeadOps.pop_back();
810  }
811
812  // If not found, this means an alias of one of the operand is dead. Add a
813  // new implicit operand.
814  if (!Found && AddIfNotFound) {
815    addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
816                                         true/*IsImp*/,false/*IsKill*/,
817                                         true/*IsDead*/));
818    return true;
819  }
820  return Found;
821}
822
823/// copyKillDeadInfo - copies killed/dead information from one instr to another
824void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
825                                    const TargetRegisterInfo *RegInfo) {
826  // If the instruction defines any virtual registers, update the VarInfo,
827  // kill and dead information for the instruction.
828  for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
829    MachineOperand &MO = OldMI->getOperand(i);
830    if (MO.isRegister() && MO.getReg() &&
831        TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
832      unsigned Reg = MO.getReg();
833      if (MO.isDef()) {
834        if (MO.isDead()) {
835          MO.setIsDead(false);
836          addRegisterDead(Reg, RegInfo);
837        }
838      }
839      if (MO.isKill()) {
840        MO.setIsKill(false);
841        addRegisterKilled(Reg, RegInfo);
842      }
843    }
844  }
845}
846