1//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPURegisterInfo.h"
16#include "AMDGPUTargetMachine.h"
17
18using namespace llvm;
19
20AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
21
22//===----------------------------------------------------------------------===//
23// Function handling callbacks - Functions are a seldom used feature of GPUS, so
24// they are not supported at this time.
25//===----------------------------------------------------------------------===//
26
27const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
28
29const MCPhysReg*
30AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
31  return &CalleeSavedReg;
32}
33
34void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
35                                             int SPAdj,
36                                             unsigned FIOperandNum,
37                                             RegScavenger *RS) const {
38  llvm_unreachable("Subroutines not supported yet");
39}
40
41unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
42  return AMDGPU::NoRegister;
43}
44
45unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
46  static const unsigned SubRegs[] = {
47    AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
48    AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
49    AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
50    AMDGPU::sub15
51  };
52
53  assert(Channel < array_lengthof(SubRegs));
54  return SubRegs[Channel];
55}
56
57unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
58
59  return getSubRegFromChannel(IndirectIndex);
60}
61
62#define GET_REGINFO_TARGET_DESC
63#include "AMDGPUGenRegisterInfo.inc"
64