ARMBaseInstrInfo.h revision 2062875a7d8f7dd94a20d9e3a298e9e216efb4b5 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21namespace llvm {
22  class ARMSubtarget;
23  class ARMBaseRegisterInfo;
24
25/// ARMII - This namespace holds all of the target specific flags that
26/// instruction info tracks.
27///
28namespace ARMII {
29  enum {
30    //===------------------------------------------------------------------===//
31    // Instruction Flags.
32
33    //===------------------------------------------------------------------===//
34    // This four-bit field describes the addressing mode used.
35
36    AddrModeMask  = 0xf,
37    AddrModeNone    = 0,
38    AddrMode1       = 1,
39    AddrMode2       = 2,
40    AddrMode3       = 3,
41    AddrMode4       = 4,
42    AddrMode5       = 5,
43    AddrMode6       = 6,
44    AddrModeT1_1    = 7,
45    AddrModeT1_2    = 8,
46    AddrModeT1_4    = 9,
47    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
48    AddrModeT2_i12  = 11,
49    AddrModeT2_i8   = 12,
50    AddrModeT2_so   = 13,
51    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
52    AddrModeT2_i8s4 = 15, // i8 * 4
53
54    // Size* - Flags to keep track of the size of an instruction.
55    SizeShift     = 4,
56    SizeMask      = 7 << SizeShift,
57    SizeSpecial   = 1,   // 0 byte pseudo or special case.
58    Size8Bytes    = 2,
59    Size4Bytes    = 3,
60    Size2Bytes    = 4,
61
62    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
63    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
64    IndexModeShift = 7,
65    IndexModeMask  = 3 << IndexModeShift,
66    IndexModePre   = 1,
67    IndexModePost  = 2,
68    IndexModeUpd   = 3,
69
70    //===------------------------------------------------------------------===//
71    // Instruction encoding formats.
72    //
73    FormShift     = 9,
74    FormMask      = 0x3f << FormShift,
75
76    // Pseudo instructions
77    Pseudo        = 0  << FormShift,
78
79    // Multiply instructions
80    MulFrm        = 1  << FormShift,
81
82    // Branch instructions
83    BrFrm         = 2  << FormShift,
84    BrMiscFrm     = 3  << FormShift,
85
86    // Data Processing instructions
87    DPFrm         = 4  << FormShift,
88    DPSoRegFrm    = 5  << FormShift,
89
90    // Load and Store
91    LdFrm         = 6  << FormShift,
92    StFrm         = 7  << FormShift,
93    LdMiscFrm     = 8  << FormShift,
94    StMiscFrm     = 9  << FormShift,
95    LdStMulFrm    = 10 << FormShift,
96
97    LdStExFrm     = 11 << FormShift,
98
99    // Miscellaneous arithmetic instructions
100    ArithMiscFrm  = 12 << FormShift,
101
102    // Extend instructions
103    ExtFrm        = 13 << FormShift,
104
105    // VFP formats
106    VFPUnaryFrm   = 14 << FormShift,
107    VFPBinaryFrm  = 15 << FormShift,
108    VFPConv1Frm   = 16 << FormShift,
109    VFPConv2Frm   = 17 << FormShift,
110    VFPConv3Frm   = 18 << FormShift,
111    VFPConv4Frm   = 19 << FormShift,
112    VFPConv5Frm   = 20 << FormShift,
113    VFPLdStFrm    = 21 << FormShift,
114    VFPLdStMulFrm = 22 << FormShift,
115    VFPMiscFrm    = 23 << FormShift,
116
117    // Thumb format
118    ThumbFrm      = 24 << FormShift,
119
120    // Miscelleaneous format
121    MiscFrm       = 25 << FormShift,
122
123    // NEON formats
124    NGetLnFrm     = 26 << FormShift,
125    NSetLnFrm     = 27 << FormShift,
126    NDupFrm       = 28 << FormShift,
127    NLdStFrm      = 29 << FormShift,
128    N1RegModImmFrm= 30 << FormShift,
129    N2RegFrm      = 31 << FormShift,
130    NVCVTFrm      = 32 << FormShift,
131    NVDupLnFrm    = 33 << FormShift,
132    N2RegVShLFrm  = 34 << FormShift,
133    N2RegVShRFrm  = 35 << FormShift,
134    N3RegFrm      = 36 << FormShift,
135    N3RegVShFrm   = 37 << FormShift,
136    NVExtFrm      = 38 << FormShift,
137    NVMulSLFrm    = 39 << FormShift,
138    NVTBLFrm      = 40 << FormShift,
139
140    //===------------------------------------------------------------------===//
141    // Misc flags.
142
143    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
144    // it doesn't have a Rn operand.
145    UnaryDP       = 1 << 15,
146
147    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
148    // a 16-bit Thumb instruction if certain conditions are met.
149    Xform16Bit    = 1 << 16,
150
151    //===------------------------------------------------------------------===//
152    // Code domain.
153    DomainShift   = 17,
154    DomainMask    = 3 << DomainShift,
155    DomainGeneral = 0 << DomainShift,
156    DomainVFP     = 1 << DomainShift,
157    DomainNEON    = 2 << DomainShift,
158
159    //===------------------------------------------------------------------===//
160    // Field shifts - such shifts are used to set field while generating
161    // machine instructions.
162    M_BitShift     = 5,
163    ShiftImmShift  = 5,
164    ShiftShift     = 7,
165    N_BitShift     = 7,
166    ImmHiShift     = 8,
167    SoRotImmShift  = 8,
168    RegRsShift     = 8,
169    ExtRotImmShift = 10,
170    RegRdLoShift   = 12,
171    RegRdShift     = 12,
172    RegRdHiShift   = 16,
173    RegRnShift     = 16,
174    S_BitShift     = 20,
175    W_BitShift     = 21,
176    AM3_I_BitShift = 22,
177    D_BitShift     = 22,
178    U_BitShift     = 23,
179    P_BitShift     = 24,
180    I_BitShift     = 25,
181    CondShift      = 28
182  };
183
184  /// Target Operand Flag enum.
185  enum TOF {
186    //===------------------------------------------------------------------===//
187    // ARM Specific MachineOperand flags.
188
189    MO_NO_FLAG,
190
191    /// MO_LO16 - On a symbol operand, this represents a relocation containing
192    /// lower 16 bit of the address. Used only via movw instruction.
193    MO_LO16,
194
195    /// MO_HI16 - On a symbol operand, this represents a relocation containing
196    /// higher 16 bit of the address. Used only via movt instruction.
197    MO_HI16
198  };
199}
200
201class ARMBaseInstrInfo : public TargetInstrInfoImpl {
202  const ARMSubtarget &Subtarget;
203protected:
204  // Can be only subclassed.
205  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
206public:
207  // Return the non-pre/post incrementing version of 'Opc'. Return 0
208  // if there is not such an opcode.
209  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
210
211  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
212                                              MachineBasicBlock::iterator &MBBI,
213                                              LiveVariables *LV) const;
214
215  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
216  const ARMSubtarget &getSubtarget() const { return Subtarget; }
217
218  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
219                                 MachineBasicBlock::iterator MI,
220                                 const std::vector<CalleeSavedInfo> &CSI,
221                                 const TargetRegisterInfo *TRI) const;
222
223  // Branch analysis.
224  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
225                             MachineBasicBlock *&FBB,
226                             SmallVectorImpl<MachineOperand> &Cond,
227                             bool AllowModify = false) const;
228  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
229  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
230                                MachineBasicBlock *FBB,
231                                const SmallVectorImpl<MachineOperand> &Cond,
232                                DebugLoc DL) const;
233
234  virtual
235  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
236
237  // Predication support.
238  bool isPredicated(const MachineInstr *MI) const {
239    int PIdx = MI->findFirstPredOperandIdx();
240    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
241  }
242
243  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
244    int PIdx = MI->findFirstPredOperandIdx();
245    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
246                      : ARMCC::AL;
247  }
248
249  virtual
250  bool PredicateInstruction(MachineInstr *MI,
251                            const SmallVectorImpl<MachineOperand> &Pred) const;
252
253  virtual
254  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
255                         const SmallVectorImpl<MachineOperand> &Pred2) const;
256
257  virtual bool DefinesPredicate(MachineInstr *MI,
258                                std::vector<MachineOperand> &Pred) const;
259
260  virtual bool isPredicable(MachineInstr *MI) const;
261
262  /// GetInstSize - Returns the size of the specified MachineInstr.
263  ///
264  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
265
266  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
267                                       int &FrameIndex) const;
268  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
269                                      int &FrameIndex) const;
270
271  virtual void copyPhysReg(MachineBasicBlock &MBB,
272                           MachineBasicBlock::iterator I, DebugLoc DL,
273                           unsigned DestReg, unsigned SrcReg,
274                           bool KillSrc) const;
275
276  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
277                                   MachineBasicBlock::iterator MBBI,
278                                   unsigned SrcReg, bool isKill, int FrameIndex,
279                                   const TargetRegisterClass *RC,
280                                   const TargetRegisterInfo *TRI) const;
281
282  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
283                                    MachineBasicBlock::iterator MBBI,
284                                    unsigned DestReg, int FrameIndex,
285                                    const TargetRegisterClass *RC,
286                                    const TargetRegisterInfo *TRI) const;
287
288  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
289                                                 int FrameIx,
290                                                 uint64_t Offset,
291                                                 const MDNode *MDPtr,
292                                                 DebugLoc DL) const;
293
294  virtual void reMaterialize(MachineBasicBlock &MBB,
295                             MachineBasicBlock::iterator MI,
296                             unsigned DestReg, unsigned SubIdx,
297                             const MachineInstr *Orig,
298                             const TargetRegisterInfo &TRI) const;
299
300  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
301
302  virtual bool produceSameValue(const MachineInstr *MI0,
303                                const MachineInstr *MI1) const;
304
305  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
306  /// determine if two loads are loading from the same base address. It should
307  /// only return true if the base pointers are the same and the only
308  /// differences between the two addresses is the offset. It also returns the
309  /// offsets by reference.
310  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
311                                       int64_t &Offset1, int64_t &Offset2)const;
312
313  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
314  /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
315  /// be scheduled togther. On some targets if two loads are loading from
316  /// addresses in the same cache line, it's better if they are scheduled
317  /// together. This function takes two integers that represent the load offsets
318  /// from the common base address. It returns true if it decides it's desirable
319  /// to schedule the two loads together. "NumLoads" is the number of loads that
320  /// have already been scheduled after Load1.
321  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
322                                       int64_t Offset1, int64_t Offset2,
323                                       unsigned NumLoads) const;
324
325  virtual bool isSchedulingBoundary(const MachineInstr *MI,
326                                    const MachineBasicBlock *MBB,
327                                    const MachineFunction &MF) const;
328
329  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
330                                   unsigned NumInstrs) const;
331
332  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
333                                   MachineBasicBlock &FMBB,unsigned NumF) const;
334
335  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
336                                         unsigned NumInstrs) const {
337    return NumInstrs && NumInstrs == 1;
338  }
339};
340
341static inline
342const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
343  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
344}
345
346static inline
347const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
348  return MIB.addReg(0);
349}
350
351static inline
352const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
353                                          bool isDead = false) {
354  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
355}
356
357static inline
358const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
359  return MIB.addReg(0);
360}
361
362static inline
363bool isUncondBranchOpcode(int Opc) {
364  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
365}
366
367static inline
368bool isCondBranchOpcode(int Opc) {
369  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
370}
371
372static inline
373bool isJumpTableBranchOpcode(int Opc) {
374  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
375    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
376}
377
378static inline
379bool isIndirectBranchOpcode(int Opc) {
380  return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
381}
382
383/// getInstrPredicate - If instruction is predicated, returns its predicate
384/// condition, otherwise returns AL. It also returns the condition code
385/// register by reference.
386ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
387
388int getMatchingCondBranchOpcode(int Opc);
389
390/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
391/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
392/// code.
393void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
394                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
395                             unsigned DestReg, unsigned BaseReg, int NumBytes,
396                             ARMCC::CondCodes Pred, unsigned PredReg,
397                             const ARMBaseInstrInfo &TII);
398
399void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
400                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
401                            unsigned DestReg, unsigned BaseReg, int NumBytes,
402                            ARMCC::CondCodes Pred, unsigned PredReg,
403                            const ARMBaseInstrInfo &TII);
404
405
406/// rewriteARMFrameIndex / rewriteT2FrameIndex -
407/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
408/// offset could not be handled directly in MI, and return the left-over
409/// portion by reference.
410bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
411                          unsigned FrameReg, int &Offset,
412                          const ARMBaseInstrInfo &TII);
413
414bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
415                         unsigned FrameReg, int &Offset,
416                         const ARMBaseInstrInfo &TII);
417
418} // End llvm namespace
419
420#endif
421