ARMBaseInstrInfo.h revision 2860b7ea3a1d60213ee7228bd274bc4f8b170772 
1//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/ADT/DenseMap.h"
21#include "llvm/ADT/SmallSet.h"
22
23#define GET_INSTRINFO_HEADER
24#include "ARMGenInstrInfo.inc"
25
26namespace llvm {
27  class ARMSubtarget;
28  class ARMBaseRegisterInfo;
29
30class ARMBaseInstrInfo : public ARMGenInstrInfo {
31  const ARMSubtarget &Subtarget;
32
33protected:
34  // Can be only subclassed.
35  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
36
37public:
38  // Return whether the target has an explicit NOP encoding.
39  bool hasNOP() const;
40
41  // Return the non-pre/post incrementing version of 'Opc'. Return 0
42  // if there is not such an opcode.
43  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
44
45  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
46                                              MachineBasicBlock::iterator &MBBI,
47                                              LiveVariables *LV) const;
48
49  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
50  const ARMSubtarget &getSubtarget() const { return Subtarget; }
51
52  ScheduleHazardRecognizer *
53  CreateTargetHazardRecognizer(const TargetMachine *TM,
54                               const ScheduleDAG *DAG) const;
55
56  ScheduleHazardRecognizer *
57  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
58                                     const ScheduleDAG *DAG) const;
59
60  // Branch analysis.
61  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
62                             MachineBasicBlock *&FBB,
63                             SmallVectorImpl<MachineOperand> &Cond,
64                             bool AllowModify = false) const;
65  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67                                MachineBasicBlock *FBB,
68                                const SmallVectorImpl<MachineOperand> &Cond,
69                                DebugLoc DL) const;
70
71  virtual
72  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
73
74  // Predication support.
75  bool isPredicated(const MachineInstr *MI) const;
76
77  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78    int PIdx = MI->findFirstPredOperandIdx();
79    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
80                      : ARMCC::AL;
81  }
82
83  virtual
84  bool PredicateInstruction(MachineInstr *MI,
85                            const SmallVectorImpl<MachineOperand> &Pred) const;
86
87  virtual
88  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89                         const SmallVectorImpl<MachineOperand> &Pred2) const;
90
91  virtual bool DefinesPredicate(MachineInstr *MI,
92                                std::vector<MachineOperand> &Pred) const;
93
94  virtual bool isPredicable(MachineInstr *MI) const;
95
96  /// GetInstSize - Returns the size of the specified MachineInstr.
97  ///
98  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
99
100  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101                                       int &FrameIndex) const;
102  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103                                      int &FrameIndex) const;
104  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
105                                             int &FrameIndex) const;
106  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
107                                            int &FrameIndex) const;
108
109  virtual void copyPhysReg(MachineBasicBlock &MBB,
110                           MachineBasicBlock::iterator I, DebugLoc DL,
111                           unsigned DestReg, unsigned SrcReg,
112                           bool KillSrc) const;
113
114  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
115                                   MachineBasicBlock::iterator MBBI,
116                                   unsigned SrcReg, bool isKill, int FrameIndex,
117                                   const TargetRegisterClass *RC,
118                                   const TargetRegisterInfo *TRI) const;
119
120  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
121                                    MachineBasicBlock::iterator MBBI,
122                                    unsigned DestReg, int FrameIndex,
123                                    const TargetRegisterClass *RC,
124                                    const TargetRegisterInfo *TRI) const;
125
126  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
127
128  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
129                                                 int FrameIx,
130                                                 uint64_t Offset,
131                                                 const MDNode *MDPtr,
132                                                 DebugLoc DL) const;
133
134  virtual void reMaterialize(MachineBasicBlock &MBB,
135                             MachineBasicBlock::iterator MI,
136                             unsigned DestReg, unsigned SubIdx,
137                             const MachineInstr *Orig,
138                             const TargetRegisterInfo &TRI) const;
139
140  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
141
142  MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
143
144  virtual bool produceSameValue(const MachineInstr *MI0,
145                                const MachineInstr *MI1,
146                                const MachineRegisterInfo *MRI) const;
147
148  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
149  /// determine if two loads are loading from the same base address. It should
150  /// only return true if the base pointers are the same and the only
151  /// differences between the two addresses is the offset. It also returns the
152  /// offsets by reference.
153  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
154                                       int64_t &Offset1, int64_t &Offset2)const;
155
156  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
157  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
158  /// should be scheduled togther. On some targets if two loads are loading from
159  /// addresses in the same cache line, it's better if they are scheduled
160  /// together. This function takes two integers that represent the load offsets
161  /// from the common base address. It returns true if it decides it's desirable
162  /// to schedule the two loads together. "NumLoads" is the number of loads that
163  /// have already been scheduled after Load1.
164  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
165                                       int64_t Offset1, int64_t Offset2,
166                                       unsigned NumLoads) const;
167
168  virtual bool isSchedulingBoundary(const MachineInstr *MI,
169                                    const MachineBasicBlock *MBB,
170                                    const MachineFunction &MF) const;
171
172  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
173                                   unsigned NumCycles, unsigned ExtraPredCycles,
174                                   const BranchProbability &Probability) const;
175
176  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
177                                   unsigned NumT, unsigned ExtraT,
178                                   MachineBasicBlock &FMBB,
179                                   unsigned NumF, unsigned ExtraF,
180                                   const BranchProbability &Probability) const;
181
182  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
183                                         unsigned NumCycles,
184                                         const BranchProbability
185                                           &Probability) const {
186    return NumCycles == 1;
187  }
188
189  /// analyzeCompare - For a comparison instruction, return the source registers
190  /// in SrcReg and SrcReg2 if having two register operands, and the value it
191  /// compares against in CmpValue. Return true if the comparison instruction
192  /// can be analyzed.
193  virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
194                              unsigned &SrcReg2, int &CmpMask,
195                              int &CmpValue) const;
196
197  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
198  /// that we can remove a "comparison with zero"; Remove a redundant CMP
199  /// instruction if the flags can be updated in the same way by an earlier
200  /// instruction such as SUB.
201  virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
202                                    unsigned SrcReg2, int CmpMask, int CmpValue,
203                                    const MachineRegisterInfo *MRI) const;
204
205  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
206  /// instruction, try to fold the immediate into the use instruction.
207  virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
208                             unsigned Reg, MachineRegisterInfo *MRI) const;
209
210  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
211                                  const MachineInstr *MI) const;
212
213  virtual
214  int getOperandLatency(const InstrItineraryData *ItinData,
215                        const MachineInstr *DefMI, unsigned DefIdx,
216                        const MachineInstr *UseMI, unsigned UseIdx) const;
217  virtual
218  int getOperandLatency(const InstrItineraryData *ItinData,
219                        SDNode *DefNode, unsigned DefIdx,
220                        SDNode *UseNode, unsigned UseIdx) const;
221
222  virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
223                                    const MachineInstr *DefMI, unsigned DefIdx,
224                                    const MachineInstr *DepMI) const;
225
226  /// VFP/NEON execution domains.
227  std::pair<uint16_t, uint16_t>
228  getExecutionDomain(const MachineInstr *MI) const;
229  void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
230
231private:
232  unsigned getInstBundleLength(const MachineInstr *MI) const;
233
234  int getVLDMDefCycle(const InstrItineraryData *ItinData,
235                      const MCInstrDesc &DefMCID,
236                      unsigned DefClass,
237                      unsigned DefIdx, unsigned DefAlign) const;
238  int getLDMDefCycle(const InstrItineraryData *ItinData,
239                     const MCInstrDesc &DefMCID,
240                     unsigned DefClass,
241                     unsigned DefIdx, unsigned DefAlign) const;
242  int getVSTMUseCycle(const InstrItineraryData *ItinData,
243                      const MCInstrDesc &UseMCID,
244                      unsigned UseClass,
245                      unsigned UseIdx, unsigned UseAlign) const;
246  int getSTMUseCycle(const InstrItineraryData *ItinData,
247                     const MCInstrDesc &UseMCID,
248                     unsigned UseClass,
249                     unsigned UseIdx, unsigned UseAlign) const;
250  int getOperandLatency(const InstrItineraryData *ItinData,
251                        const MCInstrDesc &DefMCID,
252                        unsigned DefIdx, unsigned DefAlign,
253                        const MCInstrDesc &UseMCID,
254                        unsigned UseIdx, unsigned UseAlign) const;
255
256  unsigned getInstrLatency(const InstrItineraryData *ItinData,
257                           const MachineInstr *MI,
258                           unsigned *PredCost = 0) const;
259
260  int getInstrLatency(const InstrItineraryData *ItinData,
261                      SDNode *Node) const;
262
263  bool hasHighOperandLatency(const InstrItineraryData *ItinData,
264                             const MachineRegisterInfo *MRI,
265                             const MachineInstr *DefMI, unsigned DefIdx,
266                             const MachineInstr *UseMI, unsigned UseIdx) const;
267  bool hasLowDefLatency(const InstrItineraryData *ItinData,
268                        const MachineInstr *DefMI, unsigned DefIdx) const;
269
270  /// verifyInstruction - Perform target specific instruction verification.
271  bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
272
273private:
274  /// Modeling special VFP / NEON fp MLA / MLS hazards.
275
276  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
277  /// MLx table.
278  DenseMap<unsigned, unsigned> MLxEntryMap;
279
280  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
281  /// stalls when scheduled together with fp MLA / MLS opcodes.
282  SmallSet<unsigned, 16> MLxHazardOpcodes;
283
284public:
285  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
286  /// instruction.
287  bool isFpMLxInstruction(unsigned Opcode) const {
288    return MLxEntryMap.count(Opcode);
289  }
290
291  /// isFpMLxInstruction - This version also returns the multiply opcode and the
292  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
293  /// the MLX instructions with an extra lane operand.
294  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
295                          unsigned &AddSubOpc, bool &NegAcc,
296                          bool &HasLane) const;
297
298  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
299  /// will cause stalls when scheduled after (within 4-cycle window) a fp
300  /// MLA / MLS instruction.
301  bool canCauseFpMLxStall(unsigned Opcode) const {
302    return MLxHazardOpcodes.count(Opcode);
303  }
304};
305
306static inline
307const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
308  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
309}
310
311static inline
312const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
313  return MIB.addReg(0);
314}
315
316static inline
317const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
318                                          bool isDead = false) {
319  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
320}
321
322static inline
323const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
324  return MIB.addReg(0);
325}
326
327static inline
328bool isUncondBranchOpcode(int Opc) {
329  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
330}
331
332static inline
333bool isCondBranchOpcode(int Opc) {
334  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
335}
336
337static inline
338bool isJumpTableBranchOpcode(int Opc) {
339  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
340    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
341}
342
343static inline
344bool isIndirectBranchOpcode(int Opc) {
345  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
346}
347
348/// getInstrPredicate - If instruction is predicated, returns its predicate
349/// condition, otherwise returns AL. It also returns the condition code
350/// register by reference.
351ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
352
353int getMatchingCondBranchOpcode(int Opc);
354
355/// Determine if MI can be folded into an ARM MOVCC instruction, and return the
356/// opcode of the SSA instruction representing the conditional MI.
357unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
358                                  MachineInstr *&MI,
359                                  const MachineRegisterInfo &MRI);
360
361/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
362/// the instruction is encoded with an 'S' bit is determined by the optional
363/// CPSR def operand.
364unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
365
366/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
367/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
368/// code.
369void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
370                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
371                             unsigned DestReg, unsigned BaseReg, int NumBytes,
372                             ARMCC::CondCodes Pred, unsigned PredReg,
373                             const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
374
375void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
376                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
377                            unsigned DestReg, unsigned BaseReg, int NumBytes,
378                            ARMCC::CondCodes Pred, unsigned PredReg,
379                            const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
380void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
381                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
382                               unsigned DestReg, unsigned BaseReg,
383                               int NumBytes, const TargetInstrInfo &TII,
384                               const ARMBaseRegisterInfo& MRI,
385                               unsigned MIFlags = 0);
386
387
388/// rewriteARMFrameIndex / rewriteT2FrameIndex -
389/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
390/// offset could not be handled directly in MI, and return the left-over
391/// portion by reference.
392bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
393                          unsigned FrameReg, int &Offset,
394                          const ARMBaseInstrInfo &TII);
395
396bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
397                         unsigned FrameReg, int &Offset,
398                         const ARMBaseInstrInfo &TII);
399
400} // End llvm namespace
401
402#endif
403