ARMBaseInstrInfo.h revision 48575f6ea7d5cd21ab29ca370f58fcf9ca31400b 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/ADT/DenseMap.h"
21#include "llvm/ADT/SmallSet.h"
22
23namespace llvm {
24  class ARMSubtarget;
25  class ARMBaseRegisterInfo;
26
27/// ARMII - This namespace holds all of the target specific flags that
28/// instruction info tracks.
29///
30namespace ARMII {
31  enum {
32    //===------------------------------------------------------------------===//
33    // Instruction Flags.
34
35    //===------------------------------------------------------------------===//
36    // This four-bit field describes the addressing mode used.
37
38    AddrModeMask  = 0x1f,
39    AddrModeNone    = 0,
40    AddrMode1       = 1,
41    AddrMode2       = 2,
42    AddrMode3       = 3,
43    AddrMode4       = 4,
44    AddrMode5       = 5,
45    AddrMode6       = 6,
46    AddrModeT1_1    = 7,
47    AddrModeT1_2    = 8,
48    AddrModeT1_4    = 9,
49    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
50    AddrModeT2_i12  = 11,
51    AddrModeT2_i8   = 12,
52    AddrModeT2_so   = 13,
53    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
54    AddrModeT2_i8s4 = 15, // i8 * 4
55    AddrMode_i12    = 16,
56
57    // Size* - Flags to keep track of the size of an instruction.
58    SizeShift     = 5,
59    SizeMask      = 7 << SizeShift,
60    SizeSpecial   = 1,   // 0 byte pseudo or special case.
61    Size8Bytes    = 2,
62    Size4Bytes    = 3,
63    Size2Bytes    = 4,
64
65    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
66    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
67    IndexModeShift = 8,
68    IndexModeMask  = 3 << IndexModeShift,
69    IndexModePre   = 1,
70    IndexModePost  = 2,
71    IndexModeUpd   = 3,
72
73    //===------------------------------------------------------------------===//
74    // Instruction encoding formats.
75    //
76    FormShift     = 10,
77    FormMask      = 0x3f << FormShift,
78
79    // Pseudo instructions
80    Pseudo        = 0  << FormShift,
81
82    // Multiply instructions
83    MulFrm        = 1  << FormShift,
84
85    // Branch instructions
86    BrFrm         = 2  << FormShift,
87    BrMiscFrm     = 3  << FormShift,
88
89    // Data Processing instructions
90    DPFrm         = 4  << FormShift,
91    DPSoRegFrm    = 5  << FormShift,
92
93    // Load and Store
94    LdFrm         = 6  << FormShift,
95    StFrm         = 7  << FormShift,
96    LdMiscFrm     = 8  << FormShift,
97    StMiscFrm     = 9  << FormShift,
98    LdStMulFrm    = 10 << FormShift,
99
100    LdStExFrm     = 11 << FormShift,
101
102    // Miscellaneous arithmetic instructions
103    ArithMiscFrm  = 12 << FormShift,
104    SatFrm        = 13 << FormShift,
105
106    // Extend instructions
107    ExtFrm        = 14 << FormShift,
108
109    // VFP formats
110    VFPUnaryFrm   = 15 << FormShift,
111    VFPBinaryFrm  = 16 << FormShift,
112    VFPConv1Frm   = 17 << FormShift,
113    VFPConv2Frm   = 18 << FormShift,
114    VFPConv3Frm   = 19 << FormShift,
115    VFPConv4Frm   = 20 << FormShift,
116    VFPConv5Frm   = 21 << FormShift,
117    VFPLdStFrm    = 22 << FormShift,
118    VFPLdStMulFrm = 23 << FormShift,
119    VFPMiscFrm    = 24 << FormShift,
120
121    // Thumb format
122    ThumbFrm      = 25 << FormShift,
123
124    // Miscelleaneous format
125    MiscFrm       = 26 << FormShift,
126
127    // NEON formats
128    NGetLnFrm     = 27 << FormShift,
129    NSetLnFrm     = 28 << FormShift,
130    NDupFrm       = 29 << FormShift,
131    NLdStFrm      = 30 << FormShift,
132    N1RegModImmFrm= 31 << FormShift,
133    N2RegFrm      = 32 << FormShift,
134    NVCVTFrm      = 33 << FormShift,
135    NVDupLnFrm    = 34 << FormShift,
136    N2RegVShLFrm  = 35 << FormShift,
137    N2RegVShRFrm  = 36 << FormShift,
138    N3RegFrm      = 37 << FormShift,
139    N3RegVShFrm   = 38 << FormShift,
140    NVExtFrm      = 39 << FormShift,
141    NVMulSLFrm    = 40 << FormShift,
142    NVTBLFrm      = 41 << FormShift,
143
144    //===------------------------------------------------------------------===//
145    // Misc flags.
146
147    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
148    // it doesn't have a Rn operand.
149    UnaryDP       = 1 << 16,
150
151    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
152    // a 16-bit Thumb instruction if certain conditions are met.
153    Xform16Bit    = 1 << 17,
154
155    //===------------------------------------------------------------------===//
156    // Code domain.
157    DomainShift   = 18,
158    DomainMask    = 3 << DomainShift,
159    DomainGeneral = 0 << DomainShift,
160    DomainVFP     = 1 << DomainShift,
161    DomainNEON    = 2 << DomainShift,
162
163    //===------------------------------------------------------------------===//
164    // Field shifts - such shifts are used to set field while generating
165    // machine instructions.
166    //
167    // FIXME: This list will need adjusting/fixing as the MC code emitter
168    // takes shape and the ARMCodeEmitter.cpp bits go away.
169    ShiftTypeShift = 4,
170
171    M_BitShift     = 5,
172    ShiftImmShift  = 5,
173    ShiftShift     = 7,
174    N_BitShift     = 7,
175    ImmHiShift     = 8,
176    SoRotImmShift  = 8,
177    RegRsShift     = 8,
178    ExtRotImmShift = 10,
179    RegRdLoShift   = 12,
180    RegRdShift     = 12,
181    RegRdHiShift   = 16,
182    RegRnShift     = 16,
183    S_BitShift     = 20,
184    W_BitShift     = 21,
185    AM3_I_BitShift = 22,
186    D_BitShift     = 22,
187    U_BitShift     = 23,
188    P_BitShift     = 24,
189    I_BitShift     = 25,
190    CondShift      = 28
191  };
192}
193
194class ARMBaseInstrInfo : public TargetInstrInfoImpl {
195  const ARMSubtarget &Subtarget;
196
197protected:
198  // Can be only subclassed.
199  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
200
201public:
202  // Return the non-pre/post incrementing version of 'Opc'. Return 0
203  // if there is not such an opcode.
204  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
205
206  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
207                                              MachineBasicBlock::iterator &MBBI,
208                                              LiveVariables *LV) const;
209
210  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
211  const ARMSubtarget &getSubtarget() const { return Subtarget; }
212
213  ScheduleHazardRecognizer *
214  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const;
215
216  // Branch analysis.
217  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
218                             MachineBasicBlock *&FBB,
219                             SmallVectorImpl<MachineOperand> &Cond,
220                             bool AllowModify = false) const;
221  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
222  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
223                                MachineBasicBlock *FBB,
224                                const SmallVectorImpl<MachineOperand> &Cond,
225                                DebugLoc DL) const;
226
227  virtual
228  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
229
230  // Predication support.
231  bool isPredicated(const MachineInstr *MI) const {
232    int PIdx = MI->findFirstPredOperandIdx();
233    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
234  }
235
236  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
237    int PIdx = MI->findFirstPredOperandIdx();
238    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
239                      : ARMCC::AL;
240  }
241
242  virtual
243  bool PredicateInstruction(MachineInstr *MI,
244                            const SmallVectorImpl<MachineOperand> &Pred) const;
245
246  virtual
247  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
248                         const SmallVectorImpl<MachineOperand> &Pred2) const;
249
250  virtual bool DefinesPredicate(MachineInstr *MI,
251                                std::vector<MachineOperand> &Pred) const;
252
253  virtual bool isPredicable(MachineInstr *MI) const;
254
255  /// GetInstSize - Returns the size of the specified MachineInstr.
256  ///
257  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
258
259  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
260                                       int &FrameIndex) const;
261  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
262                                      int &FrameIndex) const;
263
264  virtual void copyPhysReg(MachineBasicBlock &MBB,
265                           MachineBasicBlock::iterator I, DebugLoc DL,
266                           unsigned DestReg, unsigned SrcReg,
267                           bool KillSrc) const;
268
269  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
270                                   MachineBasicBlock::iterator MBBI,
271                                   unsigned SrcReg, bool isKill, int FrameIndex,
272                                   const TargetRegisterClass *RC,
273                                   const TargetRegisterInfo *TRI) const;
274
275  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
276                                    MachineBasicBlock::iterator MBBI,
277                                    unsigned DestReg, int FrameIndex,
278                                    const TargetRegisterClass *RC,
279                                    const TargetRegisterInfo *TRI) const;
280
281  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
282                                                 int FrameIx,
283                                                 uint64_t Offset,
284                                                 const MDNode *MDPtr,
285                                                 DebugLoc DL) const;
286
287  virtual void reMaterialize(MachineBasicBlock &MBB,
288                             MachineBasicBlock::iterator MI,
289                             unsigned DestReg, unsigned SubIdx,
290                             const MachineInstr *Orig,
291                             const TargetRegisterInfo &TRI) const;
292
293  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
294
295  virtual bool produceSameValue(const MachineInstr *MI0,
296                                const MachineInstr *MI1) const;
297
298  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
299  /// determine if two loads are loading from the same base address. It should
300  /// only return true if the base pointers are the same and the only
301  /// differences between the two addresses is the offset. It also returns the
302  /// offsets by reference.
303  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
304                                       int64_t &Offset1, int64_t &Offset2)const;
305
306  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
307  /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
308  /// be scheduled togther. On some targets if two loads are loading from
309  /// addresses in the same cache line, it's better if they are scheduled
310  /// together. This function takes two integers that represent the load offsets
311  /// from the common base address. It returns true if it decides it's desirable
312  /// to schedule the two loads together. "NumLoads" is the number of loads that
313  /// have already been scheduled after Load1.
314  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
315                                       int64_t Offset1, int64_t Offset2,
316                                       unsigned NumLoads) const;
317
318  virtual bool isSchedulingBoundary(const MachineInstr *MI,
319                                    const MachineBasicBlock *MBB,
320                                    const MachineFunction &MF) const;
321
322  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
323                                   unsigned NumCyles, unsigned ExtraPredCycles,
324                                   float Prob, float Confidence) const;
325
326  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
327                                   unsigned NumT, unsigned ExtraT,
328                                   MachineBasicBlock &FMBB,
329                                   unsigned NumF, unsigned ExtraF,
330                                   float Probability, float Confidence) const;
331
332  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
333                                         unsigned NumCyles,
334                                         float Probability,
335                                         float Confidence) const {
336    return NumCyles == 1;
337  }
338
339  /// AnalyzeCompare - For a comparison instruction, return the source register
340  /// in SrcReg and the value it compares against in CmpValue. Return true if
341  /// the comparison instruction can be analyzed.
342  virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
343                              int &CmpMask, int &CmpValue) const;
344
345  /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
346  /// that we can remove a "comparison with zero".
347  virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
348                                    int CmpMask, int CmpValue,
349                                    const MachineRegisterInfo *MRI) const;
350
351  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
352  /// instruction, try to fold the immediate into the use instruction.
353  virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
354                             unsigned Reg, MachineRegisterInfo *MRI) const;
355
356  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
357                                  const MachineInstr *MI) const;
358
359  virtual
360  int getOperandLatency(const InstrItineraryData *ItinData,
361                        const MachineInstr *DefMI, unsigned DefIdx,
362                        const MachineInstr *UseMI, unsigned UseIdx) const;
363  virtual
364  int getOperandLatency(const InstrItineraryData *ItinData,
365                        SDNode *DefNode, unsigned DefIdx,
366                        SDNode *UseNode, unsigned UseIdx) const;
367private:
368  int getVLDMDefCycle(const InstrItineraryData *ItinData,
369                      const TargetInstrDesc &DefTID,
370                      unsigned DefClass,
371                      unsigned DefIdx, unsigned DefAlign) const;
372  int getLDMDefCycle(const InstrItineraryData *ItinData,
373                     const TargetInstrDesc &DefTID,
374                     unsigned DefClass,
375                     unsigned DefIdx, unsigned DefAlign) const;
376  int getVSTMUseCycle(const InstrItineraryData *ItinData,
377                      const TargetInstrDesc &UseTID,
378                      unsigned UseClass,
379                      unsigned UseIdx, unsigned UseAlign) const;
380  int getSTMUseCycle(const InstrItineraryData *ItinData,
381                     const TargetInstrDesc &UseTID,
382                     unsigned UseClass,
383                     unsigned UseIdx, unsigned UseAlign) const;
384  int getOperandLatency(const InstrItineraryData *ItinData,
385                        const TargetInstrDesc &DefTID,
386                        unsigned DefIdx, unsigned DefAlign,
387                        const TargetInstrDesc &UseTID,
388                        unsigned UseIdx, unsigned UseAlign) const;
389
390  int getInstrLatency(const InstrItineraryData *ItinData,
391                      const MachineInstr *MI, unsigned *PredCost = 0) const;
392
393  int getInstrLatency(const InstrItineraryData *ItinData,
394                      SDNode *Node) const;
395
396  bool hasHighOperandLatency(const InstrItineraryData *ItinData,
397                             const MachineRegisterInfo *MRI,
398                             const MachineInstr *DefMI, unsigned DefIdx,
399                             const MachineInstr *UseMI, unsigned UseIdx) const;
400  bool hasLowDefLatency(const InstrItineraryData *ItinData,
401                        const MachineInstr *DefMI, unsigned DefIdx) const;
402
403private:
404  /// Modeling special VFP / NEON fp MLA / MLS hazards.
405
406  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
407  /// MLx table.
408  DenseMap<unsigned, unsigned> MLxEntryMap;
409
410  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
411  /// stalls when scheduled together with fp MLA / MLS opcodes.
412  SmallSet<unsigned, 16> MLxHazardOpcodes;
413
414public:
415  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
416  /// instruction.
417  bool isFpMLxInstruction(unsigned Opcode) const {
418    return MLxEntryMap.count(Opcode);
419  }
420
421  /// isFpMLxInstruction - This version also returns the multiply opcode and the
422  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
423  /// the MLX instructions with an extra lane operand.
424  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
425                          unsigned &AddSubOpc, bool &NegAcc,
426                          bool &HasLane) const;
427
428  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
429  /// will cause stalls when scheduled after (within 4-cycle window) a fp
430  /// MLA / MLS instruction.
431  bool canCauseFpMLxStall(unsigned Opcode) const {
432    return MLxHazardOpcodes.count(Opcode);
433  }
434};
435
436static inline
437const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
438  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
439}
440
441static inline
442const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
443  return MIB.addReg(0);
444}
445
446static inline
447const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
448                                          bool isDead = false) {
449  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
450}
451
452static inline
453const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
454  return MIB.addReg(0);
455}
456
457static inline
458bool isUncondBranchOpcode(int Opc) {
459  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
460}
461
462static inline
463bool isCondBranchOpcode(int Opc) {
464  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
465}
466
467static inline
468bool isJumpTableBranchOpcode(int Opc) {
469  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
470    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
471}
472
473static inline
474bool isIndirectBranchOpcode(int Opc) {
475  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
476}
477
478/// getInstrPredicate - If instruction is predicated, returns its predicate
479/// condition, otherwise returns AL. It also returns the condition code
480/// register by reference.
481ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
482
483int getMatchingCondBranchOpcode(int Opc);
484
485/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
486/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
487/// code.
488void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
489                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
490                             unsigned DestReg, unsigned BaseReg, int NumBytes,
491                             ARMCC::CondCodes Pred, unsigned PredReg,
492                             const ARMBaseInstrInfo &TII);
493
494void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
495                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
496                            unsigned DestReg, unsigned BaseReg, int NumBytes,
497                            ARMCC::CondCodes Pred, unsigned PredReg,
498                            const ARMBaseInstrInfo &TII);
499void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
500                               MachineBasicBlock::iterator &MBBI,
501                               unsigned DestReg, unsigned BaseReg,
502                               int NumBytes, const TargetInstrInfo &TII,
503                               const ARMBaseRegisterInfo& MRI,
504                               DebugLoc dl);
505
506
507/// rewriteARMFrameIndex / rewriteT2FrameIndex -
508/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
509/// offset could not be handled directly in MI, and return the left-over
510/// portion by reference.
511bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
512                          unsigned FrameReg, int &Offset,
513                          const ARMBaseInstrInfo &TII);
514
515bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
516                         unsigned FrameReg, int &Offset,
517                         const ARMBaseInstrInfo &TII);
518
519} // End llvm namespace
520
521#endif
522