ARMBaseInstrInfo.h revision 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "ARMRegisterInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22namespace llvm {
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28  enum {
29    //===------------------------------------------------------------------===//
30    // Instruction Flags.
31
32    //===------------------------------------------------------------------===//
33    // This four-bit field describes the addressing mode used.
34
35    AddrModeMask  = 0xf,
36    AddrModeNone    = 0,
37    AddrMode1       = 1,
38    AddrMode2       = 2,
39    AddrMode3       = 3,
40    AddrMode4       = 4,
41    AddrMode5       = 5,
42    AddrMode6       = 6,
43    AddrModeT1_1    = 7,
44    AddrModeT1_2    = 8,
45    AddrModeT1_4    = 9,
46    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
47    AddrModeT2_i12  = 11,
48    AddrModeT2_i8   = 12,
49    AddrModeT2_so   = 13,
50    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
51    AddrModeT2_i8s4 = 15, // i8 * 4
52
53    // Size* - Flags to keep track of the size of an instruction.
54    SizeShift     = 4,
55    SizeMask      = 7 << SizeShift,
56    SizeSpecial   = 1,   // 0 byte pseudo or special case.
57    Size8Bytes    = 2,
58    Size4Bytes    = 3,
59    Size2Bytes    = 4,
60
61    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
62    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
63    IndexModeShift = 7,
64    IndexModeMask  = 3 << IndexModeShift,
65    IndexModePre   = 1,
66    IndexModePost  = 2,
67    IndexModeUpd   = 3,
68
69    //===------------------------------------------------------------------===//
70    // Instruction encoding formats.
71    //
72    FormShift     = 9,
73    FormMask      = 0x3f << FormShift,
74
75    // Pseudo instructions
76    Pseudo        = 0  << FormShift,
77
78    // Multiply instructions
79    MulFrm        = 1  << FormShift,
80
81    // Branch instructions
82    BrFrm         = 2  << FormShift,
83    BrMiscFrm     = 3  << FormShift,
84
85    // Data Processing instructions
86    DPFrm         = 4  << FormShift,
87    DPSoRegFrm    = 5  << FormShift,
88
89    // Load and Store
90    LdFrm         = 6  << FormShift,
91    StFrm         = 7  << FormShift,
92    LdMiscFrm     = 8  << FormShift,
93    StMiscFrm     = 9  << FormShift,
94    LdStMulFrm    = 10 << FormShift,
95
96    LdStExFrm     = 11 << FormShift,
97
98    // Miscellaneous arithmetic instructions
99    ArithMiscFrm  = 12 << FormShift,
100
101    // Extend instructions
102    ExtFrm        = 13 << FormShift,
103
104    // VFP formats
105    VFPUnaryFrm   = 14 << FormShift,
106    VFPBinaryFrm  = 15 << FormShift,
107    VFPConv1Frm   = 16 << FormShift,
108    VFPConv2Frm   = 17 << FormShift,
109    VFPConv3Frm   = 18 << FormShift,
110    VFPConv4Frm   = 19 << FormShift,
111    VFPConv5Frm   = 20 << FormShift,
112    VFPLdStFrm    = 21 << FormShift,
113    VFPLdStMulFrm = 22 << FormShift,
114    VFPMiscFrm    = 23 << FormShift,
115
116    // Thumb format
117    ThumbFrm      = 24 << FormShift,
118
119    // NEON formats
120    NEONFrm       = 25 << FormShift,
121    NEONGetLnFrm  = 26 << FormShift,
122    NEONSetLnFrm  = 27 << FormShift,
123    NEONDupFrm    = 28 << FormShift,
124    NLdStFrm      = 31 << FormShift,
125    N1RegModImmFrm= 32 << FormShift,
126    N2RegFrm      = 33 << FormShift,
127    NVCVTFrm      = 34 << FormShift,
128    NVDupLnFrm    = 35 << FormShift,
129    N2RegVShLFrm  = 36 << FormShift,
130    N2RegVShRFrm  = 37 << FormShift,
131    N3RegFrm      = 38 << FormShift,
132    N3RegVShFrm   = 39 << FormShift,
133    NVExtFrm      = 40 << FormShift,
134    NVMulSLFrm    = 41 << FormShift,
135    NVTBLFrm      = 42 << FormShift,
136
137    //===------------------------------------------------------------------===//
138    // Misc flags.
139
140    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
141    // it doesn't have a Rn operand.
142    UnaryDP       = 1 << 15,
143
144    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
145    // a 16-bit Thumb instruction if certain conditions are met.
146    Xform16Bit    = 1 << 16,
147
148    //===------------------------------------------------------------------===//
149    // Code domain.
150    DomainShift   = 17,
151    DomainMask    = 3 << DomainShift,
152    DomainGeneral = 0 << DomainShift,
153    DomainVFP     = 1 << DomainShift,
154    DomainNEON    = 2 << DomainShift,
155
156    //===------------------------------------------------------------------===//
157    // Field shifts - such shifts are used to set field while generating
158    // machine instructions.
159    M_BitShift     = 5,
160    ShiftImmShift  = 5,
161    ShiftShift     = 7,
162    N_BitShift     = 7,
163    ImmHiShift     = 8,
164    SoRotImmShift  = 8,
165    RegRsShift     = 8,
166    ExtRotImmShift = 10,
167    RegRdLoShift   = 12,
168    RegRdShift     = 12,
169    RegRdHiShift   = 16,
170    RegRnShift     = 16,
171    S_BitShift     = 20,
172    W_BitShift     = 21,
173    AM3_I_BitShift = 22,
174    D_BitShift     = 22,
175    U_BitShift     = 23,
176    P_BitShift     = 24,
177    I_BitShift     = 25,
178    CondShift      = 28
179  };
180
181  /// Target Operand Flag enum.
182  enum TOF {
183    //===------------------------------------------------------------------===//
184    // ARM Specific MachineOperand flags.
185
186    MO_NO_FLAG,
187
188    /// MO_LO16 - On a symbol operand, this represents a relocation containing
189    /// lower 16 bit of the address. Used only via movw instruction.
190    MO_LO16,
191
192    /// MO_HI16 - On a symbol operand, this represents a relocation containing
193    /// higher 16 bit of the address. Used only via movt instruction.
194    MO_HI16
195  };
196}
197
198class ARMBaseInstrInfo : public TargetInstrInfoImpl {
199  const ARMSubtarget& Subtarget;
200protected:
201  // Can be only subclassed.
202  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
203public:
204  // Return the non-pre/post incrementing version of 'Opc'. Return 0
205  // if there is not such an opcode.
206  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
207
208  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
209                                              MachineBasicBlock::iterator &MBBI,
210                                              LiveVariables *LV) const;
211
212  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
213  const ARMSubtarget &getSubtarget() const { return Subtarget; }
214
215  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
216                                 MachineBasicBlock::iterator MI,
217                                 const std::vector<CalleeSavedInfo> &CSI,
218                                 const TargetRegisterInfo *TRI) const;
219
220  // Branch analysis.
221  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
222                             MachineBasicBlock *&FBB,
223                             SmallVectorImpl<MachineOperand> &Cond,
224                             bool AllowModify) const;
225  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
226  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
227                                MachineBasicBlock *FBB,
228                                const SmallVectorImpl<MachineOperand> &Cond,
229                                DebugLoc DL) const;
230
231  virtual
232  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
233
234  // Predication support.
235  bool isPredicated(const MachineInstr *MI) const {
236    int PIdx = MI->findFirstPredOperandIdx();
237    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
238  }
239
240  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
241    int PIdx = MI->findFirstPredOperandIdx();
242    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
243                      : ARMCC::AL;
244  }
245
246  virtual
247  bool PredicateInstruction(MachineInstr *MI,
248                            const SmallVectorImpl<MachineOperand> &Pred) const;
249
250  virtual
251  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
252                         const SmallVectorImpl<MachineOperand> &Pred2) const;
253
254  virtual bool DefinesPredicate(MachineInstr *MI,
255                                std::vector<MachineOperand> &Pred) const;
256
257  virtual bool isPredicable(MachineInstr *MI) const;
258
259  /// GetInstSize - Returns the size of the specified MachineInstr.
260  ///
261  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
262
263  /// Return true if the instruction is a register to register move and return
264  /// the source and dest operands and their sub-register indices by reference.
265  virtual bool isMoveInstr(const MachineInstr &MI,
266                           unsigned &SrcReg, unsigned &DstReg,
267                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
268
269  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
270                                       int &FrameIndex) const;
271  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
272                                      int &FrameIndex) const;
273
274  virtual bool copyRegToReg(MachineBasicBlock &MBB,
275                            MachineBasicBlock::iterator I,
276                            unsigned DestReg, unsigned SrcReg,
277                            const TargetRegisterClass *DestRC,
278                            const TargetRegisterClass *SrcRC,
279                            DebugLoc DL) const;
280
281  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
282                                   MachineBasicBlock::iterator MBBI,
283                                   unsigned SrcReg, bool isKill, int FrameIndex,
284                                   const TargetRegisterClass *RC,
285                                   const TargetRegisterInfo *TRI) const;
286
287  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
288                                    MachineBasicBlock::iterator MBBI,
289                                    unsigned DestReg, int FrameIndex,
290                                    const TargetRegisterClass *RC,
291                                    const TargetRegisterInfo *TRI) const;
292
293  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
294                                                 int FrameIx,
295                                                 uint64_t Offset,
296                                                 const MDNode *MDPtr,
297                                                 DebugLoc DL) const;
298
299  virtual bool canFoldMemoryOperand(const MachineInstr *MI,
300                                    const SmallVectorImpl<unsigned> &Ops) const;
301
302  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
303                                              MachineInstr* MI,
304                                           const SmallVectorImpl<unsigned> &Ops,
305                                              int FrameIndex) const;
306
307  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
308                                              MachineInstr* MI,
309                                           const SmallVectorImpl<unsigned> &Ops,
310                                              MachineInstr* LoadMI) const;
311
312  virtual void reMaterialize(MachineBasicBlock &MBB,
313                             MachineBasicBlock::iterator MI,
314                             unsigned DestReg, unsigned SubIdx,
315                             const MachineInstr *Orig,
316                             const TargetRegisterInfo &TRI) const;
317
318  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
319
320  virtual bool produceSameValue(const MachineInstr *MI0,
321                                const MachineInstr *MI1) const;
322
323  virtual bool isSchedulingBoundary(const MachineInstr *MI,
324                                    const MachineBasicBlock *MBB,
325                                    const MachineFunction &MF) const;
326};
327
328static inline
329const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
330  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
331}
332
333static inline
334const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
335  return MIB.addReg(0);
336}
337
338static inline
339const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
340                                          bool isDead = false) {
341  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
342}
343
344static inline
345const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
346  return MIB.addReg(0);
347}
348
349static inline
350bool isUncondBranchOpcode(int Opc) {
351  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
352}
353
354static inline
355bool isCondBranchOpcode(int Opc) {
356  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
357}
358
359static inline
360bool isJumpTableBranchOpcode(int Opc) {
361  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
362    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
363}
364
365static inline
366bool isIndirectBranchOpcode(int Opc) {
367  return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
368}
369
370/// getInstrPredicate - If instruction is predicated, returns its predicate
371/// condition, otherwise returns AL. It also returns the condition code
372/// register by reference.
373ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
374
375int getMatchingCondBranchOpcode(int Opc);
376
377/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
378/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
379/// code.
380void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
381                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
382                             unsigned DestReg, unsigned BaseReg, int NumBytes,
383                             ARMCC::CondCodes Pred, unsigned PredReg,
384                             const ARMBaseInstrInfo &TII);
385
386void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
387                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
388                            unsigned DestReg, unsigned BaseReg, int NumBytes,
389                            ARMCC::CondCodes Pred, unsigned PredReg,
390                            const ARMBaseInstrInfo &TII);
391
392
393/// rewriteARMFrameIndex / rewriteT2FrameIndex -
394/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
395/// offset could not be handled directly in MI, and return the left-over
396/// portion by reference.
397bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
398                          unsigned FrameReg, int &Offset,
399                          const ARMBaseInstrInfo &TII);
400
401bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
402                         unsigned FrameReg, int &Offset,
403                         const ARMBaseInstrInfo &TII);
404
405} // End llvm namespace
406
407#endif
408