ARMBaseInstrInfo.h revision a0792de66c8364d47b0a688c7f408efb7b10f31b 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21namespace llvm {
22  class ARMSubtarget;
23  class ARMBaseRegisterInfo;
24
25/// ARMII - This namespace holds all of the target specific flags that
26/// instruction info tracks.
27///
28namespace ARMII {
29  enum {
30    //===------------------------------------------------------------------===//
31    // Instruction Flags.
32
33    //===------------------------------------------------------------------===//
34    // This four-bit field describes the addressing mode used.
35
36    AddrModeMask  = 0x1f,
37    AddrModeNone    = 0,
38    AddrMode1       = 1,
39    AddrMode2       = 2,
40    AddrMode3       = 3,
41    AddrMode4       = 4,
42    AddrMode5       = 5,
43    AddrMode6       = 6,
44    AddrModeT1_1    = 7,
45    AddrModeT1_2    = 8,
46    AddrModeT1_4    = 9,
47    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
48    AddrModeT2_i12  = 11,
49    AddrModeT2_i8   = 12,
50    AddrModeT2_so   = 13,
51    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
52    AddrModeT2_i8s4 = 15, // i8 * 4
53
54    // Size* - Flags to keep track of the size of an instruction.
55    SizeShift     = 5,
56    SizeMask      = 7 << SizeShift,
57    SizeSpecial   = 1,   // 0 byte pseudo or special case.
58    Size8Bytes    = 2,
59    Size4Bytes    = 3,
60    Size2Bytes    = 4,
61
62    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
63    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
64    IndexModeShift = 8,
65    IndexModeMask  = 3 << IndexModeShift,
66    IndexModePre   = 1,
67    IndexModePost  = 2,
68    IndexModeUpd   = 3,
69
70    //===------------------------------------------------------------------===//
71    // Instruction encoding formats.
72    //
73    FormShift     = 10,
74    FormMask      = 0x3f << FormShift,
75
76    // Pseudo instructions
77    Pseudo        = 0  << FormShift,
78
79    // Multiply instructions
80    MulFrm        = 1  << FormShift,
81
82    // Branch instructions
83    BrFrm         = 2  << FormShift,
84    BrMiscFrm     = 3  << FormShift,
85
86    // Data Processing instructions
87    DPFrm         = 4  << FormShift,
88    DPSoRegFrm    = 5  << FormShift,
89
90    // Load and Store
91    LdFrm         = 6  << FormShift,
92    StFrm         = 7  << FormShift,
93    LdMiscFrm     = 8  << FormShift,
94    StMiscFrm     = 9  << FormShift,
95    LdStMulFrm    = 10 << FormShift,
96
97    LdStExFrm     = 11 << FormShift,
98
99    // Miscellaneous arithmetic instructions
100    ArithMiscFrm  = 12 << FormShift,
101    SatFrm        = 13 << FormShift,
102
103    // Extend instructions
104    ExtFrm        = 14 << FormShift,
105
106    // VFP formats
107    VFPUnaryFrm   = 15 << FormShift,
108    VFPBinaryFrm  = 16 << FormShift,
109    VFPConv1Frm   = 17 << FormShift,
110    VFPConv2Frm   = 18 << FormShift,
111    VFPConv3Frm   = 19 << FormShift,
112    VFPConv4Frm   = 20 << FormShift,
113    VFPConv5Frm   = 21 << FormShift,
114    VFPLdStFrm    = 22 << FormShift,
115    VFPLdStMulFrm = 23 << FormShift,
116    VFPMiscFrm    = 24 << FormShift,
117
118    // Thumb format
119    ThumbFrm      = 25 << FormShift,
120
121    // Miscelleaneous format
122    MiscFrm       = 26 << FormShift,
123
124    // NEON formats
125    NGetLnFrm     = 27 << FormShift,
126    NSetLnFrm     = 28 << FormShift,
127    NDupFrm       = 29 << FormShift,
128    NLdStFrm      = 30 << FormShift,
129    N1RegModImmFrm= 31 << FormShift,
130    N2RegFrm      = 32 << FormShift,
131    NVCVTFrm      = 33 << FormShift,
132    NVDupLnFrm    = 34 << FormShift,
133    N2RegVShLFrm  = 35 << FormShift,
134    N2RegVShRFrm  = 36 << FormShift,
135    N3RegFrm      = 37 << FormShift,
136    N3RegVShFrm   = 38 << FormShift,
137    NVExtFrm      = 39 << FormShift,
138    NVMulSLFrm    = 40 << FormShift,
139    NVTBLFrm      = 41 << FormShift,
140
141    //===------------------------------------------------------------------===//
142    // Misc flags.
143
144    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
145    // it doesn't have a Rn operand.
146    UnaryDP       = 1 << 16,
147
148    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
149    // a 16-bit Thumb instruction if certain conditions are met.
150    Xform16Bit    = 1 << 17,
151
152    //===------------------------------------------------------------------===//
153    // Code domain.
154    DomainShift   = 18,
155    DomainMask    = 3 << DomainShift,
156    DomainGeneral = 0 << DomainShift,
157    DomainVFP     = 1 << DomainShift,
158    DomainNEON    = 2 << DomainShift,
159
160    //===------------------------------------------------------------------===//
161    // Field shifts - such shifts are used to set field while generating
162    // machine instructions.
163    M_BitShift     = 5,
164    ShiftImmShift  = 5,
165    ShiftShift     = 7,
166    N_BitShift     = 7,
167    ImmHiShift     = 8,
168    SoRotImmShift  = 8,
169    RegRsShift     = 8,
170    ExtRotImmShift = 10,
171    RegRdLoShift   = 12,
172    RegRdShift     = 12,
173    RegRdHiShift   = 16,
174    RegRnShift     = 16,
175    S_BitShift     = 20,
176    W_BitShift     = 21,
177    AM3_I_BitShift = 22,
178    D_BitShift     = 22,
179    U_BitShift     = 23,
180    P_BitShift     = 24,
181    I_BitShift     = 25,
182    CondShift      = 28
183  };
184}
185
186class ARMBaseInstrInfo : public TargetInstrInfoImpl {
187  const ARMSubtarget &Subtarget;
188protected:
189  // Can be only subclassed.
190  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
191public:
192  // Return the non-pre/post incrementing version of 'Opc'. Return 0
193  // if there is not such an opcode.
194  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
195
196  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
197                                              MachineBasicBlock::iterator &MBBI,
198                                              LiveVariables *LV) const;
199
200  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
201  const ARMSubtarget &getSubtarget() const { return Subtarget; }
202
203  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
204                                 MachineBasicBlock::iterator MI,
205                                 const std::vector<CalleeSavedInfo> &CSI,
206                                 const TargetRegisterInfo *TRI) const;
207
208  // Branch analysis.
209  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
210                             MachineBasicBlock *&FBB,
211                             SmallVectorImpl<MachineOperand> &Cond,
212                             bool AllowModify = false) const;
213  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
214  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
215                                MachineBasicBlock *FBB,
216                                const SmallVectorImpl<MachineOperand> &Cond,
217                                DebugLoc DL) const;
218
219  virtual
220  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
221
222  // Predication support.
223  bool isPredicated(const MachineInstr *MI) const {
224    int PIdx = MI->findFirstPredOperandIdx();
225    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
226  }
227
228  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
229    int PIdx = MI->findFirstPredOperandIdx();
230    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
231                      : ARMCC::AL;
232  }
233
234  virtual
235  bool PredicateInstruction(MachineInstr *MI,
236                            const SmallVectorImpl<MachineOperand> &Pred) const;
237
238  virtual
239  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
240                         const SmallVectorImpl<MachineOperand> &Pred2) const;
241
242  virtual bool DefinesPredicate(MachineInstr *MI,
243                                std::vector<MachineOperand> &Pred) const;
244
245  virtual bool isPredicable(MachineInstr *MI) const;
246
247  /// GetInstSize - Returns the size of the specified MachineInstr.
248  ///
249  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
250
251  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
252                                       int &FrameIndex) const;
253  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
254                                      int &FrameIndex) const;
255
256  virtual void copyPhysReg(MachineBasicBlock &MBB,
257                           MachineBasicBlock::iterator I, DebugLoc DL,
258                           unsigned DestReg, unsigned SrcReg,
259                           bool KillSrc) const;
260
261  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
262                                   MachineBasicBlock::iterator MBBI,
263                                   unsigned SrcReg, bool isKill, int FrameIndex,
264                                   const TargetRegisterClass *RC,
265                                   const TargetRegisterInfo *TRI) const;
266
267  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
268                                    MachineBasicBlock::iterator MBBI,
269                                    unsigned DestReg, int FrameIndex,
270                                    const TargetRegisterClass *RC,
271                                    const TargetRegisterInfo *TRI) const;
272
273  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
274                                                 int FrameIx,
275                                                 uint64_t Offset,
276                                                 const MDNode *MDPtr,
277                                                 DebugLoc DL) const;
278
279  virtual void reMaterialize(MachineBasicBlock &MBB,
280                             MachineBasicBlock::iterator MI,
281                             unsigned DestReg, unsigned SubIdx,
282                             const MachineInstr *Orig,
283                             const TargetRegisterInfo &TRI) const;
284
285  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
286
287  virtual bool produceSameValue(const MachineInstr *MI0,
288                                const MachineInstr *MI1) const;
289
290  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
291  /// determine if two loads are loading from the same base address. It should
292  /// only return true if the base pointers are the same and the only
293  /// differences between the two addresses is the offset. It also returns the
294  /// offsets by reference.
295  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
296                                       int64_t &Offset1, int64_t &Offset2)const;
297
298  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
299  /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
300  /// be scheduled togther. On some targets if two loads are loading from
301  /// addresses in the same cache line, it's better if they are scheduled
302  /// together. This function takes two integers that represent the load offsets
303  /// from the common base address. It returns true if it decides it's desirable
304  /// to schedule the two loads together. "NumLoads" is the number of loads that
305  /// have already been scheduled after Load1.
306  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
307                                       int64_t Offset1, int64_t Offset2,
308                                       unsigned NumLoads) const;
309
310  virtual bool isSchedulingBoundary(const MachineInstr *MI,
311                                    const MachineBasicBlock *MBB,
312                                    const MachineFunction &MF) const;
313
314  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
315                                   unsigned NumInstrs,
316                                   float Prob, float Confidence) const;
317
318  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
319                                   MachineBasicBlock &FMBB,unsigned NumF,
320                                   float Probability, float Confidence) const;
321
322  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
323                                         unsigned NumInstrs,
324                                         float Probability,
325                                         float Confidence) const {
326    return NumInstrs && NumInstrs == 1;
327  }
328
329  /// AnalyzeCompare - For a comparison instruction, return the source register
330  /// in SrcReg and the value it compares against in CmpValue. Return true if
331  /// the comparison instruction can be analyzed.
332  virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
333                              int &CmpMask, int &CmpValue) const;
334
335  /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
336  /// that we can remove a "comparison with zero".
337  virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
338                                    int CmpMask, int CmpValue,
339                                    MachineBasicBlock::iterator &MII) const;
340
341  virtual unsigned getNumMicroOps(const MachineInstr *MI,
342                                  const InstrItineraryData *ItinData) const;
343
344  virtual
345  int getOperandLatency(const InstrItineraryData *ItinData,
346                        const MachineInstr *DefMI, unsigned DefIdx,
347                        const MachineInstr *UseMI, unsigned UseIdx) const;
348  virtual
349  int getOperandLatency(const InstrItineraryData *ItinData,
350                        SDNode *DefNode, unsigned DefIdx,
351                        SDNode *UseNode, unsigned UseIdx) const;
352private:
353  int getOperandLatency(const InstrItineraryData *ItinData,
354                        const TargetInstrDesc &DefTID,
355                        unsigned DefIdx, unsigned DefAlign,
356                        const TargetInstrDesc &UseTID,
357                        unsigned UseIdx, unsigned UseAlign) const;
358};
359
360static inline
361const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
362  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
363}
364
365static inline
366const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
367  return MIB.addReg(0);
368}
369
370static inline
371const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
372                                          bool isDead = false) {
373  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
374}
375
376static inline
377const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
378  return MIB.addReg(0);
379}
380
381static inline
382bool isUncondBranchOpcode(int Opc) {
383  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
384}
385
386static inline
387bool isCondBranchOpcode(int Opc) {
388  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
389}
390
391static inline
392bool isJumpTableBranchOpcode(int Opc) {
393  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
394    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
395}
396
397static inline
398bool isIndirectBranchOpcode(int Opc) {
399  return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
400}
401
402/// getInstrPredicate - If instruction is predicated, returns its predicate
403/// condition, otherwise returns AL. It also returns the condition code
404/// register by reference.
405ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
406
407int getMatchingCondBranchOpcode(int Opc);
408
409/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
410/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
411/// code.
412void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
413                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
414                             unsigned DestReg, unsigned BaseReg, int NumBytes,
415                             ARMCC::CondCodes Pred, unsigned PredReg,
416                             const ARMBaseInstrInfo &TII);
417
418void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
419                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
420                            unsigned DestReg, unsigned BaseReg, int NumBytes,
421                            ARMCC::CondCodes Pred, unsigned PredReg,
422                            const ARMBaseInstrInfo &TII);
423
424
425/// rewriteARMFrameIndex / rewriteT2FrameIndex -
426/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
427/// offset could not be handled directly in MI, and return the left-over
428/// portion by reference.
429bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
430                          unsigned FrameReg, int &Offset,
431                          const ARMBaseInstrInfo &TII);
432
433bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
434                         unsigned FrameReg, int &Offset,
435                         const ARMBaseInstrInfo &TII);
436
437} // End llvm namespace
438
439#endif
440