ARMBaseInstrInfo.h revision ce7bf1c55f5238870bae2909cd368151f1d813d1 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "ARMRegisterInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22namespace llvm {
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28  enum {
29    //===------------------------------------------------------------------===//
30    // Instruction Flags.
31
32    //===------------------------------------------------------------------===//
33    // This four-bit field describes the addressing mode used.
34
35    AddrModeMask  = 0xf,
36    AddrModeNone    = 0,
37    AddrMode1       = 1,
38    AddrMode2       = 2,
39    AddrMode3       = 3,
40    AddrMode4       = 4,
41    AddrMode5       = 5,
42    AddrMode6       = 6,
43    AddrModeT1_1    = 7,
44    AddrModeT1_2    = 8,
45    AddrModeT1_4    = 9,
46    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
47    AddrModeT2_i12  = 11,
48    AddrModeT2_i8   = 12,
49    AddrModeT2_so   = 13,
50    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
51    AddrModeT2_i8s4 = 15, // i8 * 4
52
53    // Size* - Flags to keep track of the size of an instruction.
54    SizeShift     = 4,
55    SizeMask      = 7 << SizeShift,
56    SizeSpecial   = 1,   // 0 byte pseudo or special case.
57    Size8Bytes    = 2,
58    Size4Bytes    = 3,
59    Size2Bytes    = 4,
60
61    // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
62    // and store ops
63    IndexModeShift = 7,
64    IndexModeMask  = 3 << IndexModeShift,
65    IndexModePre   = 1,
66    IndexModePost  = 2,
67
68    //===------------------------------------------------------------------===//
69    // Instruction encoding formats.
70    //
71    FormShift     = 9,
72    FormMask      = 0x3f << FormShift,
73
74    // Pseudo instructions
75    Pseudo        = 0  << FormShift,
76
77    // Multiply instructions
78    MulFrm        = 1  << FormShift,
79
80    // Branch instructions
81    BrFrm         = 2  << FormShift,
82    BrMiscFrm     = 3  << FormShift,
83
84    // Data Processing instructions
85    DPFrm         = 4  << FormShift,
86    DPSoRegFrm    = 5  << FormShift,
87
88    // Load and Store
89    LdFrm         = 6  << FormShift,
90    StFrm         = 7  << FormShift,
91    LdMiscFrm     = 8  << FormShift,
92    StMiscFrm     = 9  << FormShift,
93    LdStMulFrm    = 10 << FormShift,
94
95    LdStExFrm     = 28 << FormShift,
96
97    // Miscellaneous arithmetic instructions
98    ArithMiscFrm  = 11 << FormShift,
99
100    // Extend instructions
101    ExtFrm        = 12 << FormShift,
102
103    // VFP formats
104    VFPUnaryFrm   = 13 << FormShift,
105    VFPBinaryFrm  = 14 << FormShift,
106    VFPConv1Frm   = 15 << FormShift,
107    VFPConv2Frm   = 16 << FormShift,
108    VFPConv3Frm   = 17 << FormShift,
109    VFPConv4Frm   = 18 << FormShift,
110    VFPConv5Frm   = 19 << FormShift,
111    VFPLdStFrm    = 20 << FormShift,
112    VFPLdStMulFrm = 21 << FormShift,
113    VFPMiscFrm    = 22 << FormShift,
114
115    // Thumb format
116    ThumbFrm      = 23 << FormShift,
117
118    // NEON format
119    NEONFrm       = 24 << FormShift,
120    NEONGetLnFrm  = 25 << FormShift,
121    NEONSetLnFrm  = 26 << FormShift,
122    NEONDupFrm    = 27 << FormShift,
123
124    //===------------------------------------------------------------------===//
125    // Misc flags.
126
127    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
128    // it doesn't have a Rn operand.
129    UnaryDP       = 1 << 15,
130
131    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
132    // a 16-bit Thumb instruction if certain conditions are met.
133    Xform16Bit    = 1 << 16,
134
135    //===------------------------------------------------------------------===//
136    // Code domain.
137    DomainShift   = 17,
138    DomainMask    = 3 << DomainShift,
139    DomainGeneral = 0 << DomainShift,
140    DomainVFP     = 1 << DomainShift,
141    DomainNEON    = 2 << DomainShift,
142
143    //===------------------------------------------------------------------===//
144    // Field shifts - such shifts are used to set field while generating
145    // machine instructions.
146    M_BitShift     = 5,
147    ShiftImmShift  = 5,
148    ShiftShift     = 7,
149    N_BitShift     = 7,
150    ImmHiShift     = 8,
151    SoRotImmShift  = 8,
152    RegRsShift     = 8,
153    ExtRotImmShift = 10,
154    RegRdLoShift   = 12,
155    RegRdShift     = 12,
156    RegRdHiShift   = 16,
157    RegRnShift     = 16,
158    S_BitShift     = 20,
159    W_BitShift     = 21,
160    AM3_I_BitShift = 22,
161    D_BitShift     = 22,
162    U_BitShift     = 23,
163    P_BitShift     = 24,
164    I_BitShift     = 25,
165    CondShift      = 28
166  };
167
168  /// Target Operand Flag enum.
169  enum TOF {
170    //===------------------------------------------------------------------===//
171    // ARM Specific MachineOperand flags.
172
173    MO_NO_FLAG,
174
175    /// MO_LO16 - On a symbol operand, this represents a relocation containing
176    /// lower 16 bit of the address. Used only via movw instruction.
177    MO_LO16,
178
179    /// MO_HI16 - On a symbol operand, this represents a relocation containing
180    /// higher 16 bit of the address. Used only via movt instruction.
181    MO_HI16
182  };
183}
184
185class ARMBaseInstrInfo : public TargetInstrInfoImpl {
186  const ARMSubtarget& Subtarget;
187protected:
188  // Can be only subclassed.
189  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
190public:
191  // Return the non-pre/post incrementing version of 'Opc'. Return 0
192  // if there is not such an opcode.
193  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
194
195  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
196                                              MachineBasicBlock::iterator &MBBI,
197                                              LiveVariables *LV) const;
198
199  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
200  const ARMSubtarget &getSubtarget() const { return Subtarget; }
201
202  // Branch analysis.
203  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
204                             MachineBasicBlock *&FBB,
205                             SmallVectorImpl<MachineOperand> &Cond,
206                             bool AllowModify) const;
207  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
208  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
209                                MachineBasicBlock *FBB,
210                            const SmallVectorImpl<MachineOperand> &Cond) const;
211
212  virtual
213  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
214
215  // Predication support.
216  bool isPredicated(const MachineInstr *MI) const {
217    int PIdx = MI->findFirstPredOperandIdx();
218    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
219  }
220
221  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
222    int PIdx = MI->findFirstPredOperandIdx();
223    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
224                      : ARMCC::AL;
225  }
226
227  virtual
228  bool PredicateInstruction(MachineInstr *MI,
229                            const SmallVectorImpl<MachineOperand> &Pred) const;
230
231  virtual
232  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
233                         const SmallVectorImpl<MachineOperand> &Pred2) const;
234
235  virtual bool DefinesPredicate(MachineInstr *MI,
236                                std::vector<MachineOperand> &Pred) const;
237
238  virtual bool isPredicable(MachineInstr *MI) const;
239
240  /// GetInstSize - Returns the size of the specified MachineInstr.
241  ///
242  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
243
244  /// Return true if the instruction is a register to register move and return
245  /// the source and dest operands and their sub-register indices by reference.
246  virtual bool isMoveInstr(const MachineInstr &MI,
247                           unsigned &SrcReg, unsigned &DstReg,
248                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
249
250  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
251                                       int &FrameIndex) const;
252  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
253                                      int &FrameIndex) const;
254
255  virtual bool copyRegToReg(MachineBasicBlock &MBB,
256                            MachineBasicBlock::iterator I,
257                            unsigned DestReg, unsigned SrcReg,
258                            const TargetRegisterClass *DestRC,
259                            const TargetRegisterClass *SrcRC) const;
260
261  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
262                                   MachineBasicBlock::iterator MBBI,
263                                   unsigned SrcReg, bool isKill, int FrameIndex,
264                                   const TargetRegisterClass *RC) const;
265
266  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
267                                    MachineBasicBlock::iterator MBBI,
268                                    unsigned DestReg, int FrameIndex,
269                                    const TargetRegisterClass *RC) const;
270
271  virtual bool canFoldMemoryOperand(const MachineInstr *MI,
272                                    const SmallVectorImpl<unsigned> &Ops) const;
273
274  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
275                                              MachineInstr* MI,
276                                              const SmallVectorImpl<unsigned> &Ops,
277                                              int FrameIndex) const;
278
279  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
280                                              MachineInstr* MI,
281                                           const SmallVectorImpl<unsigned> &Ops,
282                                              MachineInstr* LoadMI) const;
283
284  virtual void reMaterialize(MachineBasicBlock &MBB,
285                             MachineBasicBlock::iterator MI,
286                             unsigned DestReg, unsigned SubIdx,
287                             const MachineInstr *Orig,
288                             const TargetRegisterInfo *TRI) const;
289
290  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
291
292  virtual bool produceSameValue(const MachineInstr *MI0,
293                                const MachineInstr *MI1) const;
294};
295
296static inline
297const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
298  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
299}
300
301static inline
302const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
303  return MIB.addReg(0);
304}
305
306static inline
307const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
308                                          bool isDead = false) {
309  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
310}
311
312static inline
313const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
314  return MIB.addReg(0);
315}
316
317static inline
318bool isUncondBranchOpcode(int Opc) {
319  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
320}
321
322static inline
323bool isCondBranchOpcode(int Opc) {
324  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
325}
326
327static inline
328bool isJumpTableBranchOpcode(int Opc) {
329  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
330    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
331}
332
333static inline
334bool isIndirectBranchOpcode(int Opc) {
335  return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
336}
337
338/// getInstrPredicate - If instruction is predicated, returns its predicate
339/// condition, otherwise returns AL. It also returns the condition code
340/// register by reference.
341ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
342
343int getMatchingCondBranchOpcode(int Opc);
344
345/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
346/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
347/// code.
348void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
349                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
350                             unsigned DestReg, unsigned BaseReg, int NumBytes,
351                             ARMCC::CondCodes Pred, unsigned PredReg,
352                             const ARMBaseInstrInfo &TII);
353
354void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
355                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
356                            unsigned DestReg, unsigned BaseReg, int NumBytes,
357                            ARMCC::CondCodes Pred, unsigned PredReg,
358                            const ARMBaseInstrInfo &TII);
359
360
361/// rewriteARMFrameIndex / rewriteT2FrameIndex -
362/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
363/// offset could not be handled directly in MI, and return the left-over
364/// portion by reference.
365bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
366                          unsigned FrameReg, int &Offset,
367                          const ARMBaseInstrInfo &TII);
368
369bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
370                         unsigned FrameReg, int &Offset,
371                         const ARMBaseInstrInfo &TII);
372
373} // End llvm namespace
374
375#endif
376