ARMBaseInstrInfo.h revision ee04a6d3a40c3017124e3fd89a0db473a2824498 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/ADT/DenseMap.h"
21#include "llvm/ADT/SmallSet.h"
22
23#define GET_INSTRINFO_HEADER
24#include "ARMGenInstrInfo.inc"
25
26namespace llvm {
27  class ARMSubtarget;
28  class ARMBaseRegisterInfo;
29
30class ARMBaseInstrInfo : public ARMGenInstrInfo {
31  const ARMSubtarget &Subtarget;
32
33protected:
34  // Can be only subclassed.
35  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
36
37public:
38  // Return the non-pre/post incrementing version of 'Opc'. Return 0
39  // if there is not such an opcode.
40  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
41
42  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
43                                              MachineBasicBlock::iterator &MBBI,
44                                              LiveVariables *LV) const;
45
46  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
47  const ARMSubtarget &getSubtarget() const { return Subtarget; }
48
49  ScheduleHazardRecognizer *
50  CreateTargetHazardRecognizer(const TargetMachine *TM,
51                               const ScheduleDAG *DAG) const;
52
53  ScheduleHazardRecognizer *
54  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
55                                     const ScheduleDAG *DAG) const;
56
57  // Branch analysis.
58  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
59                             MachineBasicBlock *&FBB,
60                             SmallVectorImpl<MachineOperand> &Cond,
61                             bool AllowModify = false) const;
62  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
63  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
64                                MachineBasicBlock *FBB,
65                                const SmallVectorImpl<MachineOperand> &Cond,
66                                DebugLoc DL) const;
67
68  virtual
69  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
70
71  // Predication support.
72  bool isPredicated(const MachineInstr *MI) const {
73    int PIdx = MI->findFirstPredOperandIdx();
74    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
75  }
76
77  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78    int PIdx = MI->findFirstPredOperandIdx();
79    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
80                      : ARMCC::AL;
81  }
82
83  virtual
84  bool PredicateInstruction(MachineInstr *MI,
85                            const SmallVectorImpl<MachineOperand> &Pred) const;
86
87  virtual
88  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89                         const SmallVectorImpl<MachineOperand> &Pred2) const;
90
91  virtual bool DefinesPredicate(MachineInstr *MI,
92                                std::vector<MachineOperand> &Pred) const;
93
94  virtual bool isPredicable(MachineInstr *MI) const;
95
96  /// GetInstSize - Returns the size of the specified MachineInstr.
97  ///
98  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
99
100  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101                                       int &FrameIndex) const;
102  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103                                      int &FrameIndex) const;
104
105  virtual void copyPhysReg(MachineBasicBlock &MBB,
106                           MachineBasicBlock::iterator I, DebugLoc DL,
107                           unsigned DestReg, unsigned SrcReg,
108                           bool KillSrc) const;
109
110  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
111                                   MachineBasicBlock::iterator MBBI,
112                                   unsigned SrcReg, bool isKill, int FrameIndex,
113                                   const TargetRegisterClass *RC,
114                                   const TargetRegisterInfo *TRI) const;
115
116  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
117                                    MachineBasicBlock::iterator MBBI,
118                                    unsigned DestReg, int FrameIndex,
119                                    const TargetRegisterClass *RC,
120                                    const TargetRegisterInfo *TRI) const;
121
122  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
123                                                 int FrameIx,
124                                                 uint64_t Offset,
125                                                 const MDNode *MDPtr,
126                                                 DebugLoc DL) const;
127
128  virtual void reMaterialize(MachineBasicBlock &MBB,
129                             MachineBasicBlock::iterator MI,
130                             unsigned DestReg, unsigned SubIdx,
131                             const MachineInstr *Orig,
132                             const TargetRegisterInfo &TRI) const;
133
134  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
135
136  virtual bool produceSameValue(const MachineInstr *MI0,
137                                const MachineInstr *MI1,
138                                const MachineRegisterInfo *MRI) const;
139
140  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
141  /// determine if two loads are loading from the same base address. It should
142  /// only return true if the base pointers are the same and the only
143  /// differences between the two addresses is the offset. It also returns the
144  /// offsets by reference.
145  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
146                                       int64_t &Offset1, int64_t &Offset2)const;
147
148  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
149  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
150  /// should be scheduled togther. On some targets if two loads are loading from
151  /// addresses in the same cache line, it's better if they are scheduled
152  /// together. This function takes two integers that represent the load offsets
153  /// from the common base address. It returns true if it decides it's desirable
154  /// to schedule the two loads together. "NumLoads" is the number of loads that
155  /// have already been scheduled after Load1.
156  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
157                                       int64_t Offset1, int64_t Offset2,
158                                       unsigned NumLoads) const;
159
160  virtual bool isSchedulingBoundary(const MachineInstr *MI,
161                                    const MachineBasicBlock *MBB,
162                                    const MachineFunction &MF) const;
163
164  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
165                                   unsigned NumCycles, unsigned ExtraPredCycles,
166                                   const BranchProbability &Probability) const;
167
168  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
169                                   unsigned NumT, unsigned ExtraT,
170                                   MachineBasicBlock &FMBB,
171                                   unsigned NumF, unsigned ExtraF,
172                                   const BranchProbability &Probability) const;
173
174  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
175                                         unsigned NumCycles,
176                                         const BranchProbability
177                                           &Probability) const {
178    return NumCycles == 1;
179  }
180
181  /// AnalyzeCompare - For a comparison instruction, return the source register
182  /// in SrcReg and the value it compares against in CmpValue. Return true if
183  /// the comparison instruction can be analyzed.
184  virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
185                              int &CmpMask, int &CmpValue) const;
186
187  /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
188  /// that we can remove a "comparison with zero".
189  virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
190                                    int CmpMask, int CmpValue,
191                                    const MachineRegisterInfo *MRI) const;
192
193  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
194  /// instruction, try to fold the immediate into the use instruction.
195  virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
196                             unsigned Reg, MachineRegisterInfo *MRI) const;
197
198  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
199                                  const MachineInstr *MI) const;
200
201  virtual
202  int getOperandLatency(const InstrItineraryData *ItinData,
203                        const MachineInstr *DefMI, unsigned DefIdx,
204                        const MachineInstr *UseMI, unsigned UseIdx) const;
205  virtual
206  int getOperandLatency(const InstrItineraryData *ItinData,
207                        SDNode *DefNode, unsigned DefIdx,
208                        SDNode *UseNode, unsigned UseIdx) const;
209private:
210  int getVLDMDefCycle(const InstrItineraryData *ItinData,
211                      const MCInstrDesc &DefMCID,
212                      unsigned DefClass,
213                      unsigned DefIdx, unsigned DefAlign) const;
214  int getLDMDefCycle(const InstrItineraryData *ItinData,
215                     const MCInstrDesc &DefMCID,
216                     unsigned DefClass,
217                     unsigned DefIdx, unsigned DefAlign) const;
218  int getVSTMUseCycle(const InstrItineraryData *ItinData,
219                      const MCInstrDesc &UseMCID,
220                      unsigned UseClass,
221                      unsigned UseIdx, unsigned UseAlign) const;
222  int getSTMUseCycle(const InstrItineraryData *ItinData,
223                     const MCInstrDesc &UseMCID,
224                     unsigned UseClass,
225                     unsigned UseIdx, unsigned UseAlign) const;
226  int getOperandLatency(const InstrItineraryData *ItinData,
227                        const MCInstrDesc &DefMCID,
228                        unsigned DefIdx, unsigned DefAlign,
229                        const MCInstrDesc &UseMCID,
230                        unsigned UseIdx, unsigned UseAlign) const;
231
232  int getInstrLatency(const InstrItineraryData *ItinData,
233                      const MachineInstr *MI, unsigned *PredCost = 0) const;
234
235  int getInstrLatency(const InstrItineraryData *ItinData,
236                      SDNode *Node) const;
237
238  bool hasHighOperandLatency(const InstrItineraryData *ItinData,
239                             const MachineRegisterInfo *MRI,
240                             const MachineInstr *DefMI, unsigned DefIdx,
241                             const MachineInstr *UseMI, unsigned UseIdx) const;
242  bool hasLowDefLatency(const InstrItineraryData *ItinData,
243                        const MachineInstr *DefMI, unsigned DefIdx) const;
244
245private:
246  /// Modeling special VFP / NEON fp MLA / MLS hazards.
247
248  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
249  /// MLx table.
250  DenseMap<unsigned, unsigned> MLxEntryMap;
251
252  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
253  /// stalls when scheduled together with fp MLA / MLS opcodes.
254  SmallSet<unsigned, 16> MLxHazardOpcodes;
255
256public:
257  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
258  /// instruction.
259  bool isFpMLxInstruction(unsigned Opcode) const {
260    return MLxEntryMap.count(Opcode);
261  }
262
263  /// isFpMLxInstruction - This version also returns the multiply opcode and the
264  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
265  /// the MLX instructions with an extra lane operand.
266  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
267                          unsigned &AddSubOpc, bool &NegAcc,
268                          bool &HasLane) const;
269
270  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
271  /// will cause stalls when scheduled after (within 4-cycle window) a fp
272  /// MLA / MLS instruction.
273  bool canCauseFpMLxStall(unsigned Opcode) const {
274    return MLxHazardOpcodes.count(Opcode);
275  }
276};
277
278static inline
279const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
280  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
281}
282
283static inline
284const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
285  return MIB.addReg(0);
286}
287
288static inline
289const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
290                                          bool isDead = false) {
291  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
292}
293
294static inline
295const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
296  return MIB.addReg(0);
297}
298
299static inline
300bool isUncondBranchOpcode(int Opc) {
301  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
302}
303
304static inline
305bool isCondBranchOpcode(int Opc) {
306  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
307}
308
309static inline
310bool isJumpTableBranchOpcode(int Opc) {
311  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
312    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
313}
314
315static inline
316bool isIndirectBranchOpcode(int Opc) {
317  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
318}
319
320/// getInstrPredicate - If instruction is predicated, returns its predicate
321/// condition, otherwise returns AL. It also returns the condition code
322/// register by reference.
323ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
324
325int getMatchingCondBranchOpcode(int Opc);
326
327/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
328/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
329/// code.
330void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
331                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
332                             unsigned DestReg, unsigned BaseReg, int NumBytes,
333                             ARMCC::CondCodes Pred, unsigned PredReg,
334                             const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
335
336void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
337                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
338                            unsigned DestReg, unsigned BaseReg, int NumBytes,
339                            ARMCC::CondCodes Pred, unsigned PredReg,
340                            const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
341void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
342                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
343                               unsigned DestReg, unsigned BaseReg,
344                               int NumBytes, const TargetInstrInfo &TII,
345                               const ARMBaseRegisterInfo& MRI,
346                               unsigned MIFlags = 0);
347
348
349/// rewriteARMFrameIndex / rewriteT2FrameIndex -
350/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
351/// offset could not be handled directly in MI, and return the left-over
352/// portion by reference.
353bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
354                          unsigned FrameReg, int &Offset,
355                          const ARMBaseInstrInfo &TII);
356
357bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
358                         unsigned FrameReg, int &Offset,
359                         const ARMBaseInstrInfo &TII);
360
361} // End llvm namespace
362
363#endif
364