ARMBaseInstrInfo.h revision f8c4cfb7cc330234112e1378dac6424d9956add0 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "ARMRegisterInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22namespace llvm {
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28  enum {
29    //===------------------------------------------------------------------===//
30    // Instruction Flags.
31
32    //===------------------------------------------------------------------===//
33    // This four-bit field describes the addressing mode used.
34
35    AddrModeMask  = 0xf,
36    AddrModeNone    = 0,
37    AddrMode1       = 1,
38    AddrMode2       = 2,
39    AddrMode3       = 3,
40    AddrMode4       = 4,
41    AddrMode5       = 5,
42    AddrMode6       = 6,
43    AddrModeT1_1    = 7,
44    AddrModeT1_2    = 8,
45    AddrModeT1_4    = 9,
46    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
47    AddrModeT2_i12  = 11,
48    AddrModeT2_i8   = 12,
49    AddrModeT2_so   = 13,
50    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
51    AddrModeT2_i8s4 = 15, // i8 * 4
52
53    // Size* - Flags to keep track of the size of an instruction.
54    SizeShift     = 4,
55    SizeMask      = 7 << SizeShift,
56    SizeSpecial   = 1,   // 0 byte pseudo or special case.
57    Size8Bytes    = 2,
58    Size4Bytes    = 3,
59    Size2Bytes    = 4,
60
61    // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
62    // and store ops
63    IndexModeShift = 7,
64    IndexModeMask  = 3 << IndexModeShift,
65    IndexModePre   = 1,
66    IndexModePost  = 2,
67
68    //===------------------------------------------------------------------===//
69    // Instruction encoding formats.
70    //
71    FormShift     = 9,
72    FormMask      = 0x3f << FormShift,
73
74    // Pseudo instructions
75    Pseudo        = 0  << FormShift,
76
77    // Multiply instructions
78    MulFrm        = 1  << FormShift,
79
80    // Branch instructions
81    BrFrm         = 2  << FormShift,
82    BrMiscFrm     = 3  << FormShift,
83
84    // Data Processing instructions
85    DPFrm         = 4  << FormShift,
86    DPSoRegFrm    = 5  << FormShift,
87
88    // Load and Store
89    LdFrm         = 6  << FormShift,
90    StFrm         = 7  << FormShift,
91    LdMiscFrm     = 8  << FormShift,
92    StMiscFrm     = 9  << FormShift,
93    LdStMulFrm    = 10 << FormShift,
94
95    // Miscellaneous arithmetic instructions
96    ArithMiscFrm  = 11 << FormShift,
97
98    // Extend instructions
99    ExtFrm        = 12 << FormShift,
100
101    // VFP formats
102    VFPUnaryFrm   = 13 << FormShift,
103    VFPBinaryFrm  = 14 << FormShift,
104    VFPConv1Frm   = 15 << FormShift,
105    VFPConv2Frm   = 16 << FormShift,
106    VFPConv3Frm   = 17 << FormShift,
107    VFPConv4Frm   = 18 << FormShift,
108    VFPConv5Frm   = 19 << FormShift,
109    VFPLdStFrm    = 20 << FormShift,
110    VFPLdStMulFrm = 21 << FormShift,
111    VFPMiscFrm    = 22 << FormShift,
112
113    // Thumb format
114    ThumbFrm      = 23 << FormShift,
115
116    // NEON format
117    NEONFrm       = 24 << FormShift,
118    NEONGetLnFrm  = 25 << FormShift,
119    NEONSetLnFrm  = 26 << FormShift,
120    NEONDupFrm    = 27 << FormShift,
121
122    //===------------------------------------------------------------------===//
123    // Misc flags.
124
125    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
126    // it doesn't have a Rn operand.
127    UnaryDP       = 1 << 15,
128
129    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
130    // a 16-bit Thumb instruction if certain conditions are met.
131    Xform16Bit    = 1 << 16,
132
133    //===------------------------------------------------------------------===//
134    // Code domain.
135    DomainShift   = 17,
136    DomainMask    = 3 << DomainShift,
137    DomainGeneral = 0 << DomainShift,
138    DomainVFP     = 1 << DomainShift,
139    DomainNEON    = 2 << DomainShift,
140
141    //===------------------------------------------------------------------===//
142    // Field shifts - such shifts are used to set field while generating
143    // machine instructions.
144    M_BitShift     = 5,
145    ShiftImmShift  = 5,
146    ShiftShift     = 7,
147    N_BitShift     = 7,
148    ImmHiShift     = 8,
149    SoRotImmShift  = 8,
150    RegRsShift     = 8,
151    ExtRotImmShift = 10,
152    RegRdLoShift   = 12,
153    RegRdShift     = 12,
154    RegRdHiShift   = 16,
155    RegRnShift     = 16,
156    S_BitShift     = 20,
157    W_BitShift     = 21,
158    AM3_I_BitShift = 22,
159    D_BitShift     = 22,
160    U_BitShift     = 23,
161    P_BitShift     = 24,
162    I_BitShift     = 25,
163    CondShift      = 28
164  };
165
166  /// Target Operand Flag enum.
167  enum TOF {
168    //===------------------------------------------------------------------===//
169    // ARM Specific MachineOperand flags.
170
171    MO_NO_FLAG,
172
173    /// MO_LO16 - On a symbol operand, this represents a relocation containing
174    /// lower 16 bit of the address. Used only via movw instruction.
175    MO_LO16,
176
177    /// MO_HI16 - On a symbol operand, this represents a relocation containing
178    /// higher 16 bit of the address. Used only via movt instruction.
179    MO_HI16
180  };
181}
182
183class ARMBaseInstrInfo : public TargetInstrInfoImpl {
184  const ARMSubtarget& Subtarget;
185protected:
186  // Can be only subclassed.
187  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
188public:
189  // Return the non-pre/post incrementing version of 'Opc'. Return 0
190  // if there is not such an opcode.
191  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
192
193  // Return true if the block does not fall through.
194  virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
195
196  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
197                                              MachineBasicBlock::iterator &MBBI,
198                                              LiveVariables *LV) const;
199
200  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
201  const ARMSubtarget &getSubtarget() const { return Subtarget; }
202
203  // Branch analysis.
204  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
205                             MachineBasicBlock *&FBB,
206                             SmallVectorImpl<MachineOperand> &Cond,
207                             bool AllowModify) const;
208  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
209  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
210                                MachineBasicBlock *FBB,
211                            const SmallVectorImpl<MachineOperand> &Cond) const;
212
213  virtual
214  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
215
216  // Predication support.
217  bool isPredicated(const MachineInstr *MI) const {
218    int PIdx = MI->findFirstPredOperandIdx();
219    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
220  }
221
222  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
223    int PIdx = MI->findFirstPredOperandIdx();
224    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
225                      : ARMCC::AL;
226  }
227
228  virtual
229  bool PredicateInstruction(MachineInstr *MI,
230                            const SmallVectorImpl<MachineOperand> &Pred) const;
231
232  virtual
233  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
234                         const SmallVectorImpl<MachineOperand> &Pred2) const;
235
236  virtual bool DefinesPredicate(MachineInstr *MI,
237                                std::vector<MachineOperand> &Pred) const;
238
239  virtual bool isPredicable(MachineInstr *MI) const;
240
241  /// GetInstSize - Returns the size of the specified MachineInstr.
242  ///
243  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
244
245  /// Return true if the instruction is a register to register move and return
246  /// the source and dest operands and their sub-register indices by reference.
247  virtual bool isMoveInstr(const MachineInstr &MI,
248                           unsigned &SrcReg, unsigned &DstReg,
249                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
250
251  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
252                                       int &FrameIndex) const;
253  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
254                                      int &FrameIndex) const;
255
256  virtual bool copyRegToReg(MachineBasicBlock &MBB,
257                            MachineBasicBlock::iterator I,
258                            unsigned DestReg, unsigned SrcReg,
259                            const TargetRegisterClass *DestRC,
260                            const TargetRegisterClass *SrcRC) const;
261
262  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
263                                   MachineBasicBlock::iterator MBBI,
264                                   unsigned SrcReg, bool isKill, int FrameIndex,
265                                   const TargetRegisterClass *RC) const;
266
267  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
268                                    MachineBasicBlock::iterator MBBI,
269                                    unsigned DestReg, int FrameIndex,
270                                    const TargetRegisterClass *RC) const;
271
272  virtual bool canFoldMemoryOperand(const MachineInstr *MI,
273                                    const SmallVectorImpl<unsigned> &Ops) const;
274
275  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
276                                              MachineInstr* MI,
277                                              const SmallVectorImpl<unsigned> &Ops,
278                                              int FrameIndex) const;
279
280  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
281                                              MachineInstr* MI,
282                                           const SmallVectorImpl<unsigned> &Ops,
283                                              MachineInstr* LoadMI) const;
284
285  virtual void reMaterialize(MachineBasicBlock &MBB,
286                             MachineBasicBlock::iterator MI,
287                             unsigned DestReg, unsigned SubIdx,
288                             const MachineInstr *Orig,
289                             const TargetRegisterInfo *TRI) const;
290
291  virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other,
292                           const MachineRegisterInfo *MRI) const;
293
294  virtual bool isProfitableToDuplicateIndirectBranch() const;
295};
296
297static inline
298const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
299  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
300}
301
302static inline
303const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
304  return MIB.addReg(0);
305}
306
307static inline
308const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
309                                          bool isDead = false) {
310  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
311}
312
313static inline
314const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
315  return MIB.addReg(0);
316}
317
318static inline
319bool isUncondBranchOpcode(int Opc) {
320  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
321}
322
323static inline
324bool isCondBranchOpcode(int Opc) {
325  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
326}
327
328static inline
329bool isJumpTableBranchOpcode(int Opc) {
330  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
331    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
332}
333
334static inline
335bool isIndirectBranchOpcode(int Opc) {
336  return Opc == ARM::BRIND || Opc == ARM::tBRIND;
337}
338
339/// getInstrPredicate - If instruction is predicated, returns its predicate
340/// condition, otherwise returns AL. It also returns the condition code
341/// register by reference.
342ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
343
344int getMatchingCondBranchOpcode(int Opc);
345
346/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
347/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
348/// code.
349void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
350                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
351                             unsigned DestReg, unsigned BaseReg, int NumBytes,
352                             ARMCC::CondCodes Pred, unsigned PredReg,
353                             const ARMBaseInstrInfo &TII);
354
355void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
356                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
357                            unsigned DestReg, unsigned BaseReg, int NumBytes,
358                            ARMCC::CondCodes Pred, unsigned PredReg,
359                            const ARMBaseInstrInfo &TII);
360
361
362/// rewriteARMFrameIndex / rewriteT2FrameIndex -
363/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
364/// offset could not be handled directly in MI, and return the left-over
365/// portion by reference.
366bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
367                          unsigned FrameReg, int &Offset,
368                          const ARMBaseInstrInfo &TII);
369
370bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
371                         unsigned FrameReg, int &Offset,
372                         const ARMBaseInstrInfo &TII);
373
374} // End llvm namespace
375
376#endif
377