1//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Thumb-2 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H 15#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H 16 17#include "ARMBaseInstrInfo.h" 18#include "ThumbRegisterInfo.h" 19 20namespace llvm { 21class ARMSubtarget; 22class ScheduleHazardRecognizer; 23 24class Thumb2InstrInfo : public ARMBaseInstrInfo { 25 ThumbRegisterInfo RI; 26public: 27 explicit Thumb2InstrInfo(const ARMSubtarget &STI); 28 29 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 30 void getNoopForMachoTarget(MCInst &NopInst) const override; 31 32 // Return the non-pre/post incrementing version of 'Opc'. Return 0 33 // if there is not such an opcode. 34 unsigned getUnindexedOpcode(unsigned Opc) const override; 35 36 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 37 MachineBasicBlock *NewDest) const override; 38 39 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 40 MachineBasicBlock::iterator MBBI) const override; 41 42 void copyPhysReg(MachineBasicBlock &MBB, 43 MachineBasicBlock::iterator I, DebugLoc DL, 44 unsigned DestReg, unsigned SrcReg, 45 bool KillSrc) const override; 46 47 void storeRegToStackSlot(MachineBasicBlock &MBB, 48 MachineBasicBlock::iterator MBBI, 49 unsigned SrcReg, bool isKill, int FrameIndex, 50 const TargetRegisterClass *RC, 51 const TargetRegisterInfo *TRI) const override; 52 53 void loadRegFromStackSlot(MachineBasicBlock &MBB, 54 MachineBasicBlock::iterator MBBI, 55 unsigned DestReg, int FrameIndex, 56 const TargetRegisterClass *RC, 57 const TargetRegisterInfo *TRI) const override; 58 59 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 60 /// such, whenever a client has an instance of instruction info, it should 61 /// always be able to get register info as well (through this method). 62 /// 63 const ThumbRegisterInfo &getRegisterInfo() const override { return RI; } 64 65private: 66 void expandLoadStackGuard(MachineBasicBlock::iterator MI, 67 Reloc::Model RM) const override; 68}; 69 70/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical 71/// to llvm::getInstrPredicate except it returns AL for conditional branch 72/// instructions which are "predicated", but are not in IT blocks. 73ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 74 75 76} 77 78#endif 79