nv50_program.c revision 5f4f7ad965c40327f16297606ed4f425598bfc2c
1/* 2 * Copyright 2008 Ben Skeggs 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "pipe/p_context.h" 24#include "pipe/p_defines.h" 25#include "pipe/p_state.h" 26#include "pipe/p_inlines.h" 27 28#include "pipe/p_shader_tokens.h" 29#include "tgsi/tgsi_parse.h" 30#include "tgsi/tgsi_util.h" 31 32#include "nv50_context.h" 33 34#define NV50_SU_MAX_TEMP 64 35//#define NV50_PROGRAM_DUMP 36 37/* ARL - gallium craps itself on progs/vp/arl.txt 38 * 39 * MSB - Like MAD, but MUL+SUB 40 * - Fuck it off, introduce a way to negate args for ops that 41 * support it. 42 * 43 * Look into inlining IMMD for ops other than MOV (make it general?) 44 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD, 45 * but can emit to P_TEMP first - then MOV later. NVIDIA does this 46 * 47 * In ops such as ADD it's possible to construct a bad opcode in the !is_long() 48 * case, if the emit_src() causes the inst to suddenly become long. 49 * 50 * Verify half-insns work where expected - and force disable them where they 51 * don't work - MUL has it forcibly disabled atm as it fixes POW.. 52 * 53 * FUCK! watch dst==src vectors, can overwrite components that are needed. 54 * ie. SUB R0, R0.yzxw, R0 55 * 56 * Things to check with renouveau: 57 * FP attr/result assignment - how? 58 * attrib 59 * - 0x16bc maps vp output onto fp hpos 60 * - 0x16c0 maps vp output onto fp col0 61 * result 62 * - colr always 0-3 63 * - depr always 4 64 * 0x16bc->0x16e8 --> some binding between vp/fp regs 65 * 0x16b8 --> VP output count 66 * 67 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005 68 * "MOV rcol.x, fcol.y" = 0x00000004 69 * 0x19a8 --> as above but 0x00000100 and 0x00000000 70 * - 0x00100000 used when KIL used 71 * 0x196c --> as above but 0x00000011 and 0x00000000 72 * 73 * 0x1988 --> 0xXXNNNNNN 74 * - XX == FP high something 75 */ 76struct nv50_reg { 77 enum { 78 P_TEMP, 79 P_ATTR, 80 P_RESULT, 81 P_CONST, 82 P_IMMD 83 } type; 84 int index; 85 86 int hw; 87 int neg; 88 89 int rhw; /* result hw for FP outputs, or interpolant index */ 90 int acc; /* instruction where this reg is last read (first insn == 1) */ 91}; 92 93/* arbitrary limits */ 94#define MAX_IF_DEPTH 4 95#define MAX_LOOP_DEPTH 4 96 97struct nv50_pc { 98 struct nv50_program *p; 99 100 /* hw resources */ 101 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP]; 102 103 /* tgsi resources */ 104 struct nv50_reg *temp; 105 int temp_nr; 106 struct nv50_reg *attr; 107 int attr_nr; 108 struct nv50_reg *result; 109 int result_nr; 110 struct nv50_reg *param; 111 int param_nr; 112 struct nv50_reg *immd; 113 float *immd_buf; 114 int immd_nr; 115 116 struct nv50_reg *temp_temp[16]; 117 unsigned temp_temp_nr; 118 119 /* broadcast and destination replacement regs */ 120 struct nv50_reg *r_brdc; 121 struct nv50_reg *r_dst[4]; 122 123 unsigned interp_mode[32]; 124 /* perspective interpolation registers */ 125 struct nv50_reg *iv_p; 126 struct nv50_reg *iv_c; 127 128 struct nv50_program_exec *if_cond; 129 struct nv50_program_exec *if_insn[MAX_IF_DEPTH]; 130 struct nv50_program_exec *br_join[MAX_IF_DEPTH]; 131 struct nv50_program_exec *br_loop[MAX_LOOP_DEPTH]; /* for BRK branch */ 132 int if_lvl, loop_lvl; 133 unsigned loop_pos[MAX_LOOP_DEPTH]; 134 135 /* current instruction and total number of insns */ 136 unsigned insn_cur; 137 unsigned insn_nr; 138 139 boolean allow32; 140}; 141 142static INLINE void 143ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw) 144{ 145 reg->type = type; 146 reg->index = index; 147 reg->hw = hw; 148 reg->neg = 0; 149 reg->rhw = -1; 150 reg->acc = 0; 151} 152 153static INLINE unsigned 154popcnt4(uint32_t val) 155{ 156 static const unsigned cnt[16] 157 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; 158 return cnt[val & 0xf]; 159} 160 161static void 162alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg) 163{ 164 int i = 0; 165 166 if (reg->type == P_RESULT) { 167 if (pc->p->cfg.high_result < (reg->hw + 1)) 168 pc->p->cfg.high_result = reg->hw + 1; 169 } 170 171 if (reg->type != P_TEMP) 172 return; 173 174 if (reg->hw >= 0) { 175 /*XXX: do this here too to catch FP temp-as-attr usage.. 176 * not clean, but works */ 177 if (pc->p->cfg.high_temp < (reg->hw + 1)) 178 pc->p->cfg.high_temp = reg->hw + 1; 179 return; 180 } 181 182 if (reg->rhw != -1) { 183 /* try to allocate temporary with index rhw first */ 184 if (!(pc->r_temp[reg->rhw])) { 185 pc->r_temp[reg->rhw] = reg; 186 reg->hw = reg->rhw; 187 if (pc->p->cfg.high_temp < (reg->rhw + 1)) 188 pc->p->cfg.high_temp = reg->rhw + 1; 189 return; 190 } 191 /* make sure we don't get things like $r0 needs to go 192 * in $r1 and $r1 in $r0 193 */ 194 i = pc->result_nr * 4; 195 } 196 197 for (; i < NV50_SU_MAX_TEMP; i++) { 198 if (!(pc->r_temp[i])) { 199 pc->r_temp[i] = reg; 200 reg->hw = i; 201 if (pc->p->cfg.high_temp < (i + 1)) 202 pc->p->cfg.high_temp = i + 1; 203 return; 204 } 205 } 206 207 assert(0); 208} 209 210/* XXX: For shaders that aren't executed linearly (e.g. shaders that 211 * contain loops), we need to assign all hw regs to TGSI TEMPs early, 212 * lest we risk temp_temps overwriting regs alloc'd "later". 213 */ 214static struct nv50_reg * 215alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst) 216{ 217 struct nv50_reg *r; 218 int i; 219 220 if (dst && dst->type == P_TEMP && dst->hw == -1) 221 return dst; 222 223 for (i = 0; i < NV50_SU_MAX_TEMP; i++) { 224 if (!pc->r_temp[i]) { 225 r = MALLOC_STRUCT(nv50_reg); 226 ctor_reg(r, P_TEMP, -1, i); 227 pc->r_temp[i] = r; 228 return r; 229 } 230 } 231 232 assert(0); 233 return NULL; 234} 235 236/* Assign the hw of the discarded temporary register src 237 * to the tgsi register dst and free src. 238 */ 239static void 240assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 241{ 242 assert(src->index == -1 && src->hw != -1); 243 244 if (dst->hw != -1) 245 pc->r_temp[dst->hw] = NULL; 246 pc->r_temp[src->hw] = dst; 247 dst->hw = src->hw; 248 249 FREE(src); 250} 251 252/* release the hardware resource held by r */ 253static void 254release_hw(struct nv50_pc *pc, struct nv50_reg *r) 255{ 256 assert(r->type == P_TEMP); 257 if (r->hw == -1) 258 return; 259 260 assert(pc->r_temp[r->hw] == r); 261 pc->r_temp[r->hw] = NULL; 262 263 r->acc = 0; 264 if (r->index == -1) 265 FREE(r); 266} 267 268static void 269free_temp(struct nv50_pc *pc, struct nv50_reg *r) 270{ 271 if (r->index == -1) { 272 unsigned hw = r->hw; 273 274 FREE(pc->r_temp[hw]); 275 pc->r_temp[hw] = NULL; 276 } 277} 278 279static int 280alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx) 281{ 282 int i; 283 284 if ((idx + 4) >= NV50_SU_MAX_TEMP) 285 return 1; 286 287 if (pc->r_temp[idx] || pc->r_temp[idx + 1] || 288 pc->r_temp[idx + 2] || pc->r_temp[idx + 3]) 289 return alloc_temp4(pc, dst, idx + 4); 290 291 for (i = 0; i < 4; i++) { 292 dst[i] = MALLOC_STRUCT(nv50_reg); 293 ctor_reg(dst[i], P_TEMP, -1, idx + i); 294 pc->r_temp[idx + i] = dst[i]; 295 } 296 297 return 0; 298} 299 300static void 301free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4]) 302{ 303 int i; 304 305 for (i = 0; i < 4; i++) 306 free_temp(pc, reg[i]); 307} 308 309static struct nv50_reg * 310temp_temp(struct nv50_pc *pc) 311{ 312 if (pc->temp_temp_nr >= 16) 313 assert(0); 314 315 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL); 316 return pc->temp_temp[pc->temp_temp_nr++]; 317} 318 319static void 320kill_temp_temp(struct nv50_pc *pc) 321{ 322 int i; 323 324 for (i = 0; i < pc->temp_temp_nr; i++) 325 free_temp(pc, pc->temp_temp[i]); 326 pc->temp_temp_nr = 0; 327} 328 329static int 330ctor_immd(struct nv50_pc *pc, float x, float y, float z, float w) 331{ 332 pc->immd_buf = REALLOC(pc->immd_buf, (pc->immd_nr * 4 * sizeof(float)), 333 (pc->immd_nr + 1) * 4 * sizeof(float)); 334 pc->immd_buf[(pc->immd_nr * 4) + 0] = x; 335 pc->immd_buf[(pc->immd_nr * 4) + 1] = y; 336 pc->immd_buf[(pc->immd_nr * 4) + 2] = z; 337 pc->immd_buf[(pc->immd_nr * 4) + 3] = w; 338 339 return pc->immd_nr++; 340} 341 342static struct nv50_reg * 343alloc_immd(struct nv50_pc *pc, float f) 344{ 345 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg); 346 unsigned hw; 347 348 for (hw = 0; hw < pc->immd_nr * 4; hw++) 349 if (pc->immd_buf[hw] == f) 350 break; 351 352 if (hw == pc->immd_nr * 4) 353 hw = ctor_immd(pc, f, -f, 0.5 * f, 0) * 4; 354 355 ctor_reg(r, P_IMMD, -1, hw); 356 return r; 357} 358 359static struct nv50_program_exec * 360exec(struct nv50_pc *pc) 361{ 362 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec); 363 364 e->param.index = -1; 365 return e; 366} 367 368static void 369emit(struct nv50_pc *pc, struct nv50_program_exec *e) 370{ 371 struct nv50_program *p = pc->p; 372 373 if (p->exec_tail) 374 p->exec_tail->next = e; 375 if (!p->exec_head) 376 p->exec_head = e; 377 p->exec_tail = e; 378 p->exec_size += (e->inst[0] & 1) ? 2 : 1; 379} 380 381static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *); 382 383static boolean 384is_long(struct nv50_program_exec *e) 385{ 386 if (e->inst[0] & 1) 387 return TRUE; 388 return FALSE; 389} 390 391static boolean 392is_immd(struct nv50_program_exec *e) 393{ 394 if (is_long(e) && (e->inst[1] & 3) == 3) 395 return TRUE; 396 return FALSE; 397} 398 399static INLINE void 400set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx, 401 struct nv50_program_exec *e) 402{ 403 set_long(pc, e); 404 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12)); 405 e->inst[1] |= (pred << 7) | (idx << 12); 406} 407 408static INLINE void 409set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx, 410 struct nv50_program_exec *e) 411{ 412 set_long(pc, e); 413 e->inst[1] &= ~((0x3 << 4) | (1 << 6)); 414 e->inst[1] |= (idx << 4) | (on << 6); 415} 416 417static INLINE void 418set_long(struct nv50_pc *pc, struct nv50_program_exec *e) 419{ 420 if (is_long(e)) 421 return; 422 423 e->inst[0] |= 1; 424 set_pred(pc, 0xf, 0, e); 425 set_pred_wr(pc, 0, 0, e); 426} 427 428static INLINE void 429set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e) 430{ 431 if (dst->type == P_RESULT) { 432 set_long(pc, e); 433 e->inst[1] |= 0x00000008; 434 } 435 436 alloc_reg(pc, dst); 437 e->inst[0] |= (dst->hw << 2); 438} 439 440static INLINE void 441set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e) 442{ 443 float f = pc->immd_buf[imm->hw]; 444 unsigned val = fui(imm->neg ? -f : f); 445 446 set_long(pc, e); 447 /*XXX: can't be predicated - bits overlap.. catch cases where both 448 * are required and avoid them. */ 449 set_pred(pc, 0, 0, e); 450 set_pred_wr(pc, 0, 0, e); 451 452 e->inst[1] |= 0x00000002 | 0x00000001; 453 e->inst[0] |= (val & 0x3f) << 16; 454 e->inst[1] |= (val >> 6) << 2; 455} 456 457 458#define INTERP_LINEAR 0 459#define INTERP_FLAT 1 460#define INTERP_PERSPECTIVE 2 461#define INTERP_CENTROID 4 462 463/* interpolant index has been stored in dst->rhw */ 464static void 465emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv, 466 unsigned mode) 467{ 468 assert(dst->rhw != -1); 469 struct nv50_program_exec *e = exec(pc); 470 471 e->inst[0] |= 0x80000000; 472 set_dst(pc, dst, e); 473 e->inst[0] |= (dst->rhw << 16); 474 475 if (mode & INTERP_FLAT) { 476 e->inst[0] |= (1 << 8); 477 } else { 478 if (mode & INTERP_PERSPECTIVE) { 479 e->inst[0] |= (1 << 25); 480 alloc_reg(pc, iv); 481 e->inst[0] |= (iv->hw << 9); 482 } 483 484 if (mode & INTERP_CENTROID) 485 e->inst[0] |= (1 << 24); 486 } 487 488 emit(pc, e); 489} 490 491static void 492set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s, 493 struct nv50_program_exec *e) 494{ 495 set_long(pc, e); 496 497 e->param.index = src->hw; 498 e->param.shift = s; 499 e->param.mask = m << (s % 32); 500 501 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22); 502} 503 504static void 505emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 506{ 507 struct nv50_program_exec *e = exec(pc); 508 509 e->inst[0] |= 0x10000000; 510 511 set_dst(pc, dst, e); 512 513 if (pc->allow32 && dst->type != P_RESULT && src->type == P_IMMD) { 514 set_immd(pc, src, e); 515 /*XXX: 32-bit, but steals part of "half" reg space - need to 516 * catch and handle this case if/when we do half-regs 517 */ 518 } else 519 if (src->type == P_IMMD || src->type == P_CONST) { 520 set_long(pc, e); 521 set_data(pc, src, 0x7f, 9, e); 522 e->inst[1] |= 0x20000000; /* src0 const? */ 523 } else { 524 if (src->type == P_ATTR) { 525 set_long(pc, e); 526 e->inst[1] |= 0x00200000; 527 } 528 529 alloc_reg(pc, src); 530 e->inst[0] |= (src->hw << 9); 531 } 532 533 if (is_long(e) && !is_immd(e)) { 534 e->inst[1] |= 0x04000000; /* 32-bit */ 535 e->inst[1] |= 0x0000c000; /* "subsubop" 0x3 */ 536 if (!(e->inst[1] & 0x20000000)) 537 e->inst[1] |= 0x00030000; /* "subsubop" 0xf */ 538 } else 539 e->inst[0] |= 0x00008000; 540 541 emit(pc, e); 542} 543 544static INLINE void 545emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f) 546{ 547 struct nv50_reg *imm = alloc_immd(pc, f); 548 emit_mov(pc, dst, imm); 549 FREE(imm); 550} 551 552static boolean 553check_swap_src_0_1(struct nv50_pc *pc, 554 struct nv50_reg **s0, struct nv50_reg **s1) 555{ 556 struct nv50_reg *src0 = *s0, *src1 = *s1; 557 558 if (src0->type == P_CONST) { 559 if (src1->type != P_CONST) { 560 *s0 = src1; 561 *s1 = src0; 562 return TRUE; 563 } 564 } else 565 if (src1->type == P_ATTR) { 566 if (src0->type != P_ATTR) { 567 *s0 = src1; 568 *s1 = src0; 569 return TRUE; 570 } 571 } 572 573 return FALSE; 574} 575 576static void 577set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src, 578 struct nv50_program_exec *e) 579{ 580 struct nv50_reg *temp; 581 582 if (src->type != P_TEMP) { 583 temp = temp_temp(pc); 584 emit_mov(pc, temp, src); 585 src = temp; 586 } 587 588 alloc_reg(pc, src); 589 e->inst[0] |= (src->hw << 9); 590} 591 592static void 593set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e) 594{ 595 if (src->type == P_ATTR) { 596 set_long(pc, e); 597 e->inst[1] |= 0x00200000; 598 } else 599 if (src->type == P_CONST || src->type == P_IMMD) { 600 struct nv50_reg *temp = temp_temp(pc); 601 602 emit_mov(pc, temp, src); 603 src = temp; 604 } 605 606 alloc_reg(pc, src); 607 e->inst[0] |= (src->hw << 9); 608} 609 610static void 611set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e) 612{ 613 if (src->type == P_ATTR) { 614 struct nv50_reg *temp = temp_temp(pc); 615 616 emit_mov(pc, temp, src); 617 src = temp; 618 } else 619 if (src->type == P_CONST || src->type == P_IMMD) { 620 assert(!(e->inst[0] & 0x00800000)); 621 if (e->inst[0] & 0x01000000) { 622 struct nv50_reg *temp = temp_temp(pc); 623 624 emit_mov(pc, temp, src); 625 src = temp; 626 } else { 627 set_data(pc, src, 0x7f, 16, e); 628 e->inst[0] |= 0x00800000; 629 } 630 } 631 632 alloc_reg(pc, src); 633 e->inst[0] |= (src->hw << 16); 634} 635 636static void 637set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e) 638{ 639 set_long(pc, e); 640 641 if (src->type == P_ATTR) { 642 struct nv50_reg *temp = temp_temp(pc); 643 644 emit_mov(pc, temp, src); 645 src = temp; 646 } else 647 if (src->type == P_CONST || src->type == P_IMMD) { 648 assert(!(e->inst[0] & 0x01000000)); 649 if (e->inst[0] & 0x00800000) { 650 struct nv50_reg *temp = temp_temp(pc); 651 652 emit_mov(pc, temp, src); 653 src = temp; 654 } else { 655 set_data(pc, src, 0x7f, 32+14, e); 656 e->inst[0] |= 0x01000000; 657 } 658 } 659 660 alloc_reg(pc, src); 661 e->inst[1] |= (src->hw << 14); 662} 663 664static void 665emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0, 666 struct nv50_reg *src1) 667{ 668 struct nv50_program_exec *e = exec(pc); 669 670 e->inst[0] |= 0xc0000000; 671 672 if (!pc->allow32) 673 set_long(pc, e); 674 675 check_swap_src_0_1(pc, &src0, &src1); 676 set_dst(pc, dst, e); 677 set_src_0(pc, src0, e); 678 if (src1->type == P_IMMD && !is_long(e)) { 679 if (src0->neg) 680 e->inst[0] |= 0x00008000; 681 set_immd(pc, src1, e); 682 } else { 683 set_src_1(pc, src1, e); 684 if (src0->neg ^ src1->neg) { 685 if (is_long(e)) 686 e->inst[1] |= 0x08000000; 687 else 688 e->inst[0] |= 0x00008000; 689 } 690 } 691 692 emit(pc, e); 693} 694 695static void 696emit_add(struct nv50_pc *pc, struct nv50_reg *dst, 697 struct nv50_reg *src0, struct nv50_reg *src1) 698{ 699 struct nv50_program_exec *e = exec(pc); 700 701 e->inst[0] |= 0xb0000000; 702 703 check_swap_src_0_1(pc, &src0, &src1); 704 705 if (!pc->allow32 || src0->neg || src1->neg) { 706 set_long(pc, e); 707 e->inst[1] |= (src0->neg << 26) | (src1->neg << 27); 708 } 709 710 set_dst(pc, dst, e); 711 set_src_0(pc, src0, e); 712 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e)) 713 set_src_2(pc, src1, e); 714 else 715 if (src1->type == P_IMMD) 716 set_immd(pc, src1, e); 717 else 718 set_src_1(pc, src1, e); 719 720 emit(pc, e); 721} 722 723static void 724emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst, 725 struct nv50_reg *src0, struct nv50_reg *src1) 726{ 727 struct nv50_program_exec *e = exec(pc); 728 729 set_long(pc, e); 730 e->inst[0] |= 0xb0000000; 731 e->inst[1] |= (sub << 29); 732 733 check_swap_src_0_1(pc, &src0, &src1); 734 set_dst(pc, dst, e); 735 set_src_0(pc, src0, e); 736 set_src_1(pc, src1, e); 737 738 emit(pc, e); 739} 740 741static INLINE void 742emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0, 743 struct nv50_reg *src1) 744{ 745 src1->neg ^= 1; 746 emit_add(pc, dst, src0, src1); 747 src1->neg ^= 1; 748} 749 750static void 751emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0, 752 struct nv50_reg *src1, struct nv50_reg *src2) 753{ 754 struct nv50_program_exec *e = exec(pc); 755 756 e->inst[0] |= 0xe0000000; 757 758 check_swap_src_0_1(pc, &src0, &src1); 759 set_dst(pc, dst, e); 760 set_src_0(pc, src0, e); 761 set_src_1(pc, src1, e); 762 set_src_2(pc, src2, e); 763 764 if (src0->neg ^ src1->neg) 765 e->inst[1] |= 0x04000000; 766 if (src2->neg) 767 e->inst[1] |= 0x08000000; 768 769 emit(pc, e); 770} 771 772static INLINE void 773emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0, 774 struct nv50_reg *src1, struct nv50_reg *src2) 775{ 776 src2->neg ^= 1; 777 emit_mad(pc, dst, src0, src1, src2); 778 src2->neg ^= 1; 779} 780 781static void 782emit_flop(struct nv50_pc *pc, unsigned sub, 783 struct nv50_reg *dst, struct nv50_reg *src) 784{ 785 struct nv50_program_exec *e = exec(pc); 786 787 e->inst[0] |= 0x90000000; 788 if (sub) { 789 set_long(pc, e); 790 e->inst[1] |= (sub << 29); 791 } 792 793 set_dst(pc, dst, e); 794 795 if (sub == 0 || sub == 2) 796 set_src_0_restricted(pc, src, e); 797 else 798 set_src_0(pc, src, e); 799 800 emit(pc, e); 801} 802 803static void 804emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 805{ 806 struct nv50_program_exec *e = exec(pc); 807 808 e->inst[0] |= 0xb0000000; 809 810 set_dst(pc, dst, e); 811 set_src_0(pc, src, e); 812 set_long(pc, e); 813 e->inst[1] |= (6 << 29) | 0x00004000; 814 815 emit(pc, e); 816} 817 818static void 819emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 820{ 821 struct nv50_program_exec *e = exec(pc); 822 823 e->inst[0] |= 0xb0000000; 824 825 set_dst(pc, dst, e); 826 set_src_0(pc, src, e); 827 set_long(pc, e); 828 e->inst[1] |= (6 << 29); 829 830 emit(pc, e); 831} 832 833#define CVTOP_RN 0x01 834#define CVTOP_FLOOR 0x03 835#define CVTOP_CEIL 0x05 836#define CVTOP_TRUNC 0x07 837#define CVTOP_SAT 0x08 838#define CVTOP_ABS 0x10 839 840/* 0x04 == 32 bit */ 841/* 0x40 == dst is float */ 842/* 0x80 == src is float */ 843#define CVT_F32_F32 0xc4 844#define CVT_F32_S32 0x44 845#define CVT_F32_U32 0x64 846#define CVT_S32_F32 0x8c 847#define CVT_S32_S32 0x0c 848#define CVT_NEG 0x20 849#define CVT_RI 0x08 850 851static void 852emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src, 853 int wp, unsigned cvn, unsigned fmt) 854{ 855 struct nv50_program_exec *e; 856 857 e = exec(pc); 858 set_long(pc, e); 859 860 e->inst[0] |= 0xa0000000; 861 e->inst[1] |= 0x00004000; 862 e->inst[1] |= (cvn << 16); 863 e->inst[1] |= (fmt << 24); 864 set_src_0(pc, src, e); 865 866 if (wp >= 0) 867 set_pred_wr(pc, 1, wp, e); 868 869 if (dst) 870 set_dst(pc, dst, e); 871 else { 872 e->inst[0] |= 0x000001fc; 873 e->inst[1] |= 0x00000008; 874 } 875 876 emit(pc, e); 877} 878 879/* nv50 Condition codes: 880 * 0x1 = LT 881 * 0x2 = EQ 882 * 0x3 = LE 883 * 0x4 = GT 884 * 0x5 = NE 885 * 0x6 = GE 886 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge) 887 * 0x8 = unordered bit (allows NaN) 888 */ 889static void 890emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp, 891 struct nv50_reg *src0, struct nv50_reg *src1) 892{ 893 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 }; 894 895 struct nv50_program_exec *e = exec(pc); 896 struct nv50_reg *rdst; 897 898 assert(ccode < 16); 899 if (check_swap_src_0_1(pc, &src0, &src1)) 900 ccode = cc_swapped[ccode & 7] | (ccode & 8); 901 902 rdst = dst; 903 if (dst && dst->type != P_TEMP) 904 dst = alloc_temp(pc, NULL); 905 906 /* set.u32 */ 907 set_long(pc, e); 908 e->inst[0] |= 0xb0000000; 909 e->inst[1] |= 0x60000000 | (ccode << 14); 910 911 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but 912 * that doesn't seem to match what the hw actually does 913 e->inst[1] |= 0x04000000; << breaks things, u32 by default ? 914 */ 915 916 if (wp >= 0) 917 set_pred_wr(pc, 1, wp, e); 918 if (dst) 919 set_dst(pc, dst, e); 920 else { 921 e->inst[0] |= 0x000001fc; 922 e->inst[1] |= 0x00000008; 923 } 924 925 set_src_0(pc, src0, e); 926 set_src_1(pc, src1, e); 927 928 emit(pc, e); 929 pc->if_cond = pc->p->exec_tail; /* record for OPCODE_IF */ 930 931 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */ 932 if (rdst) 933 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32); 934 if (rdst && rdst != dst) 935 free_temp(pc, dst); 936} 937 938static INLINE unsigned 939map_tgsi_setop_cc(unsigned op) 940{ 941 switch (op) { 942 case TGSI_OPCODE_SLT: return 0x1; 943 case TGSI_OPCODE_SGE: return 0x6; 944 case TGSI_OPCODE_SEQ: return 0x2; 945 case TGSI_OPCODE_SGT: return 0x4; 946 case TGSI_OPCODE_SLE: return 0x3; 947 case TGSI_OPCODE_SNE: return 0xd; 948 default: 949 assert(0); 950 return 0; 951 } 952} 953 954static INLINE void 955emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 956{ 957 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI); 958} 959 960static void 961emit_pow(struct nv50_pc *pc, struct nv50_reg *dst, 962 struct nv50_reg *v, struct nv50_reg *e) 963{ 964 struct nv50_reg *temp = alloc_temp(pc, NULL); 965 966 emit_flop(pc, 3, temp, v); 967 emit_mul(pc, temp, temp, e); 968 emit_preex2(pc, temp, temp); 969 emit_flop(pc, 6, dst, temp); 970 971 free_temp(pc, temp); 972} 973 974static INLINE void 975emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 976{ 977 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32); 978} 979 980static INLINE void 981emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 982{ 983 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32); 984} 985 986static void 987emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask, 988 struct nv50_reg **src) 989{ 990 struct nv50_reg *one = alloc_immd(pc, 1.0); 991 struct nv50_reg *zero = alloc_immd(pc, 0.0); 992 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999); 993 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999); 994 struct nv50_reg *tmp[4]; 995 boolean allow32 = pc->allow32; 996 997 pc->allow32 = FALSE; 998 999 if (mask & (3 << 1)) { 1000 tmp[0] = alloc_temp(pc, NULL); 1001 emit_minmax(pc, 4, tmp[0], src[0], zero); 1002 } 1003 1004 if (mask & (1 << 2)) { 1005 set_pred_wr(pc, 1, 0, pc->p->exec_tail); 1006 1007 tmp[1] = temp_temp(pc); 1008 emit_minmax(pc, 4, tmp[1], src[1], zero); 1009 1010 tmp[3] = temp_temp(pc); 1011 emit_minmax(pc, 4, tmp[3], src[3], neg128); 1012 emit_minmax(pc, 5, tmp[3], tmp[3], pos128); 1013 1014 emit_pow(pc, dst[2], tmp[1], tmp[3]); 1015 emit_mov(pc, dst[2], zero); 1016 set_pred(pc, 3, 0, pc->p->exec_tail); 1017 } 1018 1019 if (mask & (1 << 1)) 1020 assimilate_temp(pc, dst[1], tmp[0]); 1021 else 1022 if (mask & (1 << 2)) 1023 free_temp(pc, tmp[0]); 1024 1025 pc->allow32 = allow32; 1026 1027 /* do this last, in case src[i,j] == dst[0,3] */ 1028 if (mask & (1 << 0)) 1029 emit_mov(pc, dst[0], one); 1030 1031 if (mask & (1 << 3)) 1032 emit_mov(pc, dst[3], one); 1033 1034 FREE(pos128); 1035 FREE(neg128); 1036 FREE(zero); 1037 FREE(one); 1038} 1039 1040static void 1041emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 1042{ 1043 struct nv50_program_exec *e = exec(pc); 1044 1045 set_long(pc, e); 1046 e->inst[0] |= 0xa0000000; /* delta */ 1047 e->inst[1] |= (7 << 29); /* delta */ 1048 e->inst[1] |= 0x04000000; /* negate arg0? probably not */ 1049 e->inst[1] |= (1 << 14); /* src .f32 */ 1050 set_dst(pc, dst, e); 1051 set_src_0(pc, src, e); 1052 1053 emit(pc, e); 1054} 1055 1056static void 1057emit_kil(struct nv50_pc *pc, struct nv50_reg *src) 1058{ 1059 struct nv50_program_exec *e; 1060 const int r_pred = 1; 1061 1062 /* Sets predicate reg ? */ 1063 e = exec(pc); 1064 e->inst[0] = 0xa00001fd; 1065 e->inst[1] = 0xc4014788; 1066 set_src_0(pc, src, e); 1067 set_pred_wr(pc, 1, r_pred, e); 1068 if (src->neg) 1069 e->inst[1] |= 0x20000000; 1070 emit(pc, e); 1071 1072 /* This is probably KILP */ 1073 e = exec(pc); 1074 e->inst[0] = 0x000001fe; 1075 set_long(pc, e); 1076 set_pred(pc, 1 /* LT? */, r_pred, e); 1077 emit(pc, e); 1078} 1079 1080static void 1081emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask, 1082 struct nv50_reg **src, unsigned unit, unsigned type, boolean proj) 1083{ 1084 struct nv50_reg *temp, *t[4]; 1085 struct nv50_program_exec *e; 1086 1087 unsigned c, mode, dim; 1088 1089 switch (type) { 1090 case TGSI_TEXTURE_1D: 1091 dim = 1; 1092 break; 1093 case TGSI_TEXTURE_UNKNOWN: 1094 case TGSI_TEXTURE_2D: 1095 case TGSI_TEXTURE_SHADOW1D: /* XXX: x, z */ 1096 case TGSI_TEXTURE_RECT: 1097 dim = 2; 1098 break; 1099 case TGSI_TEXTURE_3D: 1100 case TGSI_TEXTURE_CUBE: 1101 case TGSI_TEXTURE_SHADOW2D: 1102 case TGSI_TEXTURE_SHADOWRECT: /* XXX */ 1103 dim = 3; 1104 break; 1105 default: 1106 assert(0); 1107 break; 1108 } 1109 1110 /* some cards need t[0]'s hw index to be a multiple of 4 */ 1111 alloc_temp4(pc, t, 0); 1112 1113 if (proj) { 1114 if (src[0]->type == P_TEMP && src[0]->rhw != -1) { 1115 mode = pc->interp_mode[src[0]->index]; 1116 1117 t[3]->rhw = src[3]->rhw; 1118 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID)); 1119 emit_flop(pc, 0, t[3], t[3]); 1120 1121 for (c = 0; c < dim; c++) { 1122 t[c]->rhw = src[c]->rhw; 1123 emit_interp(pc, t[c], t[3], 1124 (mode | INTERP_PERSPECTIVE)); 1125 } 1126 } else { 1127 emit_flop(pc, 0, t[3], src[3]); 1128 for (c = 0; c < dim; c++) 1129 emit_mul(pc, t[c], src[c], t[3]); 1130 1131 /* XXX: for some reason the blob sometimes uses MAD: 1132 * emit_mad(pc, t[c], src[0][c], t[3], t[3]) 1133 * pc->p->exec_tail->inst[1] |= 0x080fc000; 1134 */ 1135 } 1136 } else { 1137 if (type == TGSI_TEXTURE_CUBE) { 1138 temp = temp_temp(pc); 1139 emit_minmax(pc, 4, temp, src[0], src[1]); 1140 emit_minmax(pc, 4, temp, temp, src[2]); 1141 emit_flop(pc, 0, temp, temp); 1142 for (c = 0; c < 3; c++) 1143 emit_mul(pc, t[c], src[c], temp); 1144 } else { 1145 for (c = 0; c < dim; c++) 1146 emit_mov(pc, t[c], src[c]); 1147 } 1148 } 1149 1150 e = exec(pc); 1151 set_long(pc, e); 1152 e->inst[0] |= 0xf0000000; 1153 e->inst[1] |= 0x00000004; 1154 set_dst(pc, t[0], e); 1155 e->inst[0] |= (unit << 9); 1156 1157 if (dim == 2) 1158 e->inst[0] |= 0x00400000; 1159 else 1160 if (dim == 3) 1161 e->inst[0] |= 0x00800000; 1162 1163 e->inst[0] |= (mask & 0x3) << 25; 1164 e->inst[1] |= (mask & 0xc) << 12; 1165 1166 emit(pc, e); 1167 1168#if 1 1169 c = 0; 1170 if (mask & 1) emit_mov(pc, dst[0], t[c++]); 1171 if (mask & 2) emit_mov(pc, dst[1], t[c++]); 1172 if (mask & 4) emit_mov(pc, dst[2], t[c++]); 1173 if (mask & 8) emit_mov(pc, dst[3], t[c]); 1174 1175 free_temp4(pc, t); 1176#else 1177 /* XXX: if p.e. MUL is used directly after TEX, it would still use 1178 * the texture coordinates, not the fetched values: latency ? */ 1179 1180 for (c = 0; c < 4; c++) { 1181 if (mask & (1 << c)) 1182 assimilate_temp(pc, dst[c], t[c]); 1183 else 1184 free_temp(pc, t[c]); 1185 } 1186#endif 1187} 1188 1189static void 1190emit_branch(struct nv50_pc *pc, int pred, unsigned cc, 1191 struct nv50_program_exec **join) 1192{ 1193 struct nv50_program_exec *e = exec(pc); 1194 1195 if (join) { 1196 set_long(pc, e); 1197 e->inst[0] |= 0xa0000002; 1198 emit(pc, e); 1199 *join = e; 1200 e = exec(pc); 1201 } 1202 1203 set_long(pc, e); 1204 e->inst[0] |= 0x10000002; 1205 if (pred >= 0) 1206 set_pred(pc, cc, pred, e); 1207 emit(pc, e); 1208} 1209 1210static void 1211emit_nop(struct nv50_pc *pc) 1212{ 1213 struct nv50_program_exec *e = exec(pc); 1214 1215 e->inst[0] = 0xf0000000; 1216 set_long(pc, e); 1217 e->inst[1] = 0xe0000000; 1218 emit(pc, e); 1219} 1220 1221static void 1222convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e) 1223{ 1224 unsigned q = 0, m = ~0; 1225 1226 assert(!is_long(e)); 1227 1228 switch (e->inst[0] >> 28) { 1229 case 0x1: 1230 /* MOV */ 1231 q = 0x0403c000; 1232 m = 0xffff7fff; 1233 break; 1234 case 0x8: 1235 /* INTERP (move centroid, perspective and flat bits) */ 1236 m = ~0x03000100; 1237 q = (e->inst[0] & (3 << 24)) >> (24 - 16); 1238 q |= (e->inst[0] & (1 << 8)) << (18 - 8); 1239 break; 1240 case 0x9: 1241 /* RCP */ 1242 break; 1243 case 0xB: 1244 /* ADD */ 1245 m = ~(127 << 16); 1246 q = ((e->inst[0] & (~m)) >> 2); 1247 break; 1248 case 0xC: 1249 /* MUL */ 1250 m = ~0x00008000; 1251 q = ((e->inst[0] & (~m)) << 12); 1252 break; 1253 case 0xE: 1254 /* MAD (if src2 == dst) */ 1255 q = ((e->inst[0] & 0x1fc) << 12); 1256 break; 1257 default: 1258 assert(0); 1259 break; 1260 } 1261 1262 set_long(pc, e); 1263 pc->p->exec_size++; 1264 1265 e->inst[0] &= m; 1266 e->inst[1] |= q; 1267} 1268 1269static boolean 1270negate_supported(const struct tgsi_full_instruction *insn, int i) 1271{ 1272 switch (insn->Instruction.Opcode) { 1273 case TGSI_OPCODE_DP3: 1274 case TGSI_OPCODE_DP4: 1275 case TGSI_OPCODE_MUL: 1276 case TGSI_OPCODE_KIL: 1277 case TGSI_OPCODE_ADD: 1278 case TGSI_OPCODE_SUB: 1279 case TGSI_OPCODE_MAD: 1280 return TRUE; 1281 case TGSI_OPCODE_POW: 1282 return (i == 1) ? TRUE : FALSE; 1283 default: 1284 return FALSE; 1285 } 1286} 1287 1288/* Return a read mask for source registers deduced from opcode & write mask. */ 1289static unsigned 1290nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c) 1291{ 1292 unsigned x, mask = insn->FullDstRegisters[0].DstRegister.WriteMask; 1293 1294 switch (insn->Instruction.Opcode) { 1295 case TGSI_OPCODE_COS: 1296 case TGSI_OPCODE_SIN: 1297 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0); 1298 case TGSI_OPCODE_DP3: 1299 return 0x7; 1300 case TGSI_OPCODE_DP4: 1301 case TGSI_OPCODE_DPH: 1302 case TGSI_OPCODE_KIL: /* WriteMask ignored */ 1303 return 0xf; 1304 case TGSI_OPCODE_DST: 1305 return mask & (c ? 0xa : 0x6); 1306 case TGSI_OPCODE_EX2: 1307 case TGSI_OPCODE_LG2: 1308 case TGSI_OPCODE_POW: 1309 case TGSI_OPCODE_RCP: 1310 case TGSI_OPCODE_RSQ: 1311 case TGSI_OPCODE_SCS: 1312 return 0x1; 1313 case TGSI_OPCODE_LIT: 1314 return 0xb; 1315 case TGSI_OPCODE_TEX: 1316 case TGSI_OPCODE_TXP: 1317 { 1318 const struct tgsi_instruction_ext_texture *tex; 1319 1320 assert(insn->Instruction.Extended); 1321 tex = &insn->InstructionExtTexture; 1322 1323 mask = 0x7; 1324 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP) 1325 mask |= 0x8; 1326 1327 switch (tex->Texture) { 1328 case TGSI_TEXTURE_1D: 1329 mask &= 0x9; 1330 break; 1331 case TGSI_TEXTURE_2D: 1332 mask &= 0xb; 1333 break; 1334 default: 1335 break; 1336 } 1337 } 1338 return mask; 1339 case TGSI_OPCODE_XPD: 1340 x = 0; 1341 if (mask & 1) x |= 0x6; 1342 if (mask & 2) x |= 0x5; 1343 if (mask & 4) x |= 0x3; 1344 return x; 1345 default: 1346 break; 1347 } 1348 1349 return mask; 1350} 1351 1352static struct nv50_reg * 1353tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst) 1354{ 1355 switch (dst->DstRegister.File) { 1356 case TGSI_FILE_TEMPORARY: 1357 return &pc->temp[dst->DstRegister.Index * 4 + c]; 1358 case TGSI_FILE_OUTPUT: 1359 return &pc->result[dst->DstRegister.Index * 4 + c]; 1360 case TGSI_FILE_NULL: 1361 return NULL; 1362 default: 1363 break; 1364 } 1365 1366 return NULL; 1367} 1368 1369static struct nv50_reg * 1370tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src, 1371 boolean neg) 1372{ 1373 struct nv50_reg *r = NULL; 1374 struct nv50_reg *temp; 1375 unsigned sgn, c; 1376 1377 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan); 1378 1379 c = tgsi_util_get_full_src_register_extswizzle(src, chan); 1380 switch (c) { 1381 case TGSI_EXTSWIZZLE_X: 1382 case TGSI_EXTSWIZZLE_Y: 1383 case TGSI_EXTSWIZZLE_Z: 1384 case TGSI_EXTSWIZZLE_W: 1385 switch (src->SrcRegister.File) { 1386 case TGSI_FILE_INPUT: 1387 r = &pc->attr[src->SrcRegister.Index * 4 + c]; 1388 break; 1389 case TGSI_FILE_TEMPORARY: 1390 r = &pc->temp[src->SrcRegister.Index * 4 + c]; 1391 break; 1392 case TGSI_FILE_CONSTANT: 1393 r = &pc->param[src->SrcRegister.Index * 4 + c]; 1394 break; 1395 case TGSI_FILE_IMMEDIATE: 1396 r = &pc->immd[src->SrcRegister.Index * 4 + c]; 1397 break; 1398 case TGSI_FILE_SAMPLER: 1399 break; 1400 default: 1401 assert(0); 1402 break; 1403 } 1404 break; 1405 case TGSI_EXTSWIZZLE_ZERO: 1406 r = alloc_immd(pc, 0.0); 1407 return r; 1408 case TGSI_EXTSWIZZLE_ONE: 1409 if (sgn == TGSI_UTIL_SIGN_TOGGLE || sgn == TGSI_UTIL_SIGN_SET) 1410 return alloc_immd(pc, -1.0); 1411 return alloc_immd(pc, 1.0); 1412 default: 1413 assert(0); 1414 break; 1415 } 1416 1417 switch (sgn) { 1418 case TGSI_UTIL_SIGN_KEEP: 1419 break; 1420 case TGSI_UTIL_SIGN_CLEAR: 1421 temp = temp_temp(pc); 1422 emit_abs(pc, temp, r); 1423 r = temp; 1424 break; 1425 case TGSI_UTIL_SIGN_TOGGLE: 1426 if (neg) 1427 r->neg = 1; 1428 else { 1429 temp = temp_temp(pc); 1430 emit_neg(pc, temp, r); 1431 r = temp; 1432 } 1433 break; 1434 case TGSI_UTIL_SIGN_SET: 1435 temp = temp_temp(pc); 1436 emit_abs(pc, temp, r); 1437 if (neg) 1438 temp->neg = 1; 1439 else 1440 emit_neg(pc, temp, temp); 1441 r = temp; 1442 break; 1443 default: 1444 assert(0); 1445 break; 1446 } 1447 1448 return r; 1449} 1450 1451/* return TRUE for ops that produce only a single result */ 1452static boolean 1453is_scalar_op(unsigned op) 1454{ 1455 switch (op) { 1456 case TGSI_OPCODE_COS: 1457 case TGSI_OPCODE_DP2: 1458 case TGSI_OPCODE_DP3: 1459 case TGSI_OPCODE_DP4: 1460 case TGSI_OPCODE_DPH: 1461 case TGSI_OPCODE_EX2: 1462 case TGSI_OPCODE_LG2: 1463 case TGSI_OPCODE_POW: 1464 case TGSI_OPCODE_RCP: 1465 case TGSI_OPCODE_RSQ: 1466 case TGSI_OPCODE_SIN: 1467 /* 1468 case TGSI_OPCODE_KIL: 1469 case TGSI_OPCODE_LIT: 1470 case TGSI_OPCODE_SCS: 1471 */ 1472 return TRUE; 1473 default: 1474 return FALSE; 1475 } 1476} 1477 1478/* Returns a bitmask indicating which dst components depend 1479 * on source s, component c (reverse of nv50_tgsi_src_mask). 1480 */ 1481static unsigned 1482nv50_tgsi_dst_revdep(unsigned op, int s, int c) 1483{ 1484 if (is_scalar_op(op)) 1485 return 0x1; 1486 1487 switch (op) { 1488 case TGSI_OPCODE_DST: 1489 return (1 << c) & (s ? 0xa : 0x6); 1490 case TGSI_OPCODE_XPD: 1491 switch (c) { 1492 case 0: return 0x6; 1493 case 1: return 0x5; 1494 case 2: return 0x3; 1495 case 3: return 0x0; 1496 default: 1497 assert(0); 1498 return 0x0; 1499 } 1500 case TGSI_OPCODE_LIT: 1501 case TGSI_OPCODE_SCS: 1502 case TGSI_OPCODE_TEX: 1503 case TGSI_OPCODE_TXP: 1504 /* these take care of dangerous swizzles themselves */ 1505 return 0x0; 1506 case TGSI_OPCODE_IF: 1507 case TGSI_OPCODE_KIL: 1508 /* don't call this function for these ops */ 1509 assert(0); 1510 return 0; 1511 default: 1512 /* linear vector instruction */ 1513 return (1 << c); 1514 } 1515} 1516 1517static INLINE boolean 1518has_pred(struct nv50_program_exec *e, unsigned cc) 1519{ 1520 if (!is_long(e) || is_immd(e)) 1521 return FALSE; 1522 return ((e->inst[1] & 0x780) == (cc << 7)); 1523} 1524 1525/* on ENDIF see if we can do "@p0.neu single_op" instead of: 1526 * join_at ENDIF 1527 * @p0.eq bra ENDIF 1528 * single_op 1529 * ENDIF: nop.join 1530 */ 1531static boolean 1532nv50_kill_branch(struct nv50_pc *pc) 1533{ 1534 int lvl = pc->if_lvl; 1535 1536 if (pc->if_insn[lvl]->next != pc->p->exec_tail) 1537 return FALSE; 1538 1539 /* if ccode == 'true', the BRA is from an ELSE and the predicate 1540 * reg may no longer be valid, since we currently always use $p0 1541 */ 1542 if (has_pred(pc->if_insn[lvl], 0xf)) 1543 return FALSE; 1544 assert(pc->if_insn[lvl] && pc->br_join[lvl]); 1545 1546 /* We'll use the exec allocated for JOIN_AT (as we can't easily 1547 * update prev's next); if exec_tail is BRK, update the pointer. 1548 */ 1549 if (pc->loop_lvl && pc->br_loop[pc->loop_lvl - 1] == pc->p->exec_tail) 1550 pc->br_loop[pc->loop_lvl - 1] = pc->br_join[lvl]; 1551 1552 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */ 1553 1554 *pc->br_join[lvl] = *pc->p->exec_tail; 1555 1556 FREE(pc->if_insn[lvl]); 1557 FREE(pc->p->exec_tail); 1558 1559 pc->p->exec_tail = pc->br_join[lvl]; 1560 pc->p->exec_tail->next = NULL; 1561 set_pred(pc, 0xd, 0, pc->p->exec_tail); 1562 1563 return TRUE; 1564} 1565 1566static boolean 1567nv50_program_tx_insn(struct nv50_pc *pc, 1568 const struct tgsi_full_instruction *inst) 1569{ 1570 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp; 1571 unsigned mask, sat, unit; 1572 int i, c; 1573 1574 mask = inst->FullDstRegisters[0].DstRegister.WriteMask; 1575 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE; 1576 1577 memset(src, 0, sizeof(src)); 1578 1579 for (c = 0; c < 4; c++) { 1580 if ((mask & (1 << c)) && !pc->r_dst[c]) 1581 dst[c] = tgsi_dst(pc, c, &inst->FullDstRegisters[0]); 1582 else 1583 dst[c] = pc->r_dst[c]; 1584 rdst[c] = dst[c]; 1585 } 1586 1587 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) { 1588 const struct tgsi_full_src_register *fs = &inst->FullSrcRegisters[i]; 1589 unsigned src_mask; 1590 boolean neg_supp; 1591 1592 src_mask = nv50_tgsi_src_mask(inst, i); 1593 neg_supp = negate_supported(inst, i); 1594 1595 if (fs->SrcRegister.File == TGSI_FILE_SAMPLER) 1596 unit = fs->SrcRegister.Index; 1597 1598 for (c = 0; c < 4; c++) 1599 if (src_mask & (1 << c)) 1600 src[i][c] = tgsi_src(pc, c, fs, neg_supp); 1601 } 1602 1603 brdc = temp = pc->r_brdc; 1604 if (brdc && brdc->type != P_TEMP) { 1605 temp = temp_temp(pc); 1606 if (sat) 1607 brdc = temp; 1608 } else 1609 if (sat) { 1610 for (c = 0; c < 4; c++) { 1611 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP) 1612 continue; 1613 rdst[c] = dst[c]; 1614 dst[c] = temp_temp(pc); 1615 } 1616 } 1617 1618 assert(brdc || !is_scalar_op(inst->Instruction.Opcode)); 1619 1620 switch (inst->Instruction.Opcode) { 1621 case TGSI_OPCODE_ABS: 1622 for (c = 0; c < 4; c++) { 1623 if (!(mask & (1 << c))) 1624 continue; 1625 emit_abs(pc, dst[c], src[0][c]); 1626 } 1627 break; 1628 case TGSI_OPCODE_ADD: 1629 for (c = 0; c < 4; c++) { 1630 if (!(mask & (1 << c))) 1631 continue; 1632 emit_add(pc, dst[c], src[0][c], src[1][c]); 1633 } 1634 break; 1635 case TGSI_OPCODE_BGNLOOP: 1636 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size; 1637 break; 1638 case TGSI_OPCODE_BRK: 1639 emit_branch(pc, -1, 0, NULL); 1640 assert(pc->loop_lvl > 0); 1641 pc->br_loop[pc->loop_lvl - 1] = pc->p->exec_tail; 1642 break; 1643 case TGSI_OPCODE_CEIL: 1644 for (c = 0; c < 4; c++) { 1645 if (!(mask & (1 << c))) 1646 continue; 1647 emit_cvt(pc, dst[c], src[0][c], -1, 1648 CVTOP_CEIL, CVT_F32_F32 | CVT_RI); 1649 } 1650 break; 1651 case TGSI_OPCODE_COS: 1652 if (mask & 8) { 1653 emit_precossin(pc, temp, src[0][3]); 1654 emit_flop(pc, 5, dst[3], temp); 1655 if (!(mask &= 7)) 1656 break; 1657 if (temp == dst[3]) 1658 temp = brdc = temp_temp(pc); 1659 } 1660 emit_precossin(pc, temp, src[0][0]); 1661 emit_flop(pc, 5, brdc, temp); 1662 break; 1663 case TGSI_OPCODE_DP3: 1664 emit_mul(pc, temp, src[0][0], src[1][0]); 1665 emit_mad(pc, temp, src[0][1], src[1][1], temp); 1666 emit_mad(pc, brdc, src[0][2], src[1][2], temp); 1667 break; 1668 case TGSI_OPCODE_DP4: 1669 emit_mul(pc, temp, src[0][0], src[1][0]); 1670 emit_mad(pc, temp, src[0][1], src[1][1], temp); 1671 emit_mad(pc, temp, src[0][2], src[1][2], temp); 1672 emit_mad(pc, brdc, src[0][3], src[1][3], temp); 1673 break; 1674 case TGSI_OPCODE_DPH: 1675 emit_mul(pc, temp, src[0][0], src[1][0]); 1676 emit_mad(pc, temp, src[0][1], src[1][1], temp); 1677 emit_mad(pc, temp, src[0][2], src[1][2], temp); 1678 emit_add(pc, brdc, src[1][3], temp); 1679 break; 1680 case TGSI_OPCODE_DST: 1681 if (mask & (1 << 1)) 1682 emit_mul(pc, dst[1], src[0][1], src[1][1]); 1683 if (mask & (1 << 2)) 1684 emit_mov(pc, dst[2], src[0][2]); 1685 if (mask & (1 << 3)) 1686 emit_mov(pc, dst[3], src[1][3]); 1687 if (mask & (1 << 0)) 1688 emit_mov_immdval(pc, dst[0], 1.0f); 1689 break; 1690 case TGSI_OPCODE_ELSE: 1691 emit_branch(pc, -1, 0, NULL); 1692 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size; 1693 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail; 1694 break; 1695 case TGSI_OPCODE_ENDIF: 1696 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size; 1697 1698 /* try to replace branch over 1 insn with a predicated insn */ 1699 if (nv50_kill_branch(pc) == TRUE) 1700 break; 1701 1702 if (pc->br_join[pc->if_lvl]) { 1703 pc->br_join[pc->if_lvl]->param.index = pc->p->exec_size; 1704 pc->br_join[pc->if_lvl] = NULL; 1705 } 1706 /* emit a NOP as join point, we could set it on the next 1707 * one, but would have to make sure it is long and !immd 1708 */ 1709 emit_nop(pc); 1710 pc->p->exec_tail->inst[1] |= 2; 1711 break; 1712 case TGSI_OPCODE_ENDLOOP: 1713 emit_branch(pc, -1, 0, NULL); 1714 pc->p->exec_tail->param.index = pc->loop_pos[--pc->loop_lvl]; 1715 pc->br_loop[pc->loop_lvl]->param.index = pc->p->exec_size; 1716 break; 1717 case TGSI_OPCODE_EX2: 1718 emit_preex2(pc, temp, src[0][0]); 1719 emit_flop(pc, 6, brdc, temp); 1720 break; 1721 case TGSI_OPCODE_FLR: 1722 for (c = 0; c < 4; c++) { 1723 if (!(mask & (1 << c))) 1724 continue; 1725 emit_flr(pc, dst[c], src[0][c]); 1726 } 1727 break; 1728 case TGSI_OPCODE_FRC: 1729 temp = temp_temp(pc); 1730 for (c = 0; c < 4; c++) { 1731 if (!(mask & (1 << c))) 1732 continue; 1733 emit_flr(pc, temp, src[0][c]); 1734 emit_sub(pc, dst[c], src[0][c], temp); 1735 } 1736 break; 1737 case TGSI_OPCODE_IF: 1738 /* emitting a join_at may not be necessary */ 1739 assert(pc->if_lvl < MAX_IF_DEPTH); 1740 set_pred_wr(pc, 1, 0, pc->if_cond); 1741 emit_branch(pc, 0, 2, &pc->br_join[pc->if_lvl]); 1742 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail; 1743 break; 1744 case TGSI_OPCODE_KIL: 1745 emit_kil(pc, src[0][0]); 1746 emit_kil(pc, src[0][1]); 1747 emit_kil(pc, src[0][2]); 1748 emit_kil(pc, src[0][3]); 1749 break; 1750 case TGSI_OPCODE_LIT: 1751 emit_lit(pc, &dst[0], mask, &src[0][0]); 1752 break; 1753 case TGSI_OPCODE_LG2: 1754 emit_flop(pc, 3, brdc, src[0][0]); 1755 break; 1756 case TGSI_OPCODE_LRP: 1757 temp = temp_temp(pc); 1758 for (c = 0; c < 4; c++) { 1759 if (!(mask & (1 << c))) 1760 continue; 1761 emit_sub(pc, temp, src[1][c], src[2][c]); 1762 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]); 1763 } 1764 break; 1765 case TGSI_OPCODE_MAD: 1766 for (c = 0; c < 4; c++) { 1767 if (!(mask & (1 << c))) 1768 continue; 1769 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]); 1770 } 1771 break; 1772 case TGSI_OPCODE_MAX: 1773 for (c = 0; c < 4; c++) { 1774 if (!(mask & (1 << c))) 1775 continue; 1776 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]); 1777 } 1778 break; 1779 case TGSI_OPCODE_MIN: 1780 for (c = 0; c < 4; c++) { 1781 if (!(mask & (1 << c))) 1782 continue; 1783 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]); 1784 } 1785 break; 1786 case TGSI_OPCODE_MOV: 1787 case TGSI_OPCODE_SWZ: 1788 for (c = 0; c < 4; c++) { 1789 if (!(mask & (1 << c))) 1790 continue; 1791 emit_mov(pc, dst[c], src[0][c]); 1792 } 1793 break; 1794 case TGSI_OPCODE_MUL: 1795 for (c = 0; c < 4; c++) { 1796 if (!(mask & (1 << c))) 1797 continue; 1798 emit_mul(pc, dst[c], src[0][c], src[1][c]); 1799 } 1800 break; 1801 case TGSI_OPCODE_POW: 1802 emit_pow(pc, brdc, src[0][0], src[1][0]); 1803 break; 1804 case TGSI_OPCODE_RCP: 1805 emit_flop(pc, 0, brdc, src[0][0]); 1806 break; 1807 case TGSI_OPCODE_RSQ: 1808 emit_flop(pc, 2, brdc, src[0][0]); 1809 break; 1810 case TGSI_OPCODE_SCS: 1811 temp = temp_temp(pc); 1812 if (mask & 3) 1813 emit_precossin(pc, temp, src[0][0]); 1814 if (mask & (1 << 0)) 1815 emit_flop(pc, 5, dst[0], temp); 1816 if (mask & (1 << 1)) 1817 emit_flop(pc, 4, dst[1], temp); 1818 if (mask & (1 << 2)) 1819 emit_mov_immdval(pc, dst[2], 0.0); 1820 if (mask & (1 << 3)) 1821 emit_mov_immdval(pc, dst[3], 1.0); 1822 break; 1823 case TGSI_OPCODE_SIN: 1824 if (mask & 8) { 1825 emit_precossin(pc, temp, src[0][3]); 1826 emit_flop(pc, 4, dst[3], temp); 1827 if (!(mask &= 7)) 1828 break; 1829 if (temp == dst[3]) 1830 temp = brdc = temp_temp(pc); 1831 } 1832 emit_precossin(pc, temp, src[0][0]); 1833 emit_flop(pc, 4, brdc, temp); 1834 break; 1835 case TGSI_OPCODE_SLT: 1836 case TGSI_OPCODE_SGE: 1837 case TGSI_OPCODE_SEQ: 1838 case TGSI_OPCODE_SGT: 1839 case TGSI_OPCODE_SLE: 1840 case TGSI_OPCODE_SNE: 1841 i = map_tgsi_setop_cc(inst->Instruction.Opcode); 1842 for (c = 0; c < 4; c++) { 1843 if (!(mask & (1 << c))) 1844 continue; 1845 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]); 1846 } 1847 break; 1848 case TGSI_OPCODE_SUB: 1849 for (c = 0; c < 4; c++) { 1850 if (!(mask & (1 << c))) 1851 continue; 1852 emit_sub(pc, dst[c], src[0][c], src[1][c]); 1853 } 1854 break; 1855 case TGSI_OPCODE_TEX: 1856 emit_tex(pc, dst, mask, src[0], unit, 1857 inst->InstructionExtTexture.Texture, FALSE); 1858 break; 1859 case TGSI_OPCODE_TXP: 1860 emit_tex(pc, dst, mask, src[0], unit, 1861 inst->InstructionExtTexture.Texture, TRUE); 1862 break; 1863 case TGSI_OPCODE_TRUNC: 1864 for (c = 0; c < 4; c++) { 1865 if (!(mask & (1 << c))) 1866 continue; 1867 emit_cvt(pc, dst[c], src[0][c], -1, 1868 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI); 1869 } 1870 break; 1871 case TGSI_OPCODE_XPD: 1872 temp = temp_temp(pc); 1873 if (mask & (1 << 0)) { 1874 emit_mul(pc, temp, src[0][2], src[1][1]); 1875 emit_msb(pc, dst[0], src[0][1], src[1][2], temp); 1876 } 1877 if (mask & (1 << 1)) { 1878 emit_mul(pc, temp, src[0][0], src[1][2]); 1879 emit_msb(pc, dst[1], src[0][2], src[1][0], temp); 1880 } 1881 if (mask & (1 << 2)) { 1882 emit_mul(pc, temp, src[0][1], src[1][0]); 1883 emit_msb(pc, dst[2], src[0][0], src[1][1], temp); 1884 } 1885 if (mask & (1 << 3)) 1886 emit_mov_immdval(pc, dst[3], 1.0); 1887 break; 1888 case TGSI_OPCODE_END: 1889 break; 1890 default: 1891 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode); 1892 return FALSE; 1893 } 1894 1895 if (brdc) { 1896 if (sat) 1897 emit_sat(pc, brdc, brdc); 1898 for (c = 0; c < 4; c++) 1899 if ((mask & (1 << c)) && dst[c] != brdc) 1900 emit_mov(pc, dst[c], brdc); 1901 } else 1902 if (sat) { 1903 for (c = 0; c < 4; c++) { 1904 if (!(mask & (1 << c))) 1905 continue; 1906 /* in this case we saturate later */ 1907 if (dst[c]->type == P_TEMP && dst[c]->index < 0) 1908 continue; 1909 emit_sat(pc, rdst[c], dst[c]); 1910 } 1911 } 1912 1913 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) { 1914 for (c = 0; c < 4; c++) { 1915 if (!src[i][c]) 1916 continue; 1917 if (src[i][c]->index == -1 && src[i][c]->type == P_IMMD) 1918 FREE(src[i][c]); 1919 } 1920 } 1921 1922 kill_temp_temp(pc); 1923 return TRUE; 1924} 1925 1926static void 1927prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn) 1928{ 1929 struct nv50_reg *reg = NULL; 1930 const struct tgsi_full_src_register *src; 1931 const struct tgsi_dst_register *dst; 1932 unsigned i, c, k, mask; 1933 1934 dst = &insn->FullDstRegisters[0].DstRegister; 1935 mask = dst->WriteMask; 1936 1937 if (dst->File == TGSI_FILE_TEMPORARY) 1938 reg = pc->temp; 1939 else 1940 if (dst->File == TGSI_FILE_OUTPUT) 1941 reg = pc->result; 1942 1943 if (reg) { 1944 for (c = 0; c < 4; c++) { 1945 if (!(mask & (1 << c))) 1946 continue; 1947 reg[dst->Index * 4 + c].acc = pc->insn_nr; 1948 } 1949 } 1950 1951 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) { 1952 src = &insn->FullSrcRegisters[i]; 1953 1954 if (src->SrcRegister.File == TGSI_FILE_TEMPORARY) 1955 reg = pc->temp; 1956 else 1957 if (src->SrcRegister.File == TGSI_FILE_INPUT) 1958 reg = pc->attr; 1959 else 1960 continue; 1961 1962 mask = nv50_tgsi_src_mask(insn, i); 1963 1964 for (c = 0; c < 4; c++) { 1965 if (!(mask & (1 << c))) 1966 continue; 1967 k = tgsi_util_get_full_src_register_extswizzle(src, c); 1968 1969 if (k > TGSI_EXTSWIZZLE_W) 1970 continue; 1971 1972 reg[src->SrcRegister.Index * 4 + k].acc = pc->insn_nr; 1973 } 1974 } 1975} 1976 1977/* Returns a bitmask indicating which dst components need to be 1978 * written to temporaries first to avoid 'corrupting' sources. 1979 * 1980 * m[i] (out) indicate component to write in the i-th position 1981 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source 1982 */ 1983static unsigned 1984nv50_revdep_reorder(unsigned m[4], unsigned rdep[4]) 1985{ 1986 unsigned i, c, x, unsafe; 1987 1988 for (c = 0; c < 4; c++) 1989 m[c] = c; 1990 1991 /* Swap as long as a dst component written earlier is depended on 1992 * by one written later, but the next one isn't depended on by it. 1993 */ 1994 for (c = 0; c < 3; c++) { 1995 if (rdep[m[c + 1]] & (1 << m[c])) 1996 continue; /* if next one is depended on by us */ 1997 for (i = c + 1; i < 4; i++) 1998 /* if we are depended on by a later one */ 1999 if (rdep[m[c]] & (1 << m[i])) 2000 break; 2001 if (i == 4) 2002 continue; 2003 /* now, swap */ 2004 x = m[c]; 2005 m[c] = m[c + 1]; 2006 m[c + 1] = x; 2007 2008 /* restart */ 2009 c = 0; 2010 } 2011 2012 /* mark dependencies that could not be resolved by reordering */ 2013 for (i = 0; i < 3; ++i) 2014 for (c = i + 1; c < 4; ++c) 2015 if (rdep[m[i]] & (1 << m[c])) 2016 unsafe |= (1 << i); 2017 2018 /* NOTE: $unsafe is with respect to order, not component */ 2019 return unsafe; 2020} 2021 2022/* Select a suitable dst register for broadcasting scalar results, 2023 * or return NULL if we have to allocate an extra TEMP. 2024 * 2025 * If e.g. only 1 component is written, we may also emit the final 2026 * result to a write-only register. 2027 */ 2028static struct nv50_reg * 2029tgsi_broadcast_dst(struct nv50_pc *pc, 2030 const struct tgsi_full_dst_register *fd, unsigned mask) 2031{ 2032 if (fd->DstRegister.File == TGSI_FILE_TEMPORARY) { 2033 int c = ffs(~mask & fd->DstRegister.WriteMask); 2034 if (c) 2035 return tgsi_dst(pc, c - 1, fd); 2036 } else { 2037 int c = ffs(fd->DstRegister.WriteMask) - 1; 2038 if ((1 << c) == fd->DstRegister.WriteMask) 2039 return tgsi_dst(pc, c, fd); 2040 } 2041 2042 return NULL; 2043} 2044 2045/* Scan source swizzles and return a bitmask indicating dst regs that 2046 * also occur among the src regs, and fill rdep for nv50_revdep_reoder. 2047 */ 2048static unsigned 2049nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn, 2050 unsigned rdep[4]) 2051{ 2052 const struct tgsi_full_dst_register *fd = &insn->FullDstRegisters[0]; 2053 const struct tgsi_full_src_register *fs; 2054 unsigned i, deqs = 0; 2055 2056 for (i = 0; i < 4; ++i) 2057 rdep[i] = 0; 2058 2059 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) { 2060 unsigned chn, mask = nv50_tgsi_src_mask(insn, i); 2061 boolean neg_supp = negate_supported(insn, i); 2062 2063 fs = &insn->FullSrcRegisters[i]; 2064 if (fs->SrcRegister.File != fd->DstRegister.File || 2065 fs->SrcRegister.Index != fd->DstRegister.Index) 2066 continue; 2067 2068 for (chn = 0; chn < 4; ++chn) { 2069 unsigned s, c; 2070 2071 if (!(mask & (1 << chn))) /* src is not read */ 2072 continue; 2073 c = tgsi_util_get_full_src_register_extswizzle(fs, chn); 2074 s = tgsi_util_get_full_src_register_sign_mode(fs, chn); 2075 2076 if (c > TGSI_EXTSWIZZLE_W || 2077 !(fd->DstRegister.WriteMask & (1 << c))) 2078 continue; 2079 2080 /* no danger if src is copied to TEMP first */ 2081 if ((s != TGSI_UTIL_SIGN_KEEP) && 2082 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp)) 2083 continue; 2084 2085 rdep[c] |= nv50_tgsi_dst_revdep( 2086 insn->Instruction.Opcode, i, chn); 2087 deqs |= (1 << c); 2088 } 2089 } 2090 2091 return deqs; 2092} 2093 2094static boolean 2095nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok) 2096{ 2097 struct tgsi_full_instruction insn = tok->FullInstruction; 2098 const struct tgsi_full_dst_register *fd; 2099 unsigned i, deqs, rdep[4], m[4]; 2100 2101 fd = &tok->FullInstruction.FullDstRegisters[0]; 2102 deqs = nv50_tgsi_scan_swizzle(&insn, rdep); 2103 2104 if (is_scalar_op(insn.Instruction.Opcode)) { 2105 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs); 2106 if (!pc->r_brdc) 2107 pc->r_brdc = temp_temp(pc); 2108 return nv50_program_tx_insn(pc, &insn); 2109 } 2110 pc->r_brdc = NULL; 2111 2112 if (!deqs) 2113 return nv50_program_tx_insn(pc, &insn); 2114 2115 deqs = nv50_revdep_reorder(m, rdep); 2116 2117 for (i = 0; i < 4; ++i) { 2118 assert(pc->r_dst[m[i]] == NULL); 2119 2120 insn.FullDstRegisters[0].DstRegister.WriteMask = 2121 fd->DstRegister.WriteMask & (1 << m[i]); 2122 2123 if (!insn.FullDstRegisters[0].DstRegister.WriteMask) 2124 continue; 2125 2126 if (deqs & (1 << i)) 2127 pc->r_dst[m[i]] = alloc_temp(pc, NULL); 2128 2129 if (!nv50_program_tx_insn(pc, &insn)) 2130 return FALSE; 2131 } 2132 2133 for (i = 0; i < 4; i++) { 2134 struct nv50_reg *reg = pc->r_dst[i]; 2135 if (!reg) 2136 continue; 2137 pc->r_dst[i] = NULL; 2138 2139 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE) 2140 emit_sat(pc, tgsi_dst(pc, i, fd), reg); 2141 else 2142 emit_mov(pc, tgsi_dst(pc, i, fd), reg); 2143 free_temp(pc, reg); 2144 } 2145 2146 return TRUE; 2147} 2148 2149static void 2150load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg) 2151{ 2152 struct nv50_reg *iv, **ppiv; 2153 unsigned mode = pc->interp_mode[reg->index]; 2154 2155 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p; 2156 iv = *ppiv; 2157 2158 if ((mode & INTERP_PERSPECTIVE) && !iv) { 2159 iv = *ppiv = alloc_temp(pc, NULL); 2160 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1; 2161 2162 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID); 2163 emit_flop(pc, 0, iv, iv); 2164 2165 /* XXX: when loading interpolants dynamically, move these 2166 * to the program head, or make sure it can't be skipped. 2167 */ 2168 } 2169 2170 emit_interp(pc, reg, iv, mode); 2171} 2172 2173static boolean 2174nv50_program_tx_prep(struct nv50_pc *pc) 2175{ 2176 struct tgsi_parse_context tp; 2177 struct nv50_program *p = pc->p; 2178 boolean ret = FALSE; 2179 unsigned i, c, flat_nr = 0; 2180 2181 tgsi_parse_init(&tp, pc->p->pipe.tokens); 2182 while (!tgsi_parse_end_of_tokens(&tp)) { 2183 const union tgsi_full_token *tok = &tp.FullToken; 2184 2185 tgsi_parse_token(&tp); 2186 switch (tok->Token.Type) { 2187 case TGSI_TOKEN_TYPE_IMMEDIATE: 2188 { 2189 const struct tgsi_full_immediate *imm = 2190 &tp.FullToken.FullImmediate; 2191 2192 ctor_immd(pc, imm->u[0].Float, 2193 imm->u[1].Float, 2194 imm->u[2].Float, 2195 imm->u[3].Float); 2196 } 2197 break; 2198 case TGSI_TOKEN_TYPE_DECLARATION: 2199 { 2200 const struct tgsi_full_declaration *d; 2201 unsigned si, last, first, mode; 2202 2203 d = &tp.FullToken.FullDeclaration; 2204 first = d->DeclarationRange.First; 2205 last = d->DeclarationRange.Last; 2206 2207 switch (d->Declaration.File) { 2208 case TGSI_FILE_TEMPORARY: 2209 break; 2210 case TGSI_FILE_OUTPUT: 2211 if (!d->Declaration.Semantic || 2212 p->type == PIPE_SHADER_FRAGMENT) 2213 break; 2214 2215 si = d->Semantic.SemanticIndex; 2216 switch (d->Semantic.SemanticName) { 2217 case TGSI_SEMANTIC_BCOLOR: 2218 p->cfg.two_side[si].hw = first; 2219 if (p->cfg.io_nr > first) 2220 p->cfg.io_nr = first; 2221 break; 2222 case TGSI_SEMANTIC_PSIZE: 2223 p->cfg.psiz = first; 2224 if (p->cfg.io_nr > first) 2225 p->cfg.io_nr = first; 2226 break; 2227 /* 2228 case TGSI_SEMANTIC_CLIP_DISTANCE: 2229 p->cfg.clpd = MIN2(p->cfg.clpd, first); 2230 break; 2231 */ 2232 default: 2233 break; 2234 } 2235 break; 2236 case TGSI_FILE_INPUT: 2237 { 2238 if (p->type != PIPE_SHADER_FRAGMENT) 2239 break; 2240 2241 switch (d->Declaration.Interpolate) { 2242 case TGSI_INTERPOLATE_CONSTANT: 2243 mode = INTERP_FLAT; 2244 flat_nr++; 2245 break; 2246 case TGSI_INTERPOLATE_PERSPECTIVE: 2247 mode = INTERP_PERSPECTIVE; 2248 p->cfg.regs[1] |= 0x08 << 24; 2249 break; 2250 default: 2251 mode = INTERP_LINEAR; 2252 break; 2253 } 2254 if (d->Declaration.Centroid) 2255 mode |= INTERP_CENTROID; 2256 2257 assert(last < 32); 2258 for (i = first; i <= last; i++) 2259 pc->interp_mode[i] = mode; 2260 } 2261 break; 2262 case TGSI_FILE_CONSTANT: 2263 break; 2264 case TGSI_FILE_SAMPLER: 2265 break; 2266 default: 2267 NOUVEAU_ERR("bad decl file %d\n", 2268 d->Declaration.File); 2269 goto out_err; 2270 } 2271 } 2272 break; 2273 case TGSI_TOKEN_TYPE_INSTRUCTION: 2274 pc->insn_nr++; 2275 prep_inspect_insn(pc, &tok->FullInstruction); 2276 break; 2277 default: 2278 break; 2279 } 2280 } 2281 2282 if (p->type == PIPE_SHADER_VERTEX) { 2283 int rid = 0; 2284 2285 for (i = 0; i < pc->attr_nr * 4; ++i) { 2286 if (pc->attr[i].acc) { 2287 pc->attr[i].hw = rid++; 2288 p->cfg.attr[i / 32] |= 1 << (i % 32); 2289 } 2290 } 2291 2292 for (i = 0, rid = 0; i < pc->result_nr; ++i) { 2293 p->cfg.io[i].hw = rid; 2294 p->cfg.io[i].id_vp = i; 2295 2296 for (c = 0; c < 4; ++c) { 2297 int n = i * 4 + c; 2298 if (!pc->result[n].acc) 2299 continue; 2300 pc->result[n].hw = rid++; 2301 p->cfg.io[i].mask |= 1 << c; 2302 } 2303 } 2304 2305 for (c = 0; c < 2; ++c) 2306 if (p->cfg.two_side[c].hw < 0x40) 2307 p->cfg.two_side[c] = p->cfg.io[ 2308 p->cfg.two_side[c].hw]; 2309 2310 if (p->cfg.psiz < 0x40) 2311 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw; 2312 } else 2313 if (p->type == PIPE_SHADER_FRAGMENT) { 2314 int rid, aid; 2315 unsigned n = 0, m = pc->attr_nr - flat_nr; 2316 2317 int base = (TGSI_SEMANTIC_POSITION == 2318 p->info.input_semantic_name[0]) ? 0 : 1; 2319 2320 /* non-flat interpolants have to be mapped to 2321 * the lower hardware IDs, so sort them: 2322 */ 2323 for (i = 0; i < pc->attr_nr; i++) { 2324 if (pc->interp_mode[i] == INTERP_FLAT) { 2325 p->cfg.io[m].id_vp = i + base; 2326 p->cfg.io[m++].id_fp = i; 2327 } else { 2328 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE)) 2329 p->cfg.io[n].linear = TRUE; 2330 p->cfg.io[n].id_vp = i + base; 2331 p->cfg.io[n++].id_fp = i; 2332 } 2333 } 2334 2335 if (!base) /* set w-coordinate mask from perspective interp */ 2336 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24; 2337 2338 aid = popcnt4( /* if fcrd isn't contained in cfg.io */ 2339 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask); 2340 2341 for (n = 0; n < pc->attr_nr; ++n) { 2342 p->cfg.io[n].hw = rid = aid; 2343 i = p->cfg.io[n].id_fp; 2344 2345 for (c = 0; c < 4; ++c) { 2346 if (!pc->attr[i * 4 + c].acc) 2347 continue; 2348 pc->attr[i * 4 + c].rhw = rid++; 2349 p->cfg.io[n].mask |= 1 << c; 2350 2351 load_interpolant(pc, &pc->attr[i * 4 + c]); 2352 } 2353 aid += popcnt4(p->cfg.io[n].mask); 2354 } 2355 2356 if (!base) 2357 p->cfg.regs[1] |= p->cfg.io[0].mask << 24; 2358 2359 m = popcnt4(p->cfg.regs[1] >> 24); 2360 2361 /* set count of non-position inputs and of non-flat 2362 * non-position inputs for FP_INTERPOLANT_CTRL 2363 */ 2364 p->cfg.regs[1] |= aid - m; 2365 2366 if (flat_nr) { 2367 i = p->cfg.io[pc->attr_nr - flat_nr].hw; 2368 p->cfg.regs[1] |= (i - m) << 16; 2369 } else 2370 p->cfg.regs[1] |= p->cfg.regs[1] << 16; 2371 2372 /* mark color semantic for light-twoside */ 2373 n = 0x40; 2374 for (i = 0; i < pc->attr_nr; i++) { 2375 ubyte si, sn; 2376 2377 sn = p->info.input_semantic_name[p->cfg.io[i].id_fp]; 2378 si = p->info.input_semantic_index[p->cfg.io[i].id_fp]; 2379 2380 if (sn == TGSI_SEMANTIC_COLOR) { 2381 p->cfg.two_side[si] = p->cfg.io[i]; 2382 2383 /* increase colour count */ 2384 p->cfg.regs[0] += popcnt4( 2385 p->cfg.two_side[si].mask) << 16; 2386 2387 n = MIN2(n, p->cfg.io[i].hw - m); 2388 } 2389 } 2390 if (n < 0x40) 2391 p->cfg.regs[0] += n; 2392 2393 /* Initialize FP results: 2394 * FragDepth is always first TGSI and last hw output 2395 */ 2396 i = p->info.writes_z ? 4 : 0; 2397 for (rid = 0; i < pc->result_nr * 4; i++) 2398 pc->result[i].rhw = rid++; 2399 if (p->info.writes_z) 2400 pc->result[2].rhw = rid; 2401 2402 p->cfg.high_result = rid; 2403 } 2404 2405 if (pc->immd_nr) { 2406 int rid = 0; 2407 2408 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg)); 2409 if (!pc->immd) 2410 goto out_err; 2411 2412 for (i = 0; i < pc->immd_nr; i++) { 2413 for (c = 0; c < 4; c++, rid++) 2414 ctor_reg(&pc->immd[rid], P_IMMD, i, rid); 2415 } 2416 } 2417 2418 ret = TRUE; 2419out_err: 2420 if (pc->iv_p) 2421 free_temp(pc, pc->iv_p); 2422 if (pc->iv_c) 2423 free_temp(pc, pc->iv_c); 2424 2425 tgsi_parse_free(&tp); 2426 return ret; 2427} 2428 2429static void 2430free_nv50_pc(struct nv50_pc *pc) 2431{ 2432 if (pc->immd) 2433 FREE(pc->immd); 2434 if (pc->param) 2435 FREE(pc->param); 2436 if (pc->result) 2437 FREE(pc->result); 2438 if (pc->attr) 2439 FREE(pc->attr); 2440 if (pc->temp) 2441 FREE(pc->temp); 2442 2443 FREE(pc); 2444} 2445 2446static boolean 2447ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p) 2448{ 2449 int i, c; 2450 unsigned rtype[2] = { P_ATTR, P_RESULT }; 2451 2452 pc->p = p; 2453 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1; 2454 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1; 2455 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1; 2456 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1; 2457 2458 p->cfg.high_temp = 4; 2459 2460 p->cfg.two_side[0].hw = 0x40; 2461 p->cfg.two_side[1].hw = 0x40; 2462 2463 switch (p->type) { 2464 case PIPE_SHADER_VERTEX: 2465 p->cfg.psiz = 0x40; 2466 p->cfg.clpd = 0x40; 2467 p->cfg.io_nr = pc->result_nr; 2468 break; 2469 case PIPE_SHADER_FRAGMENT: 2470 rtype[0] = rtype[1] = P_TEMP; 2471 2472 p->cfg.regs[0] = 0x01000004; 2473 p->cfg.io_nr = pc->attr_nr; 2474 2475 if (p->info.writes_z) { 2476 p->cfg.regs[2] |= 0x00000100; 2477 p->cfg.regs[3] |= 0x00000011; 2478 } 2479 if (p->info.uses_kill) 2480 p->cfg.regs[2] |= 0x00100000; 2481 break; 2482 } 2483 2484 if (pc->temp_nr) { 2485 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg)); 2486 if (!pc->temp) 2487 return FALSE; 2488 2489 for (i = 0; i < pc->temp_nr * 4; ++i) 2490 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1); 2491 } 2492 2493 if (pc->attr_nr) { 2494 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg)); 2495 if (!pc->attr) 2496 return FALSE; 2497 2498 for (i = 0; i < pc->attr_nr * 4; ++i) 2499 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1); 2500 } 2501 2502 if (pc->result_nr) { 2503 unsigned nr = pc->result_nr * 4; 2504 2505 pc->result = MALLOC(nr * sizeof(struct nv50_reg)); 2506 if (!pc->result) 2507 return FALSE; 2508 2509 for (i = 0; i < nr; ++i) 2510 ctor_reg(&pc->result[i], rtype[1], i / 4, -1); 2511 } 2512 2513 if (pc->param_nr) { 2514 int rid = 0; 2515 2516 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg)); 2517 if (!pc->param) 2518 return FALSE; 2519 2520 for (i = 0; i < pc->param_nr; ++i) 2521 for (c = 0; c < 4; ++c, ++rid) 2522 ctor_reg(&pc->param[rid], P_CONST, i, rid); 2523 } 2524 2525 return TRUE; 2526} 2527 2528static void 2529nv50_fp_move_results(struct nv50_pc *pc) 2530{ 2531 struct nv50_reg reg; 2532 unsigned i; 2533 2534 ctor_reg(®, P_TEMP, -1, -1); 2535 2536 for (i = 0; i < pc->result_nr * 4; ++i) { 2537 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0) 2538 continue; 2539 if (pc->result[i].rhw != pc->result[i].hw) { 2540 reg.hw = pc->result[i].rhw; 2541 emit_mov(pc, ®, &pc->result[i]); 2542 } 2543 } 2544} 2545 2546static void 2547nv50_program_fixup_insns(struct nv50_pc *pc) 2548{ 2549 struct nv50_program_exec *e, *prev = NULL, **bra_list; 2550 unsigned i, n, pos; 2551 2552 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *)); 2553 2554 /* Collect branch instructions, we need to adjust their offsets 2555 * when converting 32 bit instructions to 64 bit ones 2556 */ 2557 for (n = 0, e = pc->p->exec_head; e; e = e->next) 2558 if (e->param.index >= 0 && !e->param.mask) 2559 bra_list[n++] = e; 2560 2561 /* Make sure we don't have any single 32 bit instructions. */ 2562 for (e = pc->p->exec_head, pos = 0; e; e = e->next) { 2563 pos += is_long(e) ? 2 : 1; 2564 2565 if ((pos & 1) && (!e->next || is_long(e->next))) { 2566 for (i = 0; i < n; ++i) 2567 if (bra_list[i]->param.index >= pos) 2568 bra_list[i]->param.index += 1; 2569 convert_to_long(pc, e); 2570 ++pos; 2571 } 2572 if (e->next) 2573 prev = e; 2574 } 2575 2576 assert(!is_immd(pc->p->exec_head)); 2577 assert(!is_immd(pc->p->exec_tail)); 2578 2579 /* last instruction must be long so it can have the end bit set */ 2580 if (!is_long(pc->p->exec_tail)) { 2581 convert_to_long(pc, pc->p->exec_tail); 2582 if (prev) 2583 convert_to_long(pc, prev); 2584 } 2585 assert(!(pc->p->exec_tail->inst[1] & 2)); 2586 /* set the end-bit */ 2587 pc->p->exec_tail->inst[1] |= 1; 2588 2589 FREE(bra_list); 2590} 2591 2592static boolean 2593nv50_program_tx(struct nv50_program *p) 2594{ 2595 struct tgsi_parse_context parse; 2596 struct nv50_pc *pc; 2597 boolean ret; 2598 2599 pc = CALLOC_STRUCT(nv50_pc); 2600 if (!pc) 2601 return FALSE; 2602 2603 ret = ctor_nv50_pc(pc, p); 2604 if (ret == FALSE) 2605 goto out_cleanup; 2606 2607 ret = nv50_program_tx_prep(pc); 2608 if (ret == FALSE) 2609 goto out_cleanup; 2610 2611 tgsi_parse_init(&parse, pc->p->pipe.tokens); 2612 while (!tgsi_parse_end_of_tokens(&parse)) { 2613 const union tgsi_full_token *tok = &parse.FullToken; 2614 2615 /* don't allow half insn/immd on first and last instruction */ 2616 pc->allow32 = TRUE; 2617 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr) 2618 pc->allow32 = FALSE; 2619 2620 tgsi_parse_token(&parse); 2621 2622 switch (tok->Token.Type) { 2623 case TGSI_TOKEN_TYPE_INSTRUCTION: 2624 ++pc->insn_cur; 2625 ret = nv50_tgsi_insn(pc, tok); 2626 if (ret == FALSE) 2627 goto out_err; 2628 break; 2629 default: 2630 break; 2631 } 2632 } 2633 2634 if (pc->p->type == PIPE_SHADER_FRAGMENT) 2635 nv50_fp_move_results(pc); 2636 2637 nv50_program_fixup_insns(pc); 2638 2639 p->param_nr = pc->param_nr * 4; 2640 p->immd_nr = pc->immd_nr * 4; 2641 p->immd = pc->immd_buf; 2642 2643out_err: 2644 tgsi_parse_free(&parse); 2645 2646out_cleanup: 2647 free_nv50_pc(pc); 2648 return ret; 2649} 2650 2651static void 2652nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p) 2653{ 2654 if (nv50_program_tx(p) == FALSE) 2655 assert(0); 2656 p->translated = TRUE; 2657} 2658 2659static void 2660nv50_program_upload_data(struct nv50_context *nv50, float *map, 2661 unsigned start, unsigned count, unsigned cbuf) 2662{ 2663 struct nouveau_channel *chan = nv50->screen->base.channel; 2664 struct nouveau_grobj *tesla = nv50->screen->tesla; 2665 2666 while (count) { 2667 unsigned nr = count > 2047 ? 2047 : count; 2668 2669 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1); 2670 OUT_RING (chan, (cbuf << 0) | (start << 8)); 2671 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr); 2672 OUT_RINGp (chan, map, nr); 2673 2674 map += nr; 2675 start += nr; 2676 count -= nr; 2677 } 2678} 2679 2680static void 2681nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p) 2682{ 2683 struct pipe_screen *pscreen = nv50->pipe.screen; 2684 2685 if (!p->data[0] && p->immd_nr) { 2686 struct nouveau_resource *heap = nv50->screen->immd_heap[0]; 2687 2688 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) { 2689 while (heap->next && heap->size < p->immd_nr) { 2690 struct nv50_program *evict = heap->next->priv; 2691 nouveau_resource_free(&evict->data[0]); 2692 } 2693 2694 if (nouveau_resource_alloc(heap, p->immd_nr, p, 2695 &p->data[0])) 2696 assert(0); 2697 } 2698 2699 /* immediates only need to be uploaded again when freed */ 2700 nv50_program_upload_data(nv50, p->immd, p->data[0]->start, 2701 p->immd_nr, NV50_CB_PMISC); 2702 } 2703 2704 assert(p->param_nr <= 128); 2705 2706 if (p->param_nr) { 2707 unsigned cb; 2708 float *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type], 2709 PIPE_BUFFER_USAGE_CPU_READ); 2710 2711 if (p->type == PIPE_SHADER_VERTEX) 2712 cb = NV50_CB_PVP; 2713 else 2714 cb = NV50_CB_PFP; 2715 2716 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb); 2717 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]); 2718 } 2719} 2720 2721static void 2722nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p) 2723{ 2724 struct nouveau_channel *chan = nv50->screen->base.channel; 2725 struct nouveau_grobj *tesla = nv50->screen->tesla; 2726 struct nv50_program_exec *e; 2727 struct nouveau_stateobj *so; 2728 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR; 2729 unsigned start, count, *up, *ptr; 2730 boolean upload = FALSE; 2731 2732 if (!p->bo) { 2733 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100, 2734 p->exec_size * 4, &p->bo); 2735 upload = TRUE; 2736 } 2737 2738 if (p->data[0] && p->data[0]->start != p->data_start[0]) 2739 upload = TRUE; 2740 2741 if (!upload) 2742 return; 2743 2744 for (e = p->exec_head; e; e = e->next) { 2745 unsigned ei, ci, bs; 2746 2747 if (e->param.index < 0) 2748 continue; 2749 2750 if (e->param.mask == 0) { 2751 assert(!(e->param.index & 1)); 2752 /* seem to be 8 byte steps */ 2753 ei = (e->param.index >> 1) + 0 /* START_ID */; 2754 2755 e->inst[0] &= 0xf0000fff; 2756 e->inst[0] |= ei << 12; 2757 continue; 2758 } 2759 2760 bs = (e->inst[1] >> 22) & 0x07; 2761 assert(bs < 2); 2762 ei = e->param.shift >> 5; 2763 ci = e->param.index; 2764 if (bs == 0) 2765 ci += p->data[bs]->start; 2766 2767 e->inst[ei] &= ~e->param.mask; 2768 e->inst[ei] |= (ci << e->param.shift); 2769 } 2770 2771 if (p->data[0]) 2772 p->data_start[0] = p->data[0]->start; 2773 2774#ifdef NV50_PROGRAM_DUMP 2775 NOUVEAU_ERR("-------\n"); 2776 for (e = p->exec_head; e; e = e->next) { 2777 NOUVEAU_ERR("0x%08x\n", e->inst[0]); 2778 if (is_long(e)) 2779 NOUVEAU_ERR("0x%08x\n", e->inst[1]); 2780 } 2781#endif 2782 2783 up = ptr = MALLOC(p->exec_size * 4); 2784 for (e = p->exec_head; e; e = e->next) { 2785 *(ptr++) = e->inst[0]; 2786 if (is_long(e)) 2787 *(ptr++) = e->inst[1]; 2788 } 2789 2790 so = so_new(4,2); 2791 so_method(so, nv50->screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); 2792 so_reloc (so, p->bo, 0, flags | NOUVEAU_BO_HIGH, 0, 0); 2793 so_reloc (so, p->bo, 0, flags | NOUVEAU_BO_LOW, 0, 0); 2794 so_data (so, (NV50_CB_PUPLOAD << 16) | 0x0800); //(p->exec_size * 4)); 2795 2796 start = 0; count = p->exec_size; 2797 while (count) { 2798 struct nouveau_channel *chan = nv50->screen->base.channel; 2799 unsigned nr; 2800 2801 so_emit(chan, so); 2802 2803 nr = MIN2(count, 2047); 2804 nr = MIN2(chan->pushbuf->remaining, nr); 2805 if (chan->pushbuf->remaining < (nr + 3)) { 2806 FIRE_RING(chan); 2807 continue; 2808 } 2809 2810 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1); 2811 OUT_RING (chan, (start << 8) | NV50_CB_PUPLOAD); 2812 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr); 2813 OUT_RINGp (chan, up + start, nr); 2814 2815 start += nr; 2816 count -= nr; 2817 } 2818 2819 FREE(up); 2820 so_ref(NULL, &so); 2821} 2822 2823void 2824nv50_vertprog_validate(struct nv50_context *nv50) 2825{ 2826 struct nouveau_grobj *tesla = nv50->screen->tesla; 2827 struct nv50_program *p = nv50->vertprog; 2828 struct nouveau_stateobj *so; 2829 2830 if (!p->translated) { 2831 nv50_program_validate(nv50, p); 2832 if (!p->translated) 2833 assert(0); 2834 } 2835 2836 nv50_program_validate_data(nv50, p); 2837 nv50_program_validate_code(nv50, p); 2838 2839 so = so_new(13, 2); 2840 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2); 2841 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 2842 NOUVEAU_BO_HIGH, 0, 0); 2843 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 2844 NOUVEAU_BO_LOW, 0, 0); 2845 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2); 2846 so_data (so, p->cfg.attr[0]); 2847 so_data (so, p->cfg.attr[1]); 2848 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1); 2849 so_data (so, p->cfg.high_result); 2850 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2); 2851 so_data (so, p->cfg.high_result); //8); 2852 so_data (so, p->cfg.high_temp); 2853 so_method(so, tesla, NV50TCL_VP_START_ID, 1); 2854 so_data (so, 0); /* program start offset */ 2855 so_ref(so, &nv50->state.vertprog); 2856 so_ref(NULL, &so); 2857} 2858 2859void 2860nv50_fragprog_validate(struct nv50_context *nv50) 2861{ 2862 struct nouveau_grobj *tesla = nv50->screen->tesla; 2863 struct nv50_program *p = nv50->fragprog; 2864 struct nouveau_stateobj *so; 2865 2866 if (!p->translated) { 2867 nv50_program_validate(nv50, p); 2868 if (!p->translated) 2869 assert(0); 2870 } 2871 2872 nv50_program_validate_data(nv50, p); 2873 nv50_program_validate_code(nv50, p); 2874 2875 so = so_new(64, 2); 2876 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2); 2877 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 2878 NOUVEAU_BO_HIGH, 0, 0); 2879 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 2880 NOUVEAU_BO_LOW, 0, 0); 2881 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1); 2882 so_data (so, p->cfg.high_temp); 2883 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1); 2884 so_data (so, p->cfg.high_result); 2885 so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1); 2886 so_data (so, p->cfg.regs[2]); 2887 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1); 2888 so_data (so, p->cfg.regs[3]); 2889 so_method(so, tesla, NV50TCL_FP_START_ID, 1); 2890 so_data (so, 0); /* program start offset */ 2891 so_ref(so, &nv50->state.fragprog); 2892 so_ref(NULL, &so); 2893} 2894 2895static void 2896nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base) 2897{ 2898 struct nv50_program *fp = nv50->fragprog; 2899 struct nv50_program *vp = nv50->vertprog; 2900 unsigned i, c, m = base; 2901 2902 /* XXX: This can't work correctly in all cases yet, we either 2903 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has 2904 * to be per FP input instead of per VP output 2905 */ 2906 memset(pntc, 0, 8 * sizeof(uint32_t)); 2907 2908 for (i = 0; i < fp->cfg.io_nr; i++) { 2909 uint8_t sn, si; 2910 uint8_t j = fp->cfg.io[i].id_vp, k = fp->cfg.io[i].id_fp; 2911 unsigned n = popcnt4(fp->cfg.io[i].mask); 2912 2913 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) { 2914 m += n; 2915 continue; 2916 } 2917 2918 sn = vp->info.input_semantic_name[j]; 2919 si = vp->info.input_semantic_index[j]; 2920 2921 if (j < fp->cfg.io_nr && sn == TGSI_SEMANTIC_GENERIC) { 2922 ubyte mode = 2923 nv50->rasterizer->pipe.sprite_coord_mode[si]; 2924 2925 if (mode == PIPE_SPRITE_COORD_NONE) { 2926 m += n; 2927 continue; 2928 } 2929 } 2930 2931 /* this is either PointCoord or replaced by sprite coords */ 2932 for (c = 0; c < 4; c++) { 2933 if (!(fp->cfg.io[i].mask & (1 << c))) 2934 continue; 2935 pntc[m / 8] |= (c + 1) << ((m % 8) * 4); 2936 ++m; 2937 } 2938 } 2939} 2940 2941static int 2942nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4], 2943 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo) 2944{ 2945 int c; 2946 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw; 2947 uint8_t *map = (uint8_t *)p_map; 2948 2949 for (c = 0; c < 4; ++c) { 2950 if (mf & 1) { 2951 if (fpi->linear == TRUE) 2952 lin[mid / 32] |= 1 << (mid % 32); 2953 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40); 2954 } 2955 2956 oid += mv & 1; 2957 mf >>= 1; 2958 mv >>= 1; 2959 } 2960 2961 return mid; 2962} 2963 2964void 2965nv50_linkage_validate(struct nv50_context *nv50) 2966{ 2967 struct nouveau_grobj *tesla = nv50->screen->tesla; 2968 struct nv50_program *vp = nv50->vertprog; 2969 struct nv50_program *fp = nv50->fragprog; 2970 struct nouveau_stateobj *so; 2971 struct nv50_sreg4 dummy, *vpo; 2972 int i, n, c, m = 0; 2973 uint32_t map[16], lin[4], reg[5], pcrd[8]; 2974 2975 memset(map, 0, sizeof(map)); 2976 memset(lin, 0, sizeof(lin)); 2977 2978 reg[1] = 0x00000004; /* low and high clip distance map ids */ 2979 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */ 2980 reg[3] = 0x00000000; /* point size map id & enable */ 2981 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */ 2982 reg[4] = fp->cfg.regs[1]; /* interpolant info */ 2983 2984 dummy.linear = FALSE; 2985 dummy.mask = 0xf; /* map all components of HPOS */ 2986 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]); 2987 2988 dummy.mask = 0x0; 2989 2990 if (vp->cfg.clpd < 0x40) { 2991 for (c = 0; c < vp->cfg.clpd_nr; ++c) 2992 map[m++] = vp->cfg.clpd + c; 2993 reg[1] = (m << 8); 2994 } 2995 2996 reg[0] |= m << 8; /* adjust BFC0 id */ 2997 2998 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */ 2999 if (nv50->rasterizer->pipe.light_twoside) { 3000 vpo = &vp->cfg.two_side[0]; 3001 3002 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]); 3003 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]); 3004 } 3005 3006 reg[0] += m - 4; /* adjust FFC0 id */ 3007 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */ 3008 3009 i = 0; 3010 if (fp->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) 3011 i = 1; 3012 for (; i < fp->cfg.io_nr; i++) { 3013 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id_fp]; 3014 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id_fp]; 3015 3016 n = fp->cfg.io[i].id_vp; 3017 if (n >= vp->cfg.io_nr || 3018 vp->info.output_semantic_name[n] != sn || 3019 vp->info.output_semantic_index[n] != si) 3020 vpo = &dummy; 3021 else 3022 vpo = &vp->cfg.io[n]; 3023 3024 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo); 3025 } 3026 3027 if (nv50->rasterizer->pipe.point_size_per_vertex) { 3028 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8); 3029 reg[3] = (m++ << 4) | 1; 3030 } 3031 3032 /* now fill the stateobj */ 3033 so = so_new(64, 0); 3034 3035 n = (m + 3) / 4; 3036 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1); 3037 so_data (so, m); 3038 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n); 3039 so_datap (so, map, n); 3040 3041 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4); 3042 so_datap (so, reg, 4); 3043 3044 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1); 3045 so_data (so, reg[4]); 3046 3047 so_method(so, tesla, 0x1540, 4); 3048 so_datap (so, lin, 4); 3049 3050 if (nv50->rasterizer->pipe.point_sprite) { 3051 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff); 3052 3053 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8); 3054 so_datap (so, pcrd, 8); 3055 } 3056 3057 so_ref(so, &nv50->state.programs); 3058 so_ref(NULL, &so); 3059} 3060 3061void 3062nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p) 3063{ 3064 while (p->exec_head) { 3065 struct nv50_program_exec *e = p->exec_head; 3066 3067 p->exec_head = e->next; 3068 FREE(e); 3069 } 3070 p->exec_tail = NULL; 3071 p->exec_size = 0; 3072 3073 nouveau_bo_ref(NULL, &p->bo); 3074 3075 nouveau_resource_free(&p->data[0]); 3076 3077 p->translated = 0; 3078} 3079