r300_state.c revision bdb811772fe1b11e32172b211d9935d37093c753
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_framebuffer.h" 27#include "util/u_half.h" 28#include "util/u_math.h" 29#include "util/u_mm.h" 30#include "util/u_memory.h" 31#include "util/u_pack_color.h" 32#include "util/u_transfer.h" 33 34#include "tgsi/tgsi_parse.h" 35 36#include "pipe/p_config.h" 37 38#include "r300_cb.h" 39#include "r300_context.h" 40#include "r300_emit.h" 41#include "r300_reg.h" 42#include "r300_screen.h" 43#include "r300_screen_buffer.h" 44#include "r300_state_inlines.h" 45#include "r300_fs.h" 46#include "r300_texture.h" 47#include "r300_vs.h" 48#include "r300_winsys.h" 49 50/* r300_state: Functions used to intialize state context by translating 51 * Gallium state objects into semi-native r300 state objects. */ 52 53#define UPDATE_STATE(cso, atom) \ 54 if (cso != atom.state) { \ 55 atom.state = cso; \ 56 r300_mark_atom_dirty(r300, &(atom)); \ 57 } 58 59static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 60 unsigned dstRGB, unsigned dstA) 61{ 62 /* If the blend equation is ADD or REVERSE_SUBTRACT, 63 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 64 * will not be changed. 65 * Notice that the dst factors are the src factors inverted. */ 66 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 67 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 68 srcRGB == PIPE_BLENDFACTOR_ZERO) && 69 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 71 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 72 srcA == PIPE_BLENDFACTOR_ZERO) && 73 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 74 dstRGB == PIPE_BLENDFACTOR_ONE) && 75 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 76 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 77 dstA == PIPE_BLENDFACTOR_ONE); 78} 79 80static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 81 unsigned dstRGB, unsigned dstA) 82{ 83 /* If the blend equation is ADD or REVERSE_SUBTRACT, 84 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 85 * will not be changed. 86 * Notice that the dst factors are the src factors inverted. */ 87 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 88 srcRGB == PIPE_BLENDFACTOR_ZERO) && 89 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 90 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 91 srcA == PIPE_BLENDFACTOR_ZERO) && 92 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 93 dstRGB == PIPE_BLENDFACTOR_ONE) && 94 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 95 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 96 dstA == PIPE_BLENDFACTOR_ONE); 97} 98 99static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 100 unsigned dstRGB, unsigned dstA) 101{ 102 /* If the blend equation is ADD or REVERSE_SUBTRACT, 103 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 104 * will not be changed. 105 * Notice that the dst factors are the src factors inverted. */ 106 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 107 srcRGB == PIPE_BLENDFACTOR_ZERO) && 108 (srcA == PIPE_BLENDFACTOR_ZERO) && 109 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 110 dstRGB == PIPE_BLENDFACTOR_ONE) && 111 (dstA == PIPE_BLENDFACTOR_ONE); 112} 113 114static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 115 unsigned dstRGB, unsigned dstA) 116{ 117 /* If the blend equation is ADD or REVERSE_SUBTRACT, 118 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 119 * will not be changed. 120 * Notice that the dst factors are the src factors inverted. */ 121 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 122 srcRGB == PIPE_BLENDFACTOR_ZERO) && 123 (srcA == PIPE_BLENDFACTOR_ZERO) && 124 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 125 dstRGB == PIPE_BLENDFACTOR_ONE) && 126 (dstA == PIPE_BLENDFACTOR_ONE); 127} 128 129static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 130 unsigned dstRGB, unsigned dstA) 131{ 132 /* If the blend equation is ADD or REVERSE_SUBTRACT, 133 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 134 * the colorbuffer will not be changed. 135 * Notice that the dst factors are the src factors inverted. */ 136 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 138 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 139 srcRGB == PIPE_BLENDFACTOR_ZERO) && 140 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 142 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 143 srcA == PIPE_BLENDFACTOR_ZERO) && 144 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 145 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 146 dstRGB == PIPE_BLENDFACTOR_ONE) && 147 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 148 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 149 dstA == PIPE_BLENDFACTOR_ONE); 150} 151 152static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 153 unsigned dstRGB, unsigned dstA) 154{ 155 /* If the blend equation is ADD or REVERSE_SUBTRACT, 156 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 157 * the colorbuffer will not be changed. 158 * Notice that the dst factors are the src factors inverted. */ 159 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 160 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 161 srcRGB == PIPE_BLENDFACTOR_ZERO) && 162 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 163 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 164 srcA == PIPE_BLENDFACTOR_ZERO) && 165 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 166 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 167 dstRGB == PIPE_BLENDFACTOR_ONE) && 168 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 169 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 170 dstA == PIPE_BLENDFACTOR_ONE); 171} 172 173static unsigned bgra_cmask(unsigned mask) 174{ 175 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 176 177 return ((mask & PIPE_MASK_R) << 2) | 178 ((mask & PIPE_MASK_B) >> 2) | 179 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 180} 181 182/* Create a new blend state based on the CSO blend state. 183 * 184 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 185static void* r300_create_blend_state(struct pipe_context* pipe, 186 const struct pipe_blend_state* state) 187{ 188 struct r300_screen* r300screen = r300_screen(pipe->screen); 189 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 190 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 191 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 192 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 193 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 194 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 195 boolean clamp = TRUE; 196 CB_LOCALS; 197 198 if (state->rt[0].blend_enable) 199 { 200 unsigned eqRGB = state->rt[0].rgb_func; 201 unsigned srcRGB = state->rt[0].rgb_src_factor; 202 unsigned dstRGB = state->rt[0].rgb_dst_factor; 203 204 unsigned eqA = state->rt[0].alpha_func; 205 unsigned srcA = state->rt[0].alpha_src_factor; 206 unsigned dstA = state->rt[0].alpha_dst_factor; 207 208 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 209 * this is just the crappy D3D naming */ 210 blend_control = R300_ALPHA_BLEND_ENABLE | 211 r300_translate_blend_function(eqRGB, clamp) | 212 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 213 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 214 215 /* Optimization: some operations do not require the destination color. 216 * 217 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 218 * otherwise blending gives incorrect results. It seems to be 219 * a hardware bug. */ 220 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 221 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 222 dstRGB != PIPE_BLENDFACTOR_ZERO || 223 dstA != PIPE_BLENDFACTOR_ZERO || 224 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 225 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 226 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 227 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 228 srcA == PIPE_BLENDFACTOR_DST_COLOR || 229 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 230 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 231 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 232 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 233 /* Enable reading from the colorbuffer. */ 234 blend_control |= R300_READ_ENABLE; 235 236 if (r300screen->caps.is_r500) { 237 /* Optimization: Depending on incoming pixels, we can 238 * conditionally disable the reading in hardware... */ 239 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 240 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 241 /* Disable reading if SRC_ALPHA == 0. */ 242 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 243 dstRGB == PIPE_BLENDFACTOR_ZERO) && 244 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 245 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 246 dstA == PIPE_BLENDFACTOR_ZERO)) { 247 blend_control |= R500_SRC_ALPHA_0_NO_READ; 248 } 249 250 /* Disable reading if SRC_ALPHA == 1. */ 251 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 252 dstRGB == PIPE_BLENDFACTOR_ZERO) && 253 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 254 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 255 dstA == PIPE_BLENDFACTOR_ZERO)) { 256 blend_control |= R500_SRC_ALPHA_1_NO_READ; 257 } 258 } 259 } 260 } 261 262 /* Optimization: discard pixels which don't change the colorbuffer. 263 * 264 * The code below is non-trivial and some math is involved. 265 * 266 * Discarding pixels must be disabled when FP16 AA is enabled. 267 * This is a hardware bug. Also, this implementation wouldn't work 268 * with FP blending enabled and equation clamping disabled. 269 * 270 * Equations other than ADD are rarely used and therefore won't be 271 * optimized. */ 272 if (clamp && 273 (eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 274 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 275 /* ADD: X+Y 276 * REVERSE_SUBTRACT: Y-X 277 * 278 * The idea is: 279 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 280 * then CB will not be changed. 281 * 282 * Given the srcFactor and dstFactor variables, we can derive 283 * what src and dst should be equal to and discard appropriate 284 * pixels. 285 */ 286 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 287 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 288 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 289 dstRGB, dstA)) { 290 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 291 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 292 dstRGB, dstA)) { 293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 294 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 295 dstRGB, dstA)) { 296 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 297 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 298 dstRGB, dstA)) { 299 blend_control |= 300 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 301 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 302 dstRGB, dstA)) { 303 blend_control |= 304 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 305 } 306 } 307 308 /* separate alpha */ 309 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 310 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 311 alpha_blend_control = 312 r300_translate_blend_function(eqA, clamp) | 313 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 314 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 315 } 316 } 317 318 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 319 if (state->logicop_enable) { 320 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 321 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 322 } 323 324 /* Color channel masks for all MRTs. */ 325 color_channel_mask = bgra_cmask(state->rt[0].colormask); 326 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 327 if (state->rt[1].blend_enable) { 328 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 329 } 330 if (state->rt[2].blend_enable) { 331 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 332 } 333 if (state->rt[3].blend_enable) { 334 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 335 } 336 } 337 338 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 339 * state. Since it's an optional implementation detail, we can leave it 340 * out and never dither. 341 * 342 * This could be revisited if we ever get quality or conformance hints. 343 * 344 if (state->dither) { 345 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 346 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 347 } 348 */ 349 350 /* Build a command buffer. */ 351 BEGIN_CB(blend->cb, 8); 352 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 353 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 354 OUT_CB(blend_control); 355 OUT_CB(alpha_blend_control); 356 OUT_CB(color_channel_mask); 357 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 358 END_CB; 359 360 /* The same as above, but with no colorbuffer reads and writes. */ 361 BEGIN_CB(blend->cb_no_readwrite, 8); 362 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 363 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 364 OUT_CB(0); 365 OUT_CB(0); 366 OUT_CB(0); 367 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 368 END_CB; 369 370 return (void*)blend; 371} 372 373/* Bind blend state. */ 374static void r300_bind_blend_state(struct pipe_context* pipe, 375 void* state) 376{ 377 struct r300_context* r300 = r300_context(pipe); 378 379 UPDATE_STATE(state, r300->blend_state); 380} 381 382/* Free blend state. */ 383static void r300_delete_blend_state(struct pipe_context* pipe, 384 void* state) 385{ 386 FREE(state); 387} 388 389/* Convert float to 10bit integer */ 390static unsigned float_to_fixed10(float f) 391{ 392 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 393} 394 395/* Set blend color. 396 * Setup both R300 and R500 registers, figure out later which one to write. */ 397static void r300_set_blend_color(struct pipe_context* pipe, 398 const struct pipe_blend_color* color) 399{ 400 struct r300_context* r300 = r300_context(pipe); 401 struct pipe_framebuffer_state *fb = r300->fb_state.state; 402 struct r300_blend_color_state *state = 403 (struct r300_blend_color_state*)r300->blend_color_state.state; 404 struct pipe_blend_color c; 405 enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0; 406 CB_LOCALS; 407 408 state->state = *color; /* Save it, so that we can reuse it in set_fb_state */ 409 c = *color; 410 411 /* The blend color is dependent on the colorbuffer format. */ 412 if (fb->nr_cbufs) { 413 switch (format) { 414 case PIPE_FORMAT_R8_UNORM: 415 case PIPE_FORMAT_L8_UNORM: 416 case PIPE_FORMAT_I8_UNORM: 417 c.color[1] = c.color[0]; 418 break; 419 420 case PIPE_FORMAT_A8_UNORM: 421 c.color[1] = c.color[3]; 422 break; 423 424 case PIPE_FORMAT_R8G8_UNORM: 425 c.color[2] = c.color[1]; 426 break; 427 428 case PIPE_FORMAT_L8A8_UNORM: 429 c.color[2] = c.color[3]; 430 break; 431 432 default:; 433 } 434 } 435 436 if (r300->screen->caps.is_r500) { 437 BEGIN_CB(state->cb, 3); 438 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 439 440 switch (format) { 441 case PIPE_FORMAT_R16G16B16A16_FLOAT: 442 OUT_CB(util_float_to_half(c.color[2]) | 443 (util_float_to_half(c.color[3]) << 16)); 444 OUT_CB(util_float_to_half(c.color[0]) | 445 (util_float_to_half(c.color[1]) << 16)); 446 break; 447 448 default: 449 OUT_CB(float_to_fixed10(c.color[0]) | 450 (float_to_fixed10(c.color[3]) << 16)); 451 OUT_CB(float_to_fixed10(c.color[2]) | 452 (float_to_fixed10(c.color[1]) << 16)); 453 } 454 455 END_CB; 456 } else { 457 union util_color uc; 458 util_pack_color(c.color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 459 460 BEGIN_CB(state->cb, 2); 461 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 462 END_CB; 463 } 464 465 r300_mark_atom_dirty(r300, &r300->blend_color_state); 466} 467 468static void r300_set_clip_state(struct pipe_context* pipe, 469 const struct pipe_clip_state* state) 470{ 471 struct r300_context* r300 = r300_context(pipe); 472 struct r300_clip_state *clip = 473 (struct r300_clip_state*)r300->clip_state.state; 474 CB_LOCALS; 475 476 clip->clip = *state; 477 478 if (r300->screen->caps.has_tcl) { 479 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4; 480 481 BEGIN_CB(clip->cb, r300->clip_state.size); 482 if (state->nr) { 483 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 484 (r300->screen->caps.is_r500 ? 485 R500_PVS_UCP_START : R300_PVS_UCP_START)); 486 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4); 487 OUT_CB_TABLE(state->ucp, state->nr * 4); 488 } 489 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) | 490 R300_PS_UCP_MODE_CLIP_AS_TRIFAN); 491 END_CB; 492 493 r300_mark_atom_dirty(r300, &r300->clip_state); 494 } else { 495 draw_set_clip_state(r300->draw, state); 496 } 497} 498 499static void 500r300_set_sample_mask(struct pipe_context *pipe, 501 unsigned sample_mask) 502{ 503} 504 505 506/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 507 * 508 * This contains the depth buffer, stencil buffer, alpha test, and such. 509 * On the Radeon, depth and stencil buffer setup are intertwined, which is 510 * the reason for some of the strange-looking assignments across registers. */ 511static void* 512 r300_create_dsa_state(struct pipe_context* pipe, 513 const struct pipe_depth_stencil_alpha_state* state) 514{ 515 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 516 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 517 CB_LOCALS; 518 519 dsa->dsa = *state; 520 521 /* Depth test setup. - separate write mask depth for decomp flush */ 522 if (state->depth.writemask) { 523 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 524 } 525 526 if (state->depth.enabled) { 527 dsa->z_buffer_control |= R300_Z_ENABLE; 528 529 dsa->z_stencil_control |= 530 (r300_translate_depth_stencil_function(state->depth.func) << 531 R300_Z_FUNC_SHIFT); 532 } 533 534 /* Stencil buffer setup. */ 535 if (state->stencil[0].enabled) { 536 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 537 dsa->z_stencil_control |= 538 (r300_translate_depth_stencil_function(state->stencil[0].func) << 539 R300_S_FRONT_FUNC_SHIFT) | 540 (r300_translate_stencil_op(state->stencil[0].fail_op) << 541 R300_S_FRONT_SFAIL_OP_SHIFT) | 542 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 543 R300_S_FRONT_ZPASS_OP_SHIFT) | 544 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 545 R300_S_FRONT_ZFAIL_OP_SHIFT); 546 547 dsa->stencil_ref_mask = 548 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 549 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 550 551 if (state->stencil[1].enabled) { 552 dsa->two_sided = TRUE; 553 554 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 555 dsa->z_stencil_control |= 556 (r300_translate_depth_stencil_function(state->stencil[1].func) << 557 R300_S_BACK_FUNC_SHIFT) | 558 (r300_translate_stencil_op(state->stencil[1].fail_op) << 559 R300_S_BACK_SFAIL_OP_SHIFT) | 560 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 561 R300_S_BACK_ZPASS_OP_SHIFT) | 562 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 563 R300_S_BACK_ZFAIL_OP_SHIFT); 564 565 dsa->stencil_ref_bf = 566 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 567 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 568 569 if (caps->is_r500) { 570 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 571 } else { 572 dsa->two_sided_stencil_ref = 573 (state->stencil[0].valuemask != state->stencil[1].valuemask || 574 state->stencil[0].writemask != state->stencil[1].writemask); 575 } 576 } 577 } 578 579 /* Alpha test setup. */ 580 if (state->alpha.enabled) { 581 dsa->alpha_function = 582 r300_translate_alpha_function(state->alpha.func) | 583 R300_FG_ALPHA_FUNC_ENABLE; 584 585 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 586 dsa->alpha_value = util_float_to_half(state->alpha.ref_value); 587 588 if (caps->is_r500) { 589 dsa->alpha_function_fp16 = dsa->alpha_function | 590 R500_FG_ALPHA_FUNC_FP16_ENABLE; 591 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 592 } 593 } 594 595 BEGIN_CB(&dsa->cb_begin, 10); 596 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 597 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 598 OUT_CB(dsa->z_buffer_control); 599 OUT_CB(dsa->z_stencil_control); 600 OUT_CB(dsa->stencil_ref_mask); 601 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 602 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value); 603 END_CB; 604 605 BEGIN_CB(&dsa->cb_begin_fp16, 10); 606 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16); 607 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 608 OUT_CB(dsa->z_buffer_control); 609 OUT_CB(dsa->z_stencil_control); 610 OUT_CB(dsa->stencil_ref_mask); 611 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 612 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value); 613 END_CB; 614 615 BEGIN_CB(dsa->cb_zb_no_readwrite, 10); 616 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 617 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 618 OUT_CB(0); 619 OUT_CB(0); 620 OUT_CB(0); 621 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 622 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value); 623 END_CB; 624 625 BEGIN_CB(dsa->cb_fp16_zb_no_readwrite, 10); 626 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16); 627 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 628 OUT_CB(0); 629 OUT_CB(0); 630 OUT_CB(0); 631 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 632 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value); 633 END_CB; 634 635 return (void*)dsa; 636} 637 638static void r300_dsa_inject_stencilref(struct r300_context *r300) 639{ 640 struct r300_dsa_state *dsa = 641 (struct r300_dsa_state*)r300->dsa_state.state; 642 643 if (!dsa) 644 return; 645 646 dsa->stencil_ref_mask = 647 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 648 r300->stencil_ref.ref_value[0]; 649 dsa->stencil_ref_bf = 650 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 651 r300->stencil_ref.ref_value[1]; 652} 653 654/* Bind DSA state. */ 655static void r300_bind_dsa_state(struct pipe_context* pipe, 656 void* state) 657{ 658 struct r300_context* r300 = r300_context(pipe); 659 660 if (!state) { 661 return; 662 } 663 664 UPDATE_STATE(state, r300->dsa_state); 665 666 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */ 667 r300_dsa_inject_stencilref(r300); 668} 669 670/* Free DSA state. */ 671static void r300_delete_dsa_state(struct pipe_context* pipe, 672 void* state) 673{ 674 FREE(state); 675} 676 677static void r300_set_stencil_ref(struct pipe_context* pipe, 678 const struct pipe_stencil_ref* sr) 679{ 680 struct r300_context* r300 = r300_context(pipe); 681 682 r300->stencil_ref = *sr; 683 684 r300_dsa_inject_stencilref(r300); 685 r300_mark_atom_dirty(r300, &r300->dsa_state); 686} 687 688static void r300_tex_set_tiling_flags(struct r300_context *r300, 689 struct r300_resource *tex, 690 unsigned level) 691{ 692 /* Check if the macrotile flag needs to be changed. 693 * Skip changing the flags otherwise. */ 694 if (tex->tex.macrotile[tex->surface_level] != 695 tex->tex.macrotile[level]) { 696 r300->rws->buffer_set_tiling(tex->buf, r300->cs, 697 tex->tex.microtile, tex->tex.macrotile[level], 698 tex->tex.stride_in_bytes[0]); 699 700 tex->surface_level = level; 701 } 702} 703 704/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 705static void r300_fb_set_tiling_flags(struct r300_context *r300, 706 const struct pipe_framebuffer_state *state) 707{ 708 unsigned i; 709 710 /* Set tiling flags for new surfaces. */ 711 for (i = 0; i < state->nr_cbufs; i++) { 712 r300_tex_set_tiling_flags(r300, 713 r300_resource(state->cbufs[i]->texture), 714 state->cbufs[i]->u.tex.level); 715 } 716 if (state->zsbuf) { 717 r300_tex_set_tiling_flags(r300, 718 r300_resource(state->zsbuf->texture), 719 state->zsbuf->u.tex.level); 720 } 721} 722 723static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 724 const char *binding) 725{ 726 struct pipe_resource *tex = surf->texture; 727 struct r300_resource *rtex = r300_resource(tex); 728 729 fprintf(stderr, 730 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, " 731 "Lastlayer: %i, Level: %i, Format: %s\n" 732 733 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, " 734 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 735 736 binding, index, surf->width, surf->height, 737 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level, 738 util_format_short_name(surf->format), 739 740 rtex->tex.macrotile[0] ? "YES" : " NO", 741 rtex->tex.microtile ? "YES" : " NO", 742 rtex->tex.stride_in_pixels[0], 743 tex->width0, tex->height0, tex->depth0, 744 tex->last_level, util_format_short_name(tex->format)); 745} 746 747void r300_mark_fb_state_dirty(struct r300_context *r300, 748 enum r300_fb_state_change change) 749{ 750 struct pipe_framebuffer_state *state = r300->fb_state.state; 751 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ); 752 753 r300_mark_atom_dirty(r300, &r300->gpu_flush); 754 r300_mark_atom_dirty(r300, &r300->fb_state); 755 756 /* What is marked as dirty depends on the enum r300_fb_state_change. */ 757 if (change == R300_CHANGED_FB_STATE) { 758 r300_mark_atom_dirty(r300, &r300->aa_state); 759 r300_mark_atom_dirty(r300, &r300->dsa_state); /* for AlphaRef */ 760 r300_set_blend_color(&r300->context, r300->blend_color_state.state); 761 } 762 763 if (change == R300_CHANGED_FB_STATE || 764 change == R300_CHANGED_HYPERZ_FLAG) { 765 r300_mark_atom_dirty(r300, &r300->hyperz_state); 766 } 767 768 if (change == R300_CHANGED_FB_STATE || 769 change == R300_CHANGED_MULTIWRITE) { 770 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined); 771 } 772 773 /* Now compute the fb_state atom size. */ 774 r300->fb_state.size = 2 + (8 * state->nr_cbufs); 775 776 if (r300->cbzb_clear) 777 r300->fb_state.size += 10; 778 else if (state->zsbuf) { 779 r300->fb_state.size += 10; 780 if (can_hyperz) 781 r300->fb_state.size += 8; 782 } 783 784 /* The size of the rest of atoms stays the same. */ 785} 786 787static void 788r300_set_framebuffer_state(struct pipe_context* pipe, 789 const struct pipe_framebuffer_state* state) 790{ 791 struct r300_context* r300 = r300_context(pipe); 792 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 793 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 794 unsigned max_width, max_height, i; 795 uint32_t zbuffer_bpp = 0; 796 797 if (r300->screen->caps.is_r500) { 798 max_width = max_height = 4096; 799 } else if (r300->screen->caps.is_r400) { 800 max_width = max_height = 4021; 801 } else { 802 max_width = max_height = 2560; 803 } 804 805 if (state->width > max_width || state->height > max_height) { 806 fprintf(stderr, "r300: Implementation error: Render targets are too " 807 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 808 return; 809 } 810 811 if (old_state->zsbuf && r300->zmask_in_use && !r300->hyperz_locked) { 812 /* There is a zmask in use, what are we gonna do? */ 813 if (state->zsbuf) { 814 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) { 815 /* Decompress the currently bound zbuffer before we bind another one. */ 816 r300_decompress_zmask(r300); 817 r300->hiz_in_use = FALSE; 818 } 819 } else { 820 /* We don't bind another zbuffer, so lock the current one. */ 821 r300->hyperz_locked = TRUE; 822 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf); 823 } 824 } else if (r300->hyperz_locked && r300->locked_zbuffer) { 825 /* We have a locked zbuffer now, what are we gonna do? */ 826 if (state->zsbuf) { 827 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) { 828 /* We are binding some other zbuffer, so decompress the locked one, 829 * it gets unlocked automatically. */ 830 r300_decompress_zmask_locked_unsafe(r300); 831 r300->hiz_in_use = FALSE; 832 } else { 833 /* We are binding the locked zbuffer again, so unlock it. */ 834 r300->hyperz_locked = FALSE; 835 } 836 } 837 } 838 839 /* If nr_cbufs is changed from zero to non-zero or vice versa... */ 840 if (!!old_state->nr_cbufs != !!state->nr_cbufs) { 841 r300_mark_atom_dirty(r300, &r300->blend_state); 842 } 843 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 844 if (!!old_state->zsbuf != !!state->zsbuf) { 845 r300_mark_atom_dirty(r300, &r300->dsa_state); 846 } 847 848 /* The tiling flags are dependent on the surface miplevel, unfortunately. */ 849 r300_fb_set_tiling_flags(r300, state); 850 851 util_copy_framebuffer_state(r300->fb_state.state, state); 852 853 if (!r300->hyperz_locked) { 854 pipe_surface_reference(&r300->locked_zbuffer, NULL); 855 } 856 857 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE); 858 859 if (state->zsbuf) { 860 switch (util_format_get_blocksize(state->zsbuf->texture->format)) { 861 case 2: 862 zbuffer_bpp = 16; 863 break; 864 case 4: 865 zbuffer_bpp = 24; 866 break; 867 } 868 869 /* Polygon offset depends on the zbuffer bit depth. */ 870 if (r300->zbuffer_bpp != zbuffer_bpp) { 871 r300->zbuffer_bpp = zbuffer_bpp; 872 873 if (r300->polygon_offset_enabled) 874 r300_mark_atom_dirty(r300, &r300->rs_state); 875 } 876 } 877 878 /* Set up AA config. */ 879 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 880 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 881 882 switch (state->cbufs[0]->texture->nr_samples) { 883 case 2: 884 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 885 break; 886 case 3: 887 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 888 break; 889 case 4: 890 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 891 break; 892 case 6: 893 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 894 break; 895 } 896 } else { 897 aa->aa_config = 0; 898 } 899 900 if (DBG_ON(r300, DBG_FB)) { 901 fprintf(stderr, "r300: set_framebuffer_state:\n"); 902 for (i = 0; i < state->nr_cbufs; i++) { 903 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 904 } 905 if (state->zsbuf) { 906 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 907 } 908 } 909} 910 911/* Create fragment shader state. */ 912static void* r300_create_fs_state(struct pipe_context* pipe, 913 const struct pipe_shader_state* shader) 914{ 915 struct r300_fragment_shader* fs = NULL; 916 917 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 918 919 /* Copy state directly into shader. */ 920 fs->state = *shader; 921 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 922 923 return (void*)fs; 924} 925 926void r300_mark_fs_code_dirty(struct r300_context *r300) 927{ 928 struct r300_fragment_shader* fs = r300_fs(r300); 929 930 r300_mark_atom_dirty(r300, &r300->fs); 931 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 932 r300_mark_atom_dirty(r300, &r300->fs_constants); 933 r300->fs.size = fs->shader->cb_code_size; 934 935 if (r300->screen->caps.is_r500) { 936 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 937 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 938 } else { 939 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 940 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 941 } 942 943 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table = 944 fs->shader->code.constants_remap_table; 945} 946 947/* Bind fragment shader state. */ 948static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 949{ 950 struct r300_context* r300 = r300_context(pipe); 951 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 952 struct pipe_framebuffer_state *fb = r300->fb_state.state; 953 boolean last_multi_write; 954 955 if (fs == NULL) { 956 r300->fs.state = NULL; 957 return; 958 } 959 960 last_multi_write = r300_fragment_shader_writes_all(r300_fs(r300)); 961 962 r300->fs.state = fs; 963 r300_pick_fragment_shader(r300); 964 r300_mark_fs_code_dirty(r300); 965 966 if (fb->nr_cbufs > 1 && 967 last_multi_write != r300_fragment_shader_writes_all(fs)) { 968 r300_mark_fb_state_dirty(r300, R300_CHANGED_MULTIWRITE); 969 } 970 971 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */ 972} 973 974/* Delete fragment shader state. */ 975static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 976{ 977 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 978 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 979 980 while (ptr) { 981 tmp = ptr; 982 ptr = ptr->next; 983 rc_constants_destroy(&tmp->code.constants); 984 FREE(tmp->cb_code); 985 FREE(tmp); 986 } 987 FREE((void*)fs->state.tokens); 988 FREE(shader); 989} 990 991static void r300_set_polygon_stipple(struct pipe_context* pipe, 992 const struct pipe_poly_stipple* state) 993{ 994 /* XXX no idea how to set this up, but not terribly important */ 995} 996 997/* Create a new rasterizer state based on the CSO rasterizer state. 998 * 999 * This is a very large chunk of state, and covers most of the graphics 1000 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 1001 * 1002 * In a not entirely unironic sidenote, this state has nearly nothing to do 1003 * with the actual block on the Radeon called the rasterizer (RS). */ 1004static void* r300_create_rs_state(struct pipe_context* pipe, 1005 const struct pipe_rasterizer_state* state) 1006{ 1007 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 1008 float psiz; 1009 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 1010 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 1011 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 1012 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 1013 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 1014 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 1015 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 1016 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 1017 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 1018 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 1019 uint32_t round_mode; /* R300_GA_ROUND_MODE: 0x428c */ 1020 1021 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 1022 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */ 1023 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */ 1024 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */ 1025 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */ 1026 boolean vclamp = TRUE; 1027 CB_LOCALS; 1028 1029 /* Copy rasterizer state. */ 1030 rs->rs = *state; 1031 rs->rs_draw = *state; 1032 1033 rs->rs.sprite_coord_enable = state->point_quad_rasterization * 1034 state->sprite_coord_enable; 1035 1036 /* Override some states for Draw. */ 1037 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 1038 1039#ifdef PIPE_ARCH_LITTLE_ENDIAN 1040 vap_control_status = R300_VC_NO_SWAP; 1041#else 1042 vap_control_status = R300_VC_32BIT_SWAP; 1043#endif 1044 1045 /* If no TCL engine is present, turn off the HW TCL. */ 1046 if (!r300_screen(pipe->screen)->caps.has_tcl) { 1047 vap_control_status |= R300_VAP_TCL_BYPASS; 1048 } 1049 1050 /* Point size width and height. */ 1051 point_size = 1052 pack_float_16_6x(state->point_size) | 1053 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 1054 1055 /* Point size clamping. */ 1056 if (state->point_size_per_vertex) { 1057 /* Per-vertex point size. 1058 * Clamp to [0, max FB size] */ 1059 psiz = pipe->screen->get_paramf(pipe->screen, 1060 PIPE_CAP_MAX_POINT_WIDTH); 1061 point_minmax = 1062 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT; 1063 } else { 1064 /* We cannot disable the point-size vertex output, 1065 * so clamp it. */ 1066 psiz = state->point_size; 1067 point_minmax = 1068 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 1069 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 1070 } 1071 1072 /* Line control. */ 1073 line_control = pack_float_16_6x(state->line_width) | 1074 R300_GA_LINE_CNTL_END_TYPE_COMP; 1075 1076 /* Enable polygon mode */ 1077 polygon_mode = 0; 1078 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 1079 state->fill_back != PIPE_POLYGON_MODE_FILL) { 1080 polygon_mode = R300_GA_POLY_MODE_DUAL; 1081 } 1082 1083 /* Front face */ 1084 if (state->front_ccw) 1085 cull_mode = R300_FRONT_FACE_CCW; 1086 else 1087 cull_mode = R300_FRONT_FACE_CW; 1088 1089 /* Polygon offset */ 1090 polygon_offset_enable = 0; 1091 if (util_get_offset(state, state->fill_front)) { 1092 polygon_offset_enable |= R300_FRONT_ENABLE; 1093 } 1094 if (util_get_offset(state, state->fill_back)) { 1095 polygon_offset_enable |= R300_BACK_ENABLE; 1096 } 1097 1098 rs->polygon_offset_enable = polygon_offset_enable != 0; 1099 1100 /* Polygon mode */ 1101 if (polygon_mode) { 1102 polygon_mode |= 1103 r300_translate_polygon_mode_front(state->fill_front); 1104 polygon_mode |= 1105 r300_translate_polygon_mode_back(state->fill_back); 1106 } 1107 1108 if (state->cull_face & PIPE_FACE_FRONT) { 1109 cull_mode |= R300_CULL_FRONT; 1110 } 1111 if (state->cull_face & PIPE_FACE_BACK) { 1112 cull_mode |= R300_CULL_BACK; 1113 } 1114 1115 if (state->line_stipple_enable) { 1116 line_stipple_config = 1117 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 1118 (fui((float)state->line_stipple_factor) & 1119 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 1120 /* XXX this might need to be scaled up */ 1121 line_stipple_value = state->line_stipple_pattern; 1122 } else { 1123 line_stipple_config = 0; 1124 line_stipple_value = 0; 1125 } 1126 1127 if (state->flatshade) { 1128 rs->color_control = R300_SHADE_MODEL_FLAT; 1129 } else { 1130 rs->color_control = R300_SHADE_MODEL_SMOOTH; 1131 } 1132 1133 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 1134 1135 /* Point sprites coord mode */ 1136 if (rs->rs.sprite_coord_enable) { 1137 switch (state->sprite_coord_mode) { 1138 case PIPE_SPRITE_COORD_UPPER_LEFT: 1139 point_texcoord_top = 0.0f; 1140 point_texcoord_bottom = 1.0f; 1141 break; 1142 case PIPE_SPRITE_COORD_LOWER_LEFT: 1143 point_texcoord_top = 1.0f; 1144 point_texcoord_bottom = 0.0f; 1145 break; 1146 } 1147 } 1148 1149 /* Vertex color clamping. FP20 means no clamping. */ 1150 round_mode = 1151 R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST | 1152 (!vclamp ? (R300_GA_ROUND_MODE_RGB_CLAMP_FP20 | 1153 R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20) : 0); 1154 1155 /* Build the main command buffer. */ 1156 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE); 1157 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1158 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1159 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1160 OUT_CB(point_minmax); 1161 OUT_CB(line_control); 1162 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1163 OUT_CB(polygon_offset_enable); 1164 rs->cull_mode_index = 9; 1165 OUT_CB(cull_mode); 1166 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1167 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1168 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1169 OUT_CB_REG(R300_GA_ROUND_MODE, round_mode); 1170 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1171 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1172 OUT_CB_32F(point_texcoord_left); 1173 OUT_CB_32F(point_texcoord_bottom); 1174 OUT_CB_32F(point_texcoord_right); 1175 OUT_CB_32F(point_texcoord_top); 1176 END_CB; 1177 1178 /* Build the two command buffers for polygon offset setup. */ 1179 if (polygon_offset_enable) { 1180 float scale = state->offset_scale * 12; 1181 float offset = state->offset_units * 4; 1182 1183 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1184 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1185 OUT_CB_32F(scale); 1186 OUT_CB_32F(offset); 1187 OUT_CB_32F(scale); 1188 OUT_CB_32F(offset); 1189 END_CB; 1190 1191 offset = state->offset_units * 2; 1192 1193 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1194 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1195 OUT_CB_32F(scale); 1196 OUT_CB_32F(offset); 1197 OUT_CB_32F(scale); 1198 OUT_CB_32F(offset); 1199 END_CB; 1200 } 1201 1202 return (void*)rs; 1203} 1204 1205/* Bind rasterizer state. */ 1206static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1207{ 1208 struct r300_context* r300 = r300_context(pipe); 1209 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1210 int last_sprite_coord_enable = r300->sprite_coord_enable; 1211 boolean last_two_sided_color = r300->two_sided_color; 1212 1213 if (r300->draw && rs) { 1214 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1215 } 1216 1217 if (rs) { 1218 r300->polygon_offset_enabled = rs->polygon_offset_enable; 1219 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1220 r300->two_sided_color = rs->rs.light_twoside; 1221 } else { 1222 r300->polygon_offset_enabled = FALSE; 1223 r300->sprite_coord_enable = 0; 1224 r300->two_sided_color = FALSE; 1225 } 1226 1227 UPDATE_STATE(state, r300->rs_state); 1228 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0); 1229 1230 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1231 last_two_sided_color != r300->two_sided_color) { 1232 r300_mark_atom_dirty(r300, &r300->rs_block_state); 1233 } 1234} 1235 1236/* Free rasterizer state. */ 1237static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1238{ 1239 FREE(state); 1240} 1241 1242static void* 1243 r300_create_sampler_state(struct pipe_context* pipe, 1244 const struct pipe_sampler_state* state) 1245{ 1246 struct r300_context* r300 = r300_context(pipe); 1247 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1248 boolean is_r500 = r300->screen->caps.is_r500; 1249 int lod_bias; 1250 1251 sampler->state = *state; 1252 1253 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1254 * or MIN filter is NEAREST. Since texwrap produces same results 1255 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1256 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1257 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1258 /* Wrap S. */ 1259 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1260 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1261 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1262 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1263 1264 /* Wrap T. */ 1265 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1266 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1267 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1268 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1269 1270 /* Wrap R. */ 1271 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1272 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1273 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1274 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1275 } 1276 1277 sampler->filter0 |= 1278 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1279 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1280 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1281 1282 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1283 state->mag_img_filter, 1284 state->min_mip_filter, 1285 state->max_anisotropy > 0); 1286 1287 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1288 1289 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1290 /* We must pass these to the merge function to clamp them properly. */ 1291 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0); 1292 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0); 1293 1294 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1295 1296 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; 1297 1298 /* This is very high quality anisotropic filtering for R5xx. 1299 * It's good for benchmarking the performance of texturing but 1300 * in practice we don't want to slow down the driver because it's 1301 * a pretty good performance killer. Feel free to play with it. */ 1302 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1303 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1304 } 1305 1306 /* R500-specific fixups and optimizations */ 1307 if (r300->screen->caps.is_r500) { 1308 sampler->filter1 |= R500_BORDER_FIX; 1309 } 1310 1311 return (void*)sampler; 1312} 1313 1314static void r300_bind_sampler_states(struct pipe_context* pipe, 1315 unsigned count, 1316 void** states) 1317{ 1318 struct r300_context* r300 = r300_context(pipe); 1319 struct r300_textures_state* state = 1320 (struct r300_textures_state*)r300->textures_state.state; 1321 unsigned tex_units = r300->screen->caps.num_tex_units; 1322 1323 if (count > tex_units) { 1324 return; 1325 } 1326 1327 memcpy(state->sampler_states, states, sizeof(void*) * count); 1328 state->sampler_state_count = count; 1329 1330 r300_mark_atom_dirty(r300, &r300->textures_state); 1331} 1332 1333static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1334 unsigned count, 1335 void** states) 1336{ 1337} 1338 1339static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1340{ 1341 FREE(state); 1342} 1343 1344static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1345{ 1346 /* This looks like a hack, but I believe it's suppose to work like 1347 * that. To illustrate how this works, let's assume you have 5 textures. 1348 * From docs, 5 and the successive numbers are: 1349 * 1350 * FOURTH_1 = 5 1351 * FOURTH_2 = 6 1352 * FOURTH_3 = 7 1353 * EIGHTH_0 = 8 1354 * EIGHTH_1 = 9 1355 * 1356 * First 3 textures will get 3/4 of size of the cache, divived evenly 1357 * between them. The last 1/4 of the cache must be divided between 1358 * the last 2 textures, each will therefore get 1/8 of the cache. 1359 * Why not just to use "5 + texture_index" ? 1360 * 1361 * This simple trick works for all "num" <= 16. 1362 */ 1363 if (num <= 1) 1364 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1365 else 1366 return R300_TX_CACHE(num + index); 1367} 1368 1369static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1370 unsigned count, 1371 struct pipe_sampler_view** views) 1372{ 1373 struct r300_context* r300 = r300_context(pipe); 1374 struct r300_textures_state* state = 1375 (struct r300_textures_state*)r300->textures_state.state; 1376 struct r300_resource *texture; 1377 unsigned i, real_num_views = 0, view_index = 0; 1378 unsigned tex_units = r300->screen->caps.num_tex_units; 1379 boolean dirty_tex = FALSE; 1380 1381 if (count > tex_units) { 1382 return; 1383 } 1384 1385 /* Calculate the real number of views. */ 1386 for (i = 0; i < count; i++) { 1387 if (views[i]) 1388 real_num_views++; 1389 } 1390 1391 for (i = 0; i < count; i++) { 1392 pipe_sampler_view_reference( 1393 (struct pipe_sampler_view**)&state->sampler_views[i], 1394 views[i]); 1395 1396 if (!views[i]) { 1397 continue; 1398 } 1399 1400 /* A new sampler view (= texture)... */ 1401 dirty_tex = TRUE; 1402 1403 /* Set the texrect factor in the fragment shader. 1404 * Needed for RECT and NPOT fallback. */ 1405 texture = r300_resource(views[i]->texture); 1406 if (texture->tex.is_npot) { 1407 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 1408 } 1409 1410 state->sampler_views[i]->texcache_region = 1411 r300_assign_texture_cache_region(view_index, real_num_views); 1412 view_index++; 1413 } 1414 1415 for (i = count; i < tex_units; i++) { 1416 if (state->sampler_views[i]) { 1417 pipe_sampler_view_reference( 1418 (struct pipe_sampler_view**)&state->sampler_views[i], 1419 NULL); 1420 } 1421 } 1422 1423 state->sampler_view_count = count; 1424 1425 r300_mark_atom_dirty(r300, &r300->textures_state); 1426 1427 if (dirty_tex) { 1428 r300_mark_atom_dirty(r300, &r300->texture_cache_inval); 1429 } 1430} 1431 1432static struct pipe_sampler_view * 1433r300_create_sampler_view(struct pipe_context *pipe, 1434 struct pipe_resource *texture, 1435 const struct pipe_sampler_view *templ) 1436{ 1437 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1438 struct r300_resource *tex = r300_resource(texture); 1439 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500; 1440 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle; 1441 1442 if (view) { 1443 view->base = *templ; 1444 view->base.reference.count = 1; 1445 view->base.context = pipe; 1446 view->base.texture = NULL; 1447 pipe_resource_reference(&view->base.texture, texture); 1448 1449 view->swizzle[0] = templ->swizzle_r; 1450 view->swizzle[1] = templ->swizzle_g; 1451 view->swizzle[2] = templ->swizzle_b; 1452 view->swizzle[3] = templ->swizzle_a; 1453 1454 view->format = tex->tx_format; 1455 view->format.format1 |= r300_translate_texformat(templ->format, 1456 view->swizzle, 1457 is_r500, 1458 dxtc_swizzle); 1459 if (is_r500) { 1460 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1461 } 1462 } 1463 1464 return (struct pipe_sampler_view*)view; 1465} 1466 1467static void 1468r300_sampler_view_destroy(struct pipe_context *pipe, 1469 struct pipe_sampler_view *view) 1470{ 1471 pipe_resource_reference(&view->texture, NULL); 1472 FREE(view); 1473} 1474 1475static void r300_set_scissor_state(struct pipe_context* pipe, 1476 const struct pipe_scissor_state* state) 1477{ 1478 struct r300_context* r300 = r300_context(pipe); 1479 1480 memcpy(r300->scissor_state.state, state, 1481 sizeof(struct pipe_scissor_state)); 1482 1483 r300_mark_atom_dirty(r300, &r300->scissor_state); 1484} 1485 1486static void r300_set_viewport_state(struct pipe_context* pipe, 1487 const struct pipe_viewport_state* state) 1488{ 1489 struct r300_context* r300 = r300_context(pipe); 1490 struct r300_viewport_state* viewport = 1491 (struct r300_viewport_state*)r300->viewport_state.state; 1492 1493 r300->viewport = *state; 1494 1495 if (r300->draw) { 1496 draw_set_viewport_state(r300->draw, state); 1497 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1498 return; 1499 } 1500 1501 /* Do the transform in HW. */ 1502 viewport->vte_control = R300_VTX_W0_FMT; 1503 1504 if (state->scale[0] != 1.0f) { 1505 viewport->xscale = state->scale[0]; 1506 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1507 } 1508 if (state->scale[1] != 1.0f) { 1509 viewport->yscale = state->scale[1]; 1510 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1511 } 1512 if (state->scale[2] != 1.0f) { 1513 viewport->zscale = state->scale[2]; 1514 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1515 } 1516 if (state->translate[0] != 0.0f) { 1517 viewport->xoffset = state->translate[0]; 1518 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1519 } 1520 if (state->translate[1] != 0.0f) { 1521 viewport->yoffset = state->translate[1]; 1522 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1523 } 1524 if (state->translate[2] != 0.0f) { 1525 viewport->zoffset = state->translate[2]; 1526 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1527 } 1528 1529 r300_mark_atom_dirty(r300, &r300->viewport_state); 1530 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1531 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 1532 } 1533} 1534 1535static void r300_set_vertex_buffers(struct pipe_context* pipe, 1536 unsigned count, 1537 const struct pipe_vertex_buffer* buffers) 1538{ 1539 struct r300_context* r300 = r300_context(pipe); 1540 unsigned i; 1541 struct pipe_vertex_buffer dummy_vb = {0}; 1542 1543 /* There must be at least one vertex buffer set, otherwise it locks up. */ 1544 if (!count) { 1545 dummy_vb.buffer = r300->dummy_vb; 1546 buffers = &dummy_vb; 1547 count = 1; 1548 } 1549 1550 u_vbuf_mgr_set_vertex_buffers(r300->vbuf_mgr, count, buffers); 1551 1552 if (r300->screen->caps.has_tcl) { 1553 /* HW TCL. */ 1554 for (i = 0; i < count; i++) { 1555 if (buffers[i].buffer && 1556 !r300_resource(buffers[i].buffer)->b.user_ptr) { 1557 } 1558 } 1559 r300->vertex_arrays_dirty = TRUE; 1560 } else { 1561 /* SW TCL. */ 1562 draw_set_vertex_buffers(r300->draw, count, buffers); 1563 } 1564} 1565 1566static void r300_set_index_buffer(struct pipe_context* pipe, 1567 const struct pipe_index_buffer *ib) 1568{ 1569 struct r300_context* r300 = r300_context(pipe); 1570 1571 if (ib && ib->buffer) { 1572 assert(ib->offset % ib->index_size == 0); 1573 1574 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer); 1575 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer)); 1576 r300->index_buffer.offset /= r300->index_buffer.index_size; 1577 } 1578 else { 1579 pipe_resource_reference(&r300->index_buffer.buffer, NULL); 1580 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer)); 1581 } 1582 1583 if (!r300->screen->caps.has_tcl) { 1584 draw_set_index_buffer(r300->draw, ib); 1585 } 1586} 1587 1588/* Initialize the PSC tables. */ 1589static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1590{ 1591 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1592 uint16_t type, swizzle; 1593 enum pipe_format format; 1594 unsigned i; 1595 1596 if (velems->count > 16) { 1597 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1598 " requested %i, using 16.\n", velems->count); 1599 velems->count = 16; 1600 } 1601 1602 /* Vertex shaders have no semantics on their inputs, 1603 * so PSC should just route stuff based on the vertex elements, 1604 * and not on attrib information. */ 1605 for (i = 0; i < velems->count; i++) { 1606 format = velems->velem[i].src_format; 1607 1608 type = r300_translate_vertex_data_type(format); 1609 if (type == R300_INVALID_FORMAT) { 1610 fprintf(stderr, "r300: Bad vertex format %s.\n", 1611 util_format_short_name(format)); 1612 assert(0); 1613 abort(); 1614 } 1615 1616 type |= i << R300_DST_VEC_LOC_SHIFT; 1617 swizzle = r300_translate_vertex_data_swizzle(format); 1618 1619 if (i & 1) { 1620 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1621 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1622 } else { 1623 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1624 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1625 } 1626 } 1627 1628 /* Set the last vector in the PSC. */ 1629 if (i) { 1630 i -= 1; 1631 } 1632 vstream->vap_prog_stream_cntl[i >> 1] |= 1633 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1634 1635 vstream->count = (i >> 1) + 1; 1636} 1637 1638static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1639 unsigned count, 1640 const struct pipe_vertex_element* attribs) 1641{ 1642 struct r300_context *r300 = r300_context(pipe); 1643 struct r300_vertex_element_state *velems; 1644 unsigned i; 1645 struct pipe_vertex_element dummy_attrib = {0}; 1646 1647 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */ 1648 if (!count) { 1649 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM; 1650 attribs = &dummy_attrib; 1651 count = 1; 1652 } 1653 1654 assert(count <= PIPE_MAX_ATTRIBS); 1655 velems = CALLOC_STRUCT(r300_vertex_element_state); 1656 if (!velems) 1657 return NULL; 1658 1659 velems->count = count; 1660 velems->vmgr_elements = 1661 u_vbuf_mgr_create_vertex_elements(r300->vbuf_mgr, count, attribs, 1662 velems->velem); 1663 1664 if (r300_screen(pipe->screen)->caps.has_tcl) { 1665 /* Setup PSC. 1666 * The unused components will be replaced by (..., 0, 1). */ 1667 r300_vertex_psc(velems); 1668 1669 for (i = 0; i < count; i++) { 1670 velems->format_size[i] = 1671 align(util_format_get_blocksize(velems->velem[i].src_format), 4); 1672 velems->vertex_size_dwords += velems->format_size[i] / 4; 1673 } 1674 } 1675 1676 return velems; 1677} 1678 1679static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1680 void *state) 1681{ 1682 struct r300_context *r300 = r300_context(pipe); 1683 struct r300_vertex_element_state *velems = state; 1684 1685 if (velems == NULL) { 1686 return; 1687 } 1688 1689 r300->velems = velems; 1690 1691 u_vbuf_mgr_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements); 1692 1693 if (r300->draw) { 1694 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1695 return; 1696 } 1697 1698 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1699 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1700 r300->vertex_arrays_dirty = TRUE; 1701} 1702 1703static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1704{ 1705 struct r300_context *r300 = r300_context(pipe); 1706 struct r300_vertex_element_state *velems = state; 1707 1708 u_vbuf_mgr_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements); 1709 FREE(state); 1710} 1711 1712static void* r300_create_vs_state(struct pipe_context* pipe, 1713 const struct pipe_shader_state* shader) 1714{ 1715 struct r300_context* r300 = r300_context(pipe); 1716 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1717 1718 /* Copy state directly into shader. */ 1719 vs->state = *shader; 1720 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1721 1722 if (r300->screen->caps.has_tcl) { 1723 r300_init_vs_outputs(vs); 1724 r300_translate_vertex_shader(r300, vs); 1725 } else { 1726 r300_draw_init_vertex_shader(r300->draw, vs); 1727 } 1728 1729 return vs; 1730} 1731 1732static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1733{ 1734 struct r300_context* r300 = r300_context(pipe); 1735 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1736 1737 if (vs == NULL) { 1738 r300->vs_state.state = NULL; 1739 return; 1740 } 1741 if (vs == r300->vs_state.state) { 1742 return; 1743 } 1744 r300->vs_state.state = vs; 1745 1746 /* The majority of the RS block bits is dependent on the vertex shader. */ 1747 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */ 1748 1749 if (r300->screen->caps.has_tcl) { 1750 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2; 1751 r300_mark_atom_dirty(r300, &r300->vs_state); 1752 r300->vs_state.size = 1753 vs->code.length + 9 + 1754 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0); 1755 1756 r300_mark_atom_dirty(r300, &r300->vs_constants); 1757 r300->vs_constants.size = 1758 2 + 1759 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) + 1760 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0); 1761 1762 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table = 1763 vs->code.constants_remap_table; 1764 1765 r300_mark_atom_dirty(r300, &r300->pvs_flush); 1766 } else { 1767 draw_bind_vertex_shader(r300->draw, 1768 (struct draw_vertex_shader*)vs->draw_vs); 1769 } 1770} 1771 1772static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1773{ 1774 struct r300_context* r300 = r300_context(pipe); 1775 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1776 1777 if (r300->screen->caps.has_tcl) { 1778 rc_constants_destroy(&vs->code.constants); 1779 if (vs->code.constants_remap_table) 1780 FREE(vs->code.constants_remap_table); 1781 } else { 1782 draw_delete_vertex_shader(r300->draw, 1783 (struct draw_vertex_shader*)vs->draw_vs); 1784 } 1785 1786 FREE((void*)vs->state.tokens); 1787 FREE(shader); 1788} 1789 1790static void r300_set_constant_buffer(struct pipe_context *pipe, 1791 uint shader, uint index, 1792 struct pipe_resource *buf) 1793{ 1794 struct r300_context* r300 = r300_context(pipe); 1795 struct r300_constant_buffer *cbuf; 1796 struct r300_resource *rbuf = r300_resource(buf); 1797 uint32_t *mapped; 1798 1799 switch (shader) { 1800 case PIPE_SHADER_VERTEX: 1801 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1802 break; 1803 case PIPE_SHADER_FRAGMENT: 1804 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1805 break; 1806 default: 1807 return; 1808 } 1809 1810 if (buf == NULL || buf->width0 == 0) 1811 return; 1812 1813 if (rbuf->b.user_ptr) 1814 mapped = (uint32_t*)rbuf->b.user_ptr; 1815 else if (rbuf->constant_buffer) 1816 mapped = (uint32_t*)rbuf->constant_buffer; 1817 else 1818 return; 1819 1820 if (shader == PIPE_SHADER_FRAGMENT || 1821 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1822 cbuf->ptr = mapped; 1823 } 1824 1825 if (shader == PIPE_SHADER_VERTEX) { 1826 if (r300->screen->caps.has_tcl) { 1827 struct r300_vertex_shader *vs = 1828 (struct r300_vertex_shader*)r300->vs_state.state; 1829 1830 if (!vs) { 1831 cbuf->buffer_base = 0; 1832 return; 1833 } 1834 1835 cbuf->buffer_base = r300->vs_const_base; 1836 r300->vs_const_base += vs->code.constants.Count; 1837 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) { 1838 r300->vs_const_base = vs->code.constants.Count; 1839 cbuf->buffer_base = 0; 1840 r300_mark_atom_dirty(r300, &r300->pvs_flush); 1841 } 1842 r300_mark_atom_dirty(r300, &r300->vs_constants); 1843 } else if (r300->draw) { 1844 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1845 0, mapped, buf->width0); 1846 } 1847 } else if (shader == PIPE_SHADER_FRAGMENT) { 1848 r300_mark_atom_dirty(r300, &r300->fs_constants); 1849 } 1850} 1851 1852void r300_init_state_functions(struct r300_context* r300) 1853{ 1854 r300->context.create_blend_state = r300_create_blend_state; 1855 r300->context.bind_blend_state = r300_bind_blend_state; 1856 r300->context.delete_blend_state = r300_delete_blend_state; 1857 1858 r300->context.set_blend_color = r300_set_blend_color; 1859 1860 r300->context.set_clip_state = r300_set_clip_state; 1861 r300->context.set_sample_mask = r300_set_sample_mask; 1862 1863 r300->context.set_constant_buffer = r300_set_constant_buffer; 1864 1865 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1866 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1867 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1868 1869 r300->context.set_stencil_ref = r300_set_stencil_ref; 1870 1871 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1872 1873 r300->context.create_fs_state = r300_create_fs_state; 1874 r300->context.bind_fs_state = r300_bind_fs_state; 1875 r300->context.delete_fs_state = r300_delete_fs_state; 1876 1877 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1878 1879 r300->context.create_rasterizer_state = r300_create_rs_state; 1880 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1881 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1882 1883 r300->context.create_sampler_state = r300_create_sampler_state; 1884 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1885 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1886 r300->context.delete_sampler_state = r300_delete_sampler_state; 1887 1888 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1889 r300->context.create_sampler_view = r300_create_sampler_view; 1890 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1891 1892 r300->context.set_scissor_state = r300_set_scissor_state; 1893 1894 r300->context.set_viewport_state = r300_set_viewport_state; 1895 1896 r300->context.set_vertex_buffers = r300_set_vertex_buffers; 1897 r300->context.set_index_buffer = r300_set_index_buffer; 1898 r300->context.redefine_user_buffer = u_default_redefine_user_buffer; 1899 1900 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1901 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1902 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1903 1904 r300->context.create_vs_state = r300_create_vs_state; 1905 r300->context.bind_vs_state = r300_bind_vs_state; 1906 r300->context.delete_vs_state = r300_delete_vs_state; 1907} 1908