dma_api.h revision 7e8d39a9d261ff6b5256d7cf9c7a127947b2b2a5
1/* 2 * Copyright (c) 2007 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26/*! 27****************************************************************************** 28 @file : dma_api.h 29 30 @brief 31 32 @Author Ray Livesley 33 34 @date 02/11/2005 35 36 \n<b>Description:</b>\n 37 This file contains header file for the MTX DMAC API. 38 39 The MTX DMAC API can operate synchronously or asynchronously. 40 41 In synchronous case, the API uses an internal callback function 42 to detect state transitions and the SEMA API to block whilst 43 waiting for the transfer to complete. 44 45 In the asynchronous case, the caller is responsible for 46 detecting and handling the state transitions and synchronising 47 with other processes/processing. 48 49 \n<b>Platform:</b>\n 50 MSVDX/MTX 51 52******************************************************************************/ 53/* 54****************************************************************************** 55 Modifications :- 56 57 $Log: dma_api.h $ 58 59 --- Revision Logs Removed --- 60 61 --- Revision Logs Removed --- 62 63 --- Revision Logs Removed --- 64 65 --- Revision Logs Removed --- 66 67 --- Revision Logs Removed --- 68 69 --- Revision Logs Removed --- 70 71 --- Revision Logs Removed --- 72 73 --- Revision Logs Removed --- 74 75 --- Revision Logs Removed --- 76 77 --- Revision Logs Removed --- 78 79 --- Revision Logs Removed --- 80 81 --- Revision Logs Removed --- 82 83 --- Revision Logs Removed --- 84 85 --- Revision Logs Removed --- 86 87 --- Revision Logs Removed --- 88 89 --- Revision Logs Removed --- 90 91 --- Revision Logs Removed --- 92 93 --- Revision Logs Removed --- 94 95 --- Revision Logs Removed --- 96 97 --- Revision Logs Removed --- 98 99 --- Revision Logs Removed --- 100 101 --- Revision Logs Removed --- 102 103 --- Revision Logs Removed --- 104 105 106*****************************************************************************/ 107 108 109#if !defined (__DMA_API_H__) 110#define __DMA_API_H__ 111 112#include <img_types.h> 113#include "msvdx_dmac_regs_io2.h" 114#include "msvdx_dmac_linked_list.h" 115 116#if (__cplusplus) 117extern "C" { 118#endif 119 120/*! 121****************************************************************************** 122 This type defines the DMAC status 123******************************************************************************/ 124typedef enum 125{ 126 DMA_STATUS_IDLE, //!< The DMAC is idle. 127 DMA_STATUS_BUSY, //!< The DMAC is busy - a DMA is in progress. 128 DMA_STATUS_COMPLETE, /*!< The DMAC operation has completed - return by 129 DMA_GetStatus()once before the DMAC returns 130 to #DMA_STATUS_IDLE. */ 131 DMA_STATUS_TIMEOUT, /*!< The DMAC operation has timed-out - return by 132 DMA_GetStatus()once before the DMAC returns 133 to #DMA_STATUS_IDLE. */ 134 135} DMA_eStatus; 136 137/*! 138****************************************************************************** 139 This type defines the DMA channel Ids 140******************************************************************************/ 141typedef enum 142{ 143 DMA_CHANNEL_MTX = 0x0, //!< DMA channel for MTX 144 DMA_CHANNEL_RESERVED, //!< DMA channel 1 is reserved for VEC use 145 DMA_CHANNEL_SR1, //!< DMA channel for 1st shift register 146 DMA_CHANNEL_SR2, //!< DMA channel for 2nd shift register 147 DMA_CHANNEL_SR3, //!< DMA channel for 3rd shift register 148 DMA_CHANNEL_SR4, //!< DMA channel for 4th shift register 149 150} DMA_eChannelId; 151 152/*! 153****************************************************************************** 154 Used with DMA_SyncAction() and DMA_AsyncAction() to indicate whether 155 the peripheral is the mtx or not. 156******************************************************************************/ 157enum 158{ 159 DMA_PERIPH_IS_NOT_MTX = 0, //!< The peripheral is not the mtx. 160 DMA_PERIPH_IS_MTX = 1, //!< The peripheral is the mtx. 161}; 162 163/*! 164****************************************************************************** 165 This type defines the byte swap settings. 166******************************************************************************/ 167typedef enum 168{ 169 DMA_BSWAP_NO_SWAP = 0x0, //!< No byte swapping will be performed. 170 DMA_BSWAP_REVERSE = 0x1, //!< Byte order will be reversed. 171 172} DMA_eBSwap; 173 174/*! 175****************************************************************************** 176 This type defines the peripheral width settings 177******************************************************************************/ 178typedef enum 179{ 180 DMA_PWIDTH_32_BIT = 0x0, //!< Peripheral width 32-bit. 181 DMA_PWIDTH_16_BIT = 0x1, //!< Peripheral width 16-bit. 182 DMA_PWIDTH_8_BIT = 0x2, //!< Peripheral width 8-bit. 183 184} DMA_ePW; 185 186/*! 187****************************************************************************** 188 This type defines the direction of the DMA transfer 189******************************************************************************/ 190typedef enum 191{ 192 DMA_DIR_MEM_TO_PERIPH = 0x0, //!< Data from memory to peripheral. 193 DMA_DIR_PERIPH_TO_MEM = 0x1, //!< Data from peripheral to memory. 194 195} DMA_eDir; 196 197/*! 198****************************************************************************** 199 This type defines whether the peripheral address is to be incremented 200******************************************************************************/ 201typedef enum 202{ 203 DMA_PERIPH_INCR_ON = 0x1, //!< Peripheral address will be incremented 204 DMA_PERIPH_INCR_OFF = 0x0, //!< Peripheral address will not be incremented 205 206} DMA_ePeriphIncr; 207 208/*! 209****************************************************************************** 210 This type defines how much the peripheral address is incremented by 211******************************************************************************/ 212typedef enum 213{ 214 DMA_PERIPH_INCR_1 = 0x2, //!< Increment peripheral address by 1 215 DMA_PERIPH_INCR_2 = 0x1, //!< Increment peripheral address by 2 216 DMA_PERIPH_INCR_4 = 0x0, //!< Increment peripheral address by 4 217 218} DMA_ePeriphIncrSize; 219 220/*! 221****************************************************************************** 222 This type defines whether the 2d mode is enabled or disabled 223******************************************************************************/ 224typedef enum 225{ 226 DMA_MODE_2D_ON = 0x1, //!< the 2d mode will be used 227 DMA_MODE_2D_OFF = 0x0, //!< the 2d mode will not be used 228 229} DMA_eMode2D; 230 231/*! 232****************************************************************************** 233 234 @Function DMA_LL_SET_WD0 235 236 @Description 237 238 Set word 0 in a dmac linked list entry. 239 240 @Input pList : pointer to start of linked list entry 241 242 @Input BSWAP : big/little endian byte swap (see DMA_eBSwap). 243 244 @Input DIR : transfer direction (see DMA_eDir). 245 246 @Input PW : peripheral width (see DMA_ePW). 247 248 @Return nothing 249 250******************************************************************************/ 251#define DMA_LL_SET_WD0(pList, BSWAP, DIR, PW) \ 252 do{ \ 253 MEMIO_WRITE_FIELD(pList, DMAC_LL_BSWAP, BSWAP); \ 254 MEMIO_WRITE_FIELD(pList, DMAC_LL_DIR, DIR); \ 255 MEMIO_WRITE_FIELD(pList, DMAC_LL_PW, PW); \ 256 }while(0) 257 258 259/*! 260****************************************************************************** 261 262 @Function DMA_LL_SET_WD1 263 264 @Description 265 266 Set word 1 in a dmac linked list entry. 267 268 @Input pList : pointer to start of linked list entry 269 270 @Input INCR : whether to increment the peripeheral address (see DMA_ePeriphIncr) 271 272 @Input PI : how much to increment the peripheral address by (see DMA_ePeriphIncrSize) 273 274 @Input LEN : length of transfer in peripheral width units 275 276 @Return nothing 277 278******************************************************************************/ 279#define DMA_LL_SET_WD1(pList, INCR, PI, LEN) \ 280 do { \ 281 MEMIO_WRITE_FIELD(pList, DMAC_LL_PI, PI); \ 282 MEMIO_WRITE_FIELD(pList, DMAC_LL_INCR, INCR); \ 283 MEMIO_WRITE_FIELD(pList, DMAC_LL_LEN, LEN); \ 284 }while(0) 285 286/*! 287****************************************************************************** 288 289 @Function DMA_LL_SET_WD2 290 291 @Description 292 293 Set word 2 in a dmac linked list entry. 294 295 @Input pList : pointer to start of linked list entry 296 297 @Input PERI_ADDR : the perihperal address to transfer to/from 298 299 @Return nothing 300 301******************************************************************************/ 302#define DMA_LL_SET_WD2(pList, PERI_ADDR) \ 303 do { \ 304 MEMIO_WRITE_FIELD(pList, DMAC_LL_ADDR, PERI_ADDR); \ 305 }while(0) 306 307/*! 308****************************************************************************** 309 310 @Function DMA_LL_SET_WD3 311 312 @Description 313 314 Set word 3 in a dmac linked list entry. 315 316 @Input pList : pointer to start of linked list entry 317 318 @Input ACC_DEL : access delay (see DMA_eAccDel) 319 320 @Input BURST : burst size (see DMA_eBurst) 321 322 @Return nothing 323 324******************************************************************************/ 325#define DMA_LL_SET_WD3(pList, ACC_DEL, BURST , EXTSA ) \ 326 do { \ 327 MEMIO_WRITE_FIELD(pList, DMAC_LL_ACC_DEL, ACC_DEL); \ 328 MEMIO_WRITE_FIELD(pList, DMAC_LL_BURST, BURST); \ 329 MEMIO_WRITE_FIELD(pList, DMAC_LL_EXT_SA, EXTSA); \ 330 }while(0) 331 332/*! 333****************************************************************************** 334 335 @Function DMA_LL_SET_WD4 336 337 @Description 338 339 Set word 4 in a dmac linked list entry. 340 341 @Input pList : pointer to start of linked list entry 342 343 @Input MODE_2D : enable/disable 2d mode (see DMA_eMode2D) 344 345 @Input REP_COUNT : repeat count (the number of rows transferred) 346 347 @Return nothing 348 349******************************************************************************/ 350#define DMA_LL_SET_WD4(pList, MODE_2D, REP_COUNT) \ 351 do { \ 352 MEMIO_WRITE_FIELD(pList, DMAC_LL_MODE_2D, MODE_2D); \ 353 MEMIO_WRITE_FIELD(pList, DMAC_LL_REP_COUNT, REP_COUNT); \ 354 } while(0) 355 356/*! 357****************************************************************************** 358 359 @Function DMA_LL_SET_WD5 360 361 @Description 362 363 Set word 5 in a dmac linked list entry. 364 365 @Input pList : pointer to start of linked list entry 366 367 @Input LINE_ADD_OFF : number of bytes from the end of one row to the start of the next row 368 (only applicable when using 2D transfer mode) 369 370 @Input ROW_LENGTH : number of bytes per row 371 (only applicable when using 2D transfer mode) 372 373 @Return nothing 374 375******************************************************************************/ 376#define DMA_LL_SET_WD5(pList, LINE_ADD_OFF, ROW_LENGTH) \ 377 do{ \ 378 MEMIO_WRITE_FIELD(pList, DMAC_LL_LINE_ADD_OFF, LINE_ADD_OFF); \ 379 MEMIO_WRITE_FIELD(pList, DMAC_LL_ROW_LENGTH, ROW_LENGTH); \ 380 }while(0) 381 382/*! 383****************************************************************************** 384 385 @Function DMA_LL_SET_WD6 386 387 @Description 388 389 Set word 6 in a dmac linked list entry. 390 391 @Input pList : pointer to start of linked list entry 392 393 @Input SA : the host memory address to transfer to/from 394 395 @Return nothing 396 397******************************************************************************/ 398#define DMA_LL_SET_WD6(pList, SA) \ 399 do{ \ 400 MEMIO_WRITE_FIELD(pList, DMAC_LL_SA, SA); \ 401 }while(0) 402 403/*! 404****************************************************************************** 405 406@Function DMA_LL_SET_WD7 407 408@Description 409 410Set word 7 in a dmac linked list entry. 411 412@Input pList: pointer to start of linked list entry 413 414@Input LISTPTR: pointer to next linked list entry 415 416If the linked list entry is in MTX memory (eListLocation == DMA_LIST_IS_IN_MTX_MEM) then 417LISTPTR is a pointer to the start of the next linked list entry. If the linked list entry 418is in HOST memory (eListLocation == DMA_LIST_IS_IN_SYS_MEM) then LISTPTR is a pointer to the 419start of the next linked list entry, but right shifted by 4 bits (i.e. ptr >> 4). If this 420is the last entry in the linked list sequence then LISTPTR must be set to NULL. 421 422@Return nothing 423 424******************************************************************************/ 425#define DMA_LL_SET_WD7(pList, LISTPTR) \ 426 do { \ 427 MEMIO_WRITE_FIELD(pList, DMAC_LL_LISTPTR, LISTPTR); \ 428 MEMIO_WRITE_FIELD(pList, DMAC_LL_LIST_FIN, (LISTPTR) ? 0 : 1); \ 429 }while(0) 430 431 432/*! 433****************************************************************************** 434 435 @Function DMA_VALUE_COUNT 436 437 @Description 438 439 This MACRO is used to aid the generation of the ui32Count member of the DMA_sParams 440 structure required by DMA_SyncAction() and DMA_AsyncAction(). If this is not suitable 441 for a given application then the programmer is free to fill in the fields in any way they 442 see fit. 443 444 @Input BSWAP : Big/little endian byte swap (see DMA_eBSwap). 445 446 @Input PW : The width of the peripheral DMA register (see DMA_ePW). 447 448 @Input DIR : The direction of the transfer (see DMA_eDir). 449 450 @Input PERIPH_INCR : How much to increment the peripheral address by (see DMA_ePeriphIncr). 451 452 @Input COUNT : The length of the transfer in transfer units. 453 454 @Return img_uint32 : The value of the generated word. 455 456******************************************************************************/ 457#define DMA_VALUE_COUNT(BSWAP,PW,DIR,PERIPH_INCR,COUNT) \ 458 \ 459 (((BSWAP) & DMAC_DMAC_COUNT_BSWAP_LSBMASK) << DMAC_DMAC_COUNT_BSWAP_SHIFT) | \ 460 (((PW) & DMAC_DMAC_COUNT_PW_LSBMASK) << DMAC_DMAC_COUNT_PW_SHIFT) | \ 461 (((DIR) & DMAC_DMAC_COUNT_DIR_LSBMASK) << DMAC_DMAC_COUNT_DIR_SHIFT) | \ 462 (((PERIPH_INCR) & DMAC_DMAC_COUNT_PI_LSBMASK) << DMAC_DMAC_COUNT_PI_SHIFT) | \ 463 (((COUNT) & DMAC_DMAC_COUNT_CNT_LSBMASK) << DMAC_DMAC_COUNT_CNT_SHIFT) 464 465/*! 466****************************************************************************** 467 This type defines the access delay settings. 468******************************************************************************/ 469typedef enum 470{ 471 DMA_ACC_DEL_0 = 0x0, //!< Access delay zero clock cycles 472 DMA_ACC_DEL_256 = 0x1, //!< Access delay 256 clock cycles 473 DMA_ACC_DEL_512 = 0x2, //!< Access delay 512 clock cycles 474 DMA_ACC_DEL_768 = 0x3, //!< Access delay 768 clock cycles 475 DMA_ACC_DEL_1024 = 0x4, //!< Access delay 1024 clock cycles 476 DMA_ACC_DEL_1280 = 0x5, //!< Access delay 1280 clock cycles 477 DMA_ACC_DEL_1536 = 0x6, //!< Access delay 1536 clock cycles 478 DMA_ACC_DEL_1792 = 0x7, //!< Access delay 1792 clock cycles 479 480} DMA_eAccDel; 481 482/*! 483****************************************************************************** 484 This type defines whether the peripheral address is static or auto-incremented. 485******************************************************************************/ 486typedef enum 487{ 488 DMA_INCR_OFF = 0, //!< Static peripheral address. 489 DMA_INCR_ON = 1 //!< Incrementing peripheral address. 490 491} DMA_eIncr; 492 493/*! 494****************************************************************************** 495 This type defines the burst size setting. 496******************************************************************************/ 497typedef enum 498{ 499 DMA_BURST_0 = 0x0, //!< burst size of 0 500 DMA_BURST_1 = 0x1, //!< burst size of 1 501 DMA_BURST_2 = 0x2, //!< burst size of 2 502 DMA_BURST_3 = 0x3, //!< burst size of 3 503 DMA_BURST_4 = 0x4, //!< burst size of 4 504 DMA_BURST_5 = 0x5, //!< burst size of 5 505 DMA_BURST_6 = 0x6, //!< burst size of 6 506 DMA_BURST_7 = 0x7, //!< burst size of 7 507 508} DMA_eBurst; 509 510/*! 511****************************************************************************** 512 513@Function DMA_VALUE_PERIPH_PARAM 514 515@Description 516 517This MACRO is used to aid the generation of the ui32PeripheralParam member of the 518DMA_sParams structure required by DMA_SyncAction() and DMA_AsyncAction(). If this is 519not suitable for a given application then the programmer is free to fill in the fields in 520any way they see fit. 521 522@Input ACC_DEL: The access delay (see DMA_eAccDel). 523 524@Input INCR: Whether the peripheral address is incremented (see DMA_eIncr). 525 526@Input BURST: The burst size. This should correspond to the amount of data that the 527 peripheral will either be able to supply or accept from its FIFO (see DMA_eBurst). 528 529@Return img_uint32: The value of the generated word. 530 531******************************************************************************/ 532#define DMA_VALUE_PERIPH_PARAM(ACC_DEL,INCR,BURST) \ 533 \ 534 (((ACC_DEL) & DMAC_DMAC_PERIPH_ACC_DEL_LSBMASK) << DMAC_DMAC_PERIPH_ACC_DEL_SHIFT) | \ 535 (((INCR) & DMAC_DMAC_PERIPH_INCR_LSBMASK) << DMAC_DMAC_PERIPH_INCR_SHIFT) | \ 536 (((BURST) & DMAC_DMAC_PERIPH_BURST_LSBMASK) << DMAC_DMAC_PERIPH_BURST_SHIFT) 537 538 539 540/*! 541****************************************************************************** 542 Used to describe the location of the linked list structure 543******************************************************************************/ 544typedef enum { 545 DMA_LIST_IS_IN_MTX_MEM, 546 DMA_LIST_IS_IN_SYS_MEM, 547} DMA_LIST_LOCATION; 548 549/*! 550****************************************************************************** 551 DMAC linked list structure 552******************************************************************************/ 553typedef struct 554{ 555 IMG_UINT32 ui32Word_0; //!< Word 0 of the linked list (see DMA_LL_SET_WD0). 556 IMG_UINT32 ui32Word_1; //!< Word 1 of the linked list (see DMA_LL_SET_WD1). 557 IMG_UINT32 ui32Word_2; //!< Word 2 of the linked list (see DMA_LL_SET_WD2). 558 IMG_UINT32 ui32Word_3; //!< Word 3 of the linked list (see DMA_LL_SET_WD3). 559 IMG_UINT32 ui32Word_4; //!< Word 4 of the linked list (see DMA_LL_SET_WD4). 560 IMG_UINT32 ui32Word_5; //!< Word 5 of the linked list (see DMA_LL_SET_WD5). 561 IMG_UINT32 ui32Word_6; //!< Word 6 of the linked list (see DMA_LL_SET_WD6). 562 IMG_UINT32 ui32Word_7; //!< Word 7 of the linked list (see DMA_LL_SET_WD7). 563 564} DMA_sLinkedList; 565 566/*! 567****************************************************************************** 568 DMAC Parameter structure 569******************************************************************************/ 570typedef struct 571{ 572 IMG_UINT32 ui32PerHold; //!< peripheral hold register (see PER_HOLD register in TRM) 573 DMA_LIST_LOCATION eListLocation; //!< is the linked list in mtx memory or system memory 574 DMA_sLinkedList * psDmaLinkedList; //!< pointer to first element in the linked list 575 IMG_UINT32 ui32Ext_sa; 576} DMA_sParams; 577 578/*! 579****************************************************************************** 580 581 @Function DMA_Initialise 582 583 @Description 584 585 This function initialises the DMAC. Only has effect on the first call, second 586 and subsequent calls are ignored. 587 588 @Input eChannel : The channel to initialise. 589 590 @Return None. 591 592******************************************************************************/ 593extern IMG_VOID DMA_Initialise (DMA_eChannelId eChannel); 594 595/*! 596****************************************************************************** 597 598 @Function DMA_Reset 599 600 @Description 601 602 This function resets the DMAC, cancels any pending DMAC operation and 603 return the DMAC to the idle state - #DMA_STATUS_IDLE. 604 605 @Input eChannel : The channel to reset. 606 607 @Return None. 608 609******************************************************************************/ 610extern IMG_VOID DMA_Reset (DMA_eChannelId eChannel); 611 612/*! 613****************************************************************************** 614 615 @Function DMA_SyncAction 616 617 @Description 618 619 This function is used to initiate a synchronous (blocking) DMAC tranfer. 620 621 An internal callback function is registered using DMA_RegisterStatusCallback() 622 to detect and act upon status transitions. 623 624 The DMAC driver also uses the SEMA API, SEMA_ID_B to block whilst waiting 625 for the DMAC transfer to complete. The callback function will set the 626 semaphore when the 627 628 NOTE: The DMAC must be in the idle state - #DMA_STATUS_IDLE - when the 629 transfer is initiated. 630 631 @Input eChannel : The channel to use. 632 633 @Input psParams : A pointer to a #DMA_sParams structure set with the 634 required DMAC setup. 635 636 @Input bMtx : If true then the peripheral address specifies an 637 offset in MTX memory 638 639 @Return DMA_eStatus : The completion status - #DMA_STATUS_COMPLETE or 640 #DMA_STATUS_TIMEOUT. 641 642******************************************************************************/ 643extern DMA_eStatus DMA_SyncAction ( 644 DMA_eChannelId eChannel, 645 DMA_sParams * psParams, 646 IMG_BOOL bMtx 647); 648 649/*! 650****************************************************************************** 651 652 @Function DMA_AsyncAction 653 654 @Description 655 656 This function is used to initiate an asynchronous (non-blocking) DMAC tranfer. 657 658 NOTE: The DMAC must be in the idle state - #DMA_STATUS_IDLE - when the 659 transfer is initiated. 660 661 @Input eChannel : The channel to use. 662 663 @Input psDmacLinkedList : A pointer to a #DMA_sLinkedList structure set with the 664 required DMAC setup. 665 666 @Input bPeriphIsMtx : If true then the peripheral address specifies an 667 offset in MTX memory. 668 669 NOTE: If eListLocation is DMA_LIST_IS_IN_SYS_MEM and bPeriphIsMtx is IMG_TRUE the linked list can only contain a single entry. 670 671 NOTE: If eListLocation is DMA_LIST_IS_IN_MTX_MEM then bPeriphIsMtx applies to all entries in the linked list (i.e. 672 they all use the mtx as the peripheral, or none of them use the mtx as the peripheral). 673 674 @Return None. 675 676******************************************************************************/ 677extern IMG_VOID DMA_AsyncAction ( 678 DMA_eChannelId eChannel, 679 DMA_sParams * psParams, 680 IMG_BOOL bPeriphIsMtx 681); 682 683/*! 684****************************************************************************** 685 686 @Function DMA_WaitForTransfer 687 688 @Description 689 690 This function waits for the current transfer to complete or timeout. 691 692 @Input eChannel : The channel to wait use. 693 694 @Return DMA_eStatus : DMA_STATUS_COMPLETE when transfer has completed or DMA_STATUS_IDLE 695 if there wasn't an active transfer in progress to wait for. 696 697******************************************************************************/ 698extern DMA_eStatus DMA_WaitForTransfer(DMA_eChannelId eChannel); 699 700/*! 701****************************************************************************** 702 703 @Function DMA_GetStatus 704 705 @Description 706 707 This function returns the status of the DMAC. 708 709 @Input eChannel : The channel to get the status of. 710 711 @Return DMA_eStatus : The status of the DMAC. 712 713******************************************************************************/ 714extern DMA_eStatus DMA_GetStatus(DMA_eChannelId eChannel); 715 716/*! 717****************************************************************************** 718 719 @Function DMA_pfnStatusCallback 720 721 @Description 722 723 This is the prototype for a status callback functions. 724 725 @Input eChannel : The channel that the status change is being reported on. 726 727 @Input DMA_eStatus : The "new" state of the DMAC. 728 729 @Return None. 730 731******************************************************************************/ 732typedef IMG_VOID (*DMA_pfnStatusCallback) ( 733 DMA_eChannelId eChannel, 734 DMA_eStatus eStatus 735); 736 737 738/*! 739****************************************************************************** 740 741 @Function DMA_RegisterStatusCallback 742 743 @Description 744 745 This function is used to register a status callback function. The caller 746 provides the address of a function that will be called when a change in the 747 status occurs - see #DMA_eStatus. 748 749 NOTE: This can happen asynchronously (at interrupt level) on a 750 #DMA_STATUS_COMPLETE or #DMA_STATUS_TIMEOUT - or synchronously when 751 DMA_Action() is called and the state changes to #DMA_STATUS_BUSY or 752 when DMA_GetStatus() or DMA_Reset() are called and the state returns to 753 #DMA_STATUS_IDLE. 754 755 NOTE: Only one callback function can be registered with the API. The 756 callback function is persistent and is not removed by subsequent calls 757 to DMA_Initialise() or DMA_Reset(). 758 759 NOTE: The function asserts if a callback function has already been set. 760 761 @Input eChannel : The channel that the status change is being reported on. 762 763 @Input pfnStatusCallback : A pointer to a status callback function. 764 765 @Return None. 766 767******************************************************************************/ 768extern IMG_VOID DMA_RegisterStatusCallback ( 769 DMA_eChannelId eChannel, 770 DMA_pfnStatusCallback pfnStatusCallback 771); 772 773 774#if (__cplusplus) 775} 776#endif 777 778#endif /* __DMA_API_H__ */ 779