dma_api.h revision f91c8768670386683a281cc39141e21bdda9c97f
1/* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 27/*! 28****************************************************************************** 29 @file : dma_api.h 30 31 @brief 32 33 @date 02/11/2005 34 35 \n<b>Description:</b>\n 36 This file contains header file for the MTX DMAC API. 37 38 The MTX DMAC API can operate synchronously or asynchronously. 39 40 In synchronous case, the API uses an internal callback function 41 to detect state transitions and the SEMA API to block whilst 42 waiting for the transfer to complete. 43 44 In the asynchronous case, the caller is responsible for 45 detecting and handling the state transitions and synchronising 46 with other processes/processing. 47 48 \n<b>Platform:</b>\n 49 MSVDX/MTX 50 51******************************************************************************/ 52/* 53****************************************************************************** 54 Modifications :- 55 56 $Log: dma_api.h $ 57 58 --- Revision Logs Removed --- 59 60 --- Revision Logs Removed --- 61 62 --- Revision Logs Removed --- 63 64 --- Revision Logs Removed --- 65 66 --- Revision Logs Removed --- 67 68 --- Revision Logs Removed --- 69 70 --- Revision Logs Removed --- 71 72 --- Revision Logs Removed --- 73 74 --- Revision Logs Removed --- 75 76 --- Revision Logs Removed --- 77 78 --- Revision Logs Removed --- 79 80 --- Revision Logs Removed --- 81 82 --- Revision Logs Removed --- 83 84 --- Revision Logs Removed --- 85 86 --- Revision Logs Removed --- 87 88 --- Revision Logs Removed --- 89 90 --- Revision Logs Removed --- 91 92 --- Revision Logs Removed --- 93 94 --- Revision Logs Removed --- 95 96 --- Revision Logs Removed --- 97 98 --- Revision Logs Removed --- 99 100 --- Revision Logs Removed --- 101 102 --- Revision Logs Removed --- 103 104 105*****************************************************************************/ 106 107 108#if !defined (__DMA_API_H__) 109#define __DMA_API_H__ 110 111#include <img_types.h> 112#include "msvdx_dmac_regs_io2.h" 113#include "msvdx_dmac_linked_list.h" 114 115#if (__cplusplus) 116extern "C" { 117#endif 118 119 /*! 120 ****************************************************************************** 121 This type defines the DMAC status 122 ******************************************************************************/ 123 typedef enum { 124 DMA_STATUS_IDLE, //!< The DMAC is idle. 125 DMA_STATUS_BUSY, //!< The DMAC is busy - a DMA is in progress. 126 DMA_STATUS_COMPLETE, /*!< The DMAC operation has completed - return by 127 DMA_GetStatus()once before the DMAC returns 128 to #DMA_STATUS_IDLE. */ 129 DMA_STATUS_TIMEOUT, /*!< The DMAC operation has timed-out - return by 130 DMA_GetStatus()once before the DMAC returns 131 to #DMA_STATUS_IDLE. */ 132 133 } 134 DMA_eStatus; 135 136 /*! 137 ****************************************************************************** 138 This type defines the DMA channel Ids 139 ******************************************************************************/ 140 typedef enum { 141 DMA_CHANNEL_MTX = 0x0, //!< DMA channel for MTX 142 DMA_CHANNEL_RESERVED, //!< DMA channel 1 is reserved for VEC use 143 DMA_CHANNEL_SR1, //!< DMA channel for 1st shift register 144 DMA_CHANNEL_SR2, //!< DMA channel for 2nd shift register 145 DMA_CHANNEL_SR3, //!< DMA channel for 3rd shift register 146 DMA_CHANNEL_SR4, //!< DMA channel for 4th shift register 147 148 } DMA_eChannelId; 149 150 /*! 151 ****************************************************************************** 152 Used with DMA_SyncAction() and DMA_AsyncAction() to indicate whether 153 the peripheral is the mtx or not. 154 ******************************************************************************/ 155 enum { 156 DMA_PERIPH_IS_NOT_MTX = 0, //!< The peripheral is not the mtx. 157 DMA_PERIPH_IS_MTX = 1, //!< The peripheral is the mtx. 158 }; 159 160 /*! 161 ****************************************************************************** 162 This type defines the byte swap settings. 163 ******************************************************************************/ 164 typedef enum { 165 DMA_BSWAP_NO_SWAP = 0x0, //!< No byte swapping will be performed. 166 DMA_BSWAP_REVERSE = 0x1, //!< Byte order will be reversed. 167 168 } DMA_eBSwap; 169 170 /*! 171 ****************************************************************************** 172 This type defines the peripheral width settings 173 ******************************************************************************/ 174 typedef enum { 175 DMA_PWIDTH_32_BIT = 0x0, //!< Peripheral width 32-bit. 176 DMA_PWIDTH_16_BIT = 0x1, //!< Peripheral width 16-bit. 177 DMA_PWIDTH_8_BIT = 0x2, //!< Peripheral width 8-bit. 178 179 } DMA_ePW; 180 181 /*! 182 ****************************************************************************** 183 This type defines the direction of the DMA transfer 184 ******************************************************************************/ 185 typedef enum { 186 DMA_DIR_MEM_TO_PERIPH = 0x0, //!< Data from memory to peripheral. 187 DMA_DIR_PERIPH_TO_MEM = 0x1, //!< Data from peripheral to memory. 188 189 } DMA_eDir; 190 191 /*! 192 ****************************************************************************** 193 This type defines whether the peripheral address is to be incremented 194 ******************************************************************************/ 195 typedef enum { 196 DMA_PERIPH_INCR_ON = 0x1, //!< Peripheral address will be incremented 197 DMA_PERIPH_INCR_OFF = 0x0, //!< Peripheral address will not be incremented 198 199 } DMA_ePeriphIncr; 200 201 /*! 202 ****************************************************************************** 203 This type defines how much the peripheral address is incremented by 204 ******************************************************************************/ 205 typedef enum { 206 DMA_PERIPH_INCR_1 = 0x2, //!< Increment peripheral address by 1 207 DMA_PERIPH_INCR_2 = 0x1, //!< Increment peripheral address by 2 208 DMA_PERIPH_INCR_4 = 0x0, //!< Increment peripheral address by 4 209 210 } DMA_ePeriphIncrSize; 211 212 /*! 213 ****************************************************************************** 214 This type defines whether the 2d mode is enabled or disabled 215 ******************************************************************************/ 216 typedef enum { 217 DMA_MODE_2D_ON = 0x1, //!< the 2d mode will be used 218 DMA_MODE_2D_OFF = 0x0, //!< the 2d mode will not be used 219 220 } DMA_eMode2D; 221 222 /*! 223 ****************************************************************************** 224 225 @Function DMA_LL_SET_WD0 226 227 @Description 228 229 Set word 0 in a dmac linked list entry. 230 231 @Input pList : pointer to start of linked list entry 232 233 @Input BSWAP : big/little endian byte swap (see DMA_eBSwap). 234 235 @Input DIR : transfer direction (see DMA_eDir). 236 237 @Input PW : peripheral width (see DMA_ePW). 238 239 @Return nothing 240 241 ******************************************************************************/ 242#define DMA_LL_SET_WD0(pList, BSWAP, DIR, PW) \ 243 do{ \ 244 MEMIO_WRITE_FIELD(pList, DMAC_LL_BSWAP, BSWAP); \ 245 MEMIO_WRITE_FIELD(pList, DMAC_LL_DIR, DIR); \ 246 MEMIO_WRITE_FIELD(pList, DMAC_LL_PW, PW); \ 247 }while(0) 248 249 250 /*! 251 ****************************************************************************** 252 253 @Function DMA_LL_SET_WD1 254 255 @Description 256 257 Set word 1 in a dmac linked list entry. 258 259 @Input pList : pointer to start of linked list entry 260 261 @Input INCR : whether to increment the peripeheral address (see DMA_ePeriphIncr) 262 263 @Input PI : how much to increment the peripheral address by (see DMA_ePeriphIncrSize) 264 265 @Input LEN : length of transfer in peripheral width units 266 267 @Return nothing 268 269 ******************************************************************************/ 270#define DMA_LL_SET_WD1(pList, INCR, PI, LEN) \ 271 do { \ 272 MEMIO_WRITE_FIELD(pList, DMAC_LL_PI, PI); \ 273 MEMIO_WRITE_FIELD(pList, DMAC_LL_INCR, INCR); \ 274 MEMIO_WRITE_FIELD(pList, DMAC_LL_LEN, LEN); \ 275 }while(0) 276 277 /*! 278 ****************************************************************************** 279 280 @Function DMA_LL_SET_WD2 281 282 @Description 283 284 Set word 2 in a dmac linked list entry. 285 286 @Input pList : pointer to start of linked list entry 287 288 @Input PERI_ADDR : the perihperal address to transfer to/from 289 290 @Return nothing 291 292 ******************************************************************************/ 293#define DMA_LL_SET_WD2(pList, PERI_ADDR) \ 294 do { \ 295 MEMIO_WRITE_FIELD(pList, DMAC_LL_ADDR, PERI_ADDR); \ 296 }while(0) 297 298 /*! 299 ****************************************************************************** 300 301 @Function DMA_LL_SET_WD3 302 303 @Description 304 305 Set word 3 in a dmac linked list entry. 306 307 @Input pList : pointer to start of linked list entry 308 309 @Input ACC_DEL : access delay (see DMA_eAccDel) 310 311 @Input BURST : burst size (see DMA_eBurst) 312 313 @Return nothing 314 315 ******************************************************************************/ 316#define DMA_LL_SET_WD3(pList, ACC_DEL, BURST , EXTSA ) \ 317 do { \ 318 MEMIO_WRITE_FIELD(pList, DMAC_LL_ACC_DEL, ACC_DEL); \ 319 MEMIO_WRITE_FIELD(pList, DMAC_LL_BURST, BURST); \ 320 MEMIO_WRITE_FIELD(pList, DMAC_LL_EXT_SA, EXTSA); \ 321 }while(0) 322 323 /*! 324 ****************************************************************************** 325 326 @Function DMA_LL_SET_WD4 327 328 @Description 329 330 Set word 4 in a dmac linked list entry. 331 332 @Input pList : pointer to start of linked list entry 333 334 @Input MODE_2D : enable/disable 2d mode (see DMA_eMode2D) 335 336 @Input REP_COUNT : repeat count (the number of rows transferred) 337 338 @Return nothing 339 340 ******************************************************************************/ 341#define DMA_LL_SET_WD4(pList, MODE_2D, REP_COUNT) \ 342 do { \ 343 MEMIO_WRITE_FIELD(pList, DMAC_LL_MODE_2D, MODE_2D); \ 344 MEMIO_WRITE_FIELD(pList, DMAC_LL_REP_COUNT, REP_COUNT); \ 345 } while(0) 346 347 /*! 348 ****************************************************************************** 349 350 @Function DMA_LL_SET_WD5 351 352 @Description 353 354 Set word 5 in a dmac linked list entry. 355 356 @Input pList : pointer to start of linked list entry 357 358 @Input LINE_ADD_OFF : number of bytes from the end of one row to the start of the next row 359 (only applicable when using 2D transfer mode) 360 361 @Input ROW_LENGTH : number of bytes per row 362 (only applicable when using 2D transfer mode) 363 364 @Return nothing 365 366 ******************************************************************************/ 367#define DMA_LL_SET_WD5(pList, LINE_ADD_OFF, ROW_LENGTH) \ 368 do{ \ 369 MEMIO_WRITE_FIELD(pList, DMAC_LL_LINE_ADD_OFF, LINE_ADD_OFF); \ 370 MEMIO_WRITE_FIELD(pList, DMAC_LL_ROW_LENGTH, ROW_LENGTH); \ 371 }while(0) 372 373 /*! 374 ****************************************************************************** 375 376 @Function DMA_LL_SET_WD6 377 378 @Description 379 380 Set word 6 in a dmac linked list entry. 381 382 @Input pList : pointer to start of linked list entry 383 384 @Input SA : the host memory address to transfer to/from 385 386 @Return nothing 387 388 ******************************************************************************/ 389#define DMA_LL_SET_WD6(pList, SA) \ 390 do{ \ 391 MEMIO_WRITE_FIELD(pList, DMAC_LL_SA, SA); \ 392 }while(0) 393 394 /*! 395 ****************************************************************************** 396 397 @Function DMA_LL_SET_WD7 398 399 @Description 400 401 Set word 7 in a dmac linked list entry. 402 403 @Input pList: pointer to start of linked list entry 404 405 @Input LISTPTR: pointer to next linked list entry 406 407 If the linked list entry is in MTX memory (eListLocation == DMA_LIST_IS_IN_MTX_MEM) then 408 LISTPTR is a pointer to the start of the next linked list entry. If the linked list entry 409 is in HOST memory (eListLocation == DMA_LIST_IS_IN_SYS_MEM) then LISTPTR is a pointer to the 410 start of the next linked list entry, but right shifted by 4 bits (i.e. ptr >> 4). If this 411 is the last entry in the linked list sequence then LISTPTR must be set to NULL. 412 413 @Return nothing 414 415 ******************************************************************************/ 416#define DMA_LL_SET_WD7(pList, LISTPTR) \ 417 do { \ 418 MEMIO_WRITE_FIELD(pList, DMAC_LL_LISTPTR, LISTPTR); \ 419 MEMIO_WRITE_FIELD(pList, DMAC_LL_LIST_FIN, (LISTPTR) ? 0 : 1); \ 420 }while(0) 421 422 423 /*! 424 ****************************************************************************** 425 426 @Function DMA_VALUE_COUNT 427 428 @Description 429 430 This MACRO is used to aid the generation of the ui32Count member of the DMA_sParams 431 structure required by DMA_SyncAction() and DMA_AsyncAction(). If this is not suitable 432 for a given application then the programmer is free to fill in the fields in any way they 433 see fit. 434 435 @Input BSWAP : Big/little endian byte swap (see DMA_eBSwap). 436 437 @Input PW : The width of the peripheral DMA register (see DMA_ePW). 438 439 @Input DIR : The direction of the transfer (see DMA_eDir). 440 441 @Input PERIPH_INCR : How much to increment the peripheral address by (see DMA_ePeriphIncr). 442 443 @Input COUNT : The length of the transfer in transfer units. 444 445 @Return img_uint32 : The value of the generated word. 446 447 ******************************************************************************/ 448#define DMA_VALUE_COUNT(BSWAP,PW,DIR,PERIPH_INCR,COUNT) \ 449 \ 450 (((BSWAP) & DMAC_DMAC_COUNT_BSWAP_LSBMASK) << DMAC_DMAC_COUNT_BSWAP_SHIFT) | \ 451 (((PW) & DMAC_DMAC_COUNT_PW_LSBMASK) << DMAC_DMAC_COUNT_PW_SHIFT) | \ 452 (((DIR) & DMAC_DMAC_COUNT_DIR_LSBMASK) << DMAC_DMAC_COUNT_DIR_SHIFT) | \ 453 (((PERIPH_INCR) & DMAC_DMAC_COUNT_PI_LSBMASK) << DMAC_DMAC_COUNT_PI_SHIFT) | \ 454 (((COUNT) & DMAC_DMAC_COUNT_CNT_LSBMASK) << DMAC_DMAC_COUNT_CNT_SHIFT) 455 456 /*! 457 ****************************************************************************** 458 This type defines the access delay settings. 459 ******************************************************************************/ 460 typedef enum { 461 DMA_ACC_DEL_0 = 0x0, //!< Access delay zero clock cycles 462 DMA_ACC_DEL_256 = 0x1, //!< Access delay 256 clock cycles 463 DMA_ACC_DEL_512 = 0x2, //!< Access delay 512 clock cycles 464 DMA_ACC_DEL_768 = 0x3, //!< Access delay 768 clock cycles 465 DMA_ACC_DEL_1024 = 0x4, //!< Access delay 1024 clock cycles 466 DMA_ACC_DEL_1280 = 0x5, //!< Access delay 1280 clock cycles 467 DMA_ACC_DEL_1536 = 0x6, //!< Access delay 1536 clock cycles 468 DMA_ACC_DEL_1792 = 0x7, //!< Access delay 1792 clock cycles 469 470 } DMA_eAccDel; 471 472 /*! 473 ****************************************************************************** 474 This type defines whether the peripheral address is static or auto-incremented. 475 ******************************************************************************/ 476 typedef enum { 477 DMA_INCR_OFF = 0, //!< Static peripheral address. 478 DMA_INCR_ON = 1 //!< Incrementing peripheral address. 479 480 } DMA_eIncr; 481 482 /*! 483 ****************************************************************************** 484 This type defines the burst size setting. 485 ******************************************************************************/ 486 typedef enum { 487 DMA_BURST_0 = 0x0, //!< burst size of 0 488 DMA_BURST_1 = 0x1, //!< burst size of 1 489 DMA_BURST_2 = 0x2, //!< burst size of 2 490 DMA_BURST_3 = 0x3, //!< burst size of 3 491 DMA_BURST_4 = 0x4, //!< burst size of 4 492 DMA_BURST_5 = 0x5, //!< burst size of 5 493 DMA_BURST_6 = 0x6, //!< burst size of 6 494 DMA_BURST_7 = 0x7, //!< burst size of 7 495 496 } DMA_eBurst; 497 498 /*! 499 ****************************************************************************** 500 501 @Function DMA_VALUE_PERIPH_PARAM 502 503 @Description 504 505 This MACRO is used to aid the generation of the ui32PeripheralParam member of the 506 DMA_sParams structure required by DMA_SyncAction() and DMA_AsyncAction(). If this is 507 not suitable for a given application then the programmer is free to fill in the fields in 508 any way they see fit. 509 510 @Input ACC_DEL: The access delay (see DMA_eAccDel). 511 512 @Input INCR: Whether the peripheral address is incremented (see DMA_eIncr). 513 514 @Input BURST: The burst size. This should correspond to the amount of data that the 515 peripheral will either be able to supply or accept from its FIFO (see DMA_eBurst). 516 517 @Return img_uint32: The value of the generated word. 518 519 ******************************************************************************/ 520#define DMA_VALUE_PERIPH_PARAM(ACC_DEL,INCR,BURST) \ 521 \ 522 (((ACC_DEL) & DMAC_DMAC_PERIPH_ACC_DEL_LSBMASK) << DMAC_DMAC_PERIPH_ACC_DEL_SHIFT) | \ 523 (((INCR) & DMAC_DMAC_PERIPH_INCR_LSBMASK) << DMAC_DMAC_PERIPH_INCR_SHIFT) | \ 524 (((BURST) & DMAC_DMAC_PERIPH_BURST_LSBMASK) << DMAC_DMAC_PERIPH_BURST_SHIFT) 525 526 527 528 /*! 529 ****************************************************************************** 530 Used to describe the location of the linked list structure 531 ******************************************************************************/ 532 typedef enum { 533 DMA_LIST_IS_IN_MTX_MEM, 534 DMA_LIST_IS_IN_SYS_MEM, 535 } DMA_LIST_LOCATION; 536 537 /*! 538 ****************************************************************************** 539 DMAC linked list structure 540 ******************************************************************************/ 541 typedef struct { 542 IMG_UINT32 ui32Word_0; //!< Word 0 of the linked list (see DMA_LL_SET_WD0). 543 IMG_UINT32 ui32Word_1; //!< Word 1 of the linked list (see DMA_LL_SET_WD1). 544 IMG_UINT32 ui32Word_2; //!< Word 2 of the linked list (see DMA_LL_SET_WD2). 545 IMG_UINT32 ui32Word_3; //!< Word 3 of the linked list (see DMA_LL_SET_WD3). 546 IMG_UINT32 ui32Word_4; //!< Word 4 of the linked list (see DMA_LL_SET_WD4). 547 IMG_UINT32 ui32Word_5; //!< Word 5 of the linked list (see DMA_LL_SET_WD5). 548 IMG_UINT32 ui32Word_6; //!< Word 6 of the linked list (see DMA_LL_SET_WD6). 549 IMG_UINT32 ui32Word_7; //!< Word 7 of the linked list (see DMA_LL_SET_WD7). 550 551 } DMA_sLinkedList; 552 553 /*! 554 ****************************************************************************** 555 DMAC Parameter structure 556 ******************************************************************************/ 557 typedef struct { 558 IMG_UINT32 ui32PerHold; //!< peripheral hold register (see PER_HOLD register in TRM) 559 DMA_LIST_LOCATION eListLocation; //!< is the linked list in mtx memory or system memory 560 DMA_sLinkedList * psDmaLinkedList; //!< pointer to first element in the linked list 561 IMG_UINT32 ui32Ext_sa; 562 } DMA_sParams; 563 564 /*! 565 ****************************************************************************** 566 567 @Function DMA_Initialise 568 569 @Description 570 571 This function initialises the DMAC. Only has effect on the first call, second 572 and subsequent calls are ignored. 573 574 @Input eChannel : The channel to initialise. 575 576 @Return None. 577 578 ******************************************************************************/ 579 extern IMG_VOID DMA_Initialise(DMA_eChannelId eChannel); 580 581 /*! 582 ****************************************************************************** 583 584 @Function DMA_Reset 585 586 @Description 587 588 This function resets the DMAC, cancels any pending DMAC operation and 589 return the DMAC to the idle state - #DMA_STATUS_IDLE. 590 591 @Input eChannel : The channel to reset. 592 593 @Return None. 594 595 ******************************************************************************/ 596 extern IMG_VOID DMA_Reset(DMA_eChannelId eChannel); 597 598 /*! 599 ****************************************************************************** 600 601 @Function DMA_SyncAction 602 603 @Description 604 605 This function is used to initiate a synchronous (blocking) DMAC tranfer. 606 607 An internal callback function is registered using DMA_RegisterStatusCallback() 608 to detect and act upon status transitions. 609 610 The DMAC driver also uses the SEMA API, SEMA_ID_B to block whilst waiting 611 for the DMAC transfer to complete. The callback function will set the 612 semaphore when the 613 614 NOTE: The DMAC must be in the idle state - #DMA_STATUS_IDLE - when the 615 transfer is initiated. 616 617 @Input eChannel : The channel to use. 618 619 @Input psParams : A pointer to a #DMA_sParams structure set with the 620 required DMAC setup. 621 622 @Input bMtx : If true then the peripheral address specifies an 623 offset in MTX memory 624 625 @Return DMA_eStatus : The completion status - #DMA_STATUS_COMPLETE or 626 #DMA_STATUS_TIMEOUT. 627 628 ******************************************************************************/ 629 extern DMA_eStatus DMA_SyncAction( 630 DMA_eChannelId eChannel, 631 DMA_sParams * psParams, 632 IMG_BOOL bMtx 633 ); 634 635 /*! 636 ****************************************************************************** 637 638 @Function DMA_AsyncAction 639 640 @Description 641 642 This function is used to initiate an asynchronous (non-blocking) DMAC tranfer. 643 644 NOTE: The DMAC must be in the idle state - #DMA_STATUS_IDLE - when the 645 transfer is initiated. 646 647 @Input eChannel : The channel to use. 648 649 @Input psDmacLinkedList : A pointer to a #DMA_sLinkedList structure set with the 650 required DMAC setup. 651 652 @Input bPeriphIsMtx : If true then the peripheral address specifies an 653 offset in MTX memory. 654 655 NOTE: If eListLocation is DMA_LIST_IS_IN_SYS_MEM and bPeriphIsMtx is IMG_TRUE the linked list can only contain a single entry. 656 657 NOTE: If eListLocation is DMA_LIST_IS_IN_MTX_MEM then bPeriphIsMtx applies to all entries in the linked list (i.e. 658 they all use the mtx as the peripheral, or none of them use the mtx as the peripheral). 659 660 @Return None. 661 662 ******************************************************************************/ 663 extern IMG_VOID DMA_AsyncAction( 664 DMA_eChannelId eChannel, 665 DMA_sParams * psParams, 666 IMG_BOOL bPeriphIsMtx 667 ); 668 669 /*! 670 ****************************************************************************** 671 672 @Function DMA_WaitForTransfer 673 674 @Description 675 676 This function waits for the current transfer to complete or timeout. 677 678 @Input eChannel : The channel to wait use. 679 680 @Return DMA_eStatus : DMA_STATUS_COMPLETE when transfer has completed or DMA_STATUS_IDLE 681 if there wasn't an active transfer in progress to wait for. 682 683 ******************************************************************************/ 684 extern DMA_eStatus DMA_WaitForTransfer(DMA_eChannelId eChannel); 685 686 /*! 687 ****************************************************************************** 688 689 @Function DMA_GetStatus 690 691 @Description 692 693 This function returns the status of the DMAC. 694 695 @Input eChannel : The channel to get the status of. 696 697 @Return DMA_eStatus : The status of the DMAC. 698 699 ******************************************************************************/ 700 extern DMA_eStatus DMA_GetStatus(DMA_eChannelId eChannel); 701 702 /*! 703 ****************************************************************************** 704 705 @Function DMA_pfnStatusCallback 706 707 @Description 708 709 This is the prototype for a status callback functions. 710 711 @Input eChannel : The channel that the status change is being reported on. 712 713 @Input DMA_eStatus : The "new" state of the DMAC. 714 715 @Return None. 716 717 ******************************************************************************/ 718 typedef IMG_VOID(*DMA_pfnStatusCallback)( 719 DMA_eChannelId eChannel, 720 DMA_eStatus eStatus 721 ); 722 723 724 /*! 725 ****************************************************************************** 726 727 @Function DMA_RegisterStatusCallback 728 729 @Description 730 731 This function is used to register a status callback function. The caller 732 provides the address of a function that will be called when a change in the 733 status occurs - see #DMA_eStatus. 734 735 NOTE: This can happen asynchronously (at interrupt level) on a 736 #DMA_STATUS_COMPLETE or #DMA_STATUS_TIMEOUT - or synchronously when 737 DMA_Action() is called and the state changes to #DMA_STATUS_BUSY or 738 when DMA_GetStatus() or DMA_Reset() are called and the state returns to 739 #DMA_STATUS_IDLE. 740 741 NOTE: Only one callback function can be registered with the API. The 742 callback function is persistent and is not removed by subsequent calls 743 to DMA_Initialise() or DMA_Reset(). 744 745 NOTE: The function asserts if a callback function has already been set. 746 747 @Input eChannel : The channel that the status change is being reported on. 748 749 @Input pfnStatusCallback : A pointer to a status callback function. 750 751 @Return None. 752 753 ******************************************************************************/ 754 extern IMG_VOID DMA_RegisterStatusCallback( 755 DMA_eChannelId eChannel, 756 DMA_pfnStatusCallback pfnStatusCallback 757 ); 758 759 760#if (__cplusplus) 761} 762#endif 763 764#endif /* __DMA_API_H__ */ 765