| de2d8694e25a814696358e95141f4b1aa4d8847e |
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20-Sep-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r275480
Bug: http://b/31320715
This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from
aosp/dev.
Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)
Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 6948897e478cbd66626159776a8017b3c18579b9 |
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01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
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08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| ebe69fe11e48d322045d5949c83283927a0d790b |
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23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 633f98bdfa266871dcd17ab27af1594c6cc31d9e |
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03-Nov-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: added VPCONFLICT instruction and intrinsics,
added EVEX_KZ to tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 279d28265dccc2a7c56f9ea04917c87dc50c1578 |
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03-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Add XOP disassembler support. Fixes PR13933.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 92b45819531966f2d1365ab3564342a561f3b949 |
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30-Sep-2013 |
Craig Topper <craig.topper@gmail.com> |
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| c18f4efc5dd24adcc653806455fc7ae8508e9c66 |
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28-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 76b29b518dad5e719077a1066e242fa91f777a7c |
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13-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163774 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 5a2c607153993fb7f7e04f9482520b64dffe5757 |
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01-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 5592b4567d46ad2a74ffc734165b3b41a397a1b1 |
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31-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 769bbfd951018f9b36f3d2f0d70a23d81f2d3287 |
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03-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 991271d9c454c9d599b63e4ebdd27b546e1782a1 |
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04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint8_t instead of enums to store values in X86 disassembler table. Shaves 150k off the size of X86DisassemblerDecoder.o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 930a1ebd929aa0ab4c2610e7f7a721c18dcfe052 |
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27-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
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18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| f41ab77847251f1ca88142b4e9cba597f9c094a8 |
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09-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
More tweaks to get the size of the X86 disassembler tables down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| c8eb880a7fb0958a3a048a82c8558beec11f1209 |
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07-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
More AVX2 instructions and their intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 29480fd798dc6452948f63825ff41c66f09c2493 |
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11-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 6744a17dcfb941d9fdd869b9f06e20660e18ff88 |
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04-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| e1b4a1a07ec79440536e4535721f15de3893cd13 |
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01-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 4a8ac8de1ddfeaadb9ff13ce361bfc6435f18028 |
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04-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add support for the VIA PadLock instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| a21e2eae3def2fe39caed861dcb73c76c715569b |
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15-Mar-2011 |
Sean Callanan <scallanan@apple.com> |
X86 table-generator and disassembler support for the AVX
instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 1f6efa3996dd1929fbc129203ce5009b620e6969 |
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29-Nov-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Merge System into Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| b2ef4c1235c846c2503d0796541f4255ef1e13f5 |
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29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add basic avx support to the disassembler, also teach it about ssmem/sdmem
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 1a8b789a4b8290d263c1c75411788ca45bae3230 |
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06-May-2010 |
Sean Callanan <scallanan@apple.com> |
Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 5edca8162623b742282f5f03b0872ac3469b5bed |
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07-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter. Now, the
disassembler rejects instructions with out-of-range values
for that immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 7fb35a2fd83f5deadefcb230669b07e1d5b98137 |
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22-Dec-2009 |
Sean Callanan <scallanan@apple.com> |
Fixes to the X86 disassembler:
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 8ed9f51663bc5533f36ca62e5668ae08e9a1313f |
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19-Dec-2009 |
Sean Callanan <scallanan@apple.com> |
Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit
incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|