Cross Reference: /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c

Lines Matching refs:XhciMmioBase
167   EFI_PHYSICAL_ADDRESS        XhciMmioBase;

171   XhciMmioBase = (EFI_PHYSICAL_ADDRESS) (LShiftU64 ((UINT64) High, 32) | Low);

172   XhciMmioBase &= XHCI_BASE_ADDRESS_64_BIT_MASK;

174   if ((XhciMmioBase == 0) || (XhciMmioBase == XHCI_BASE_ADDRESS_64_BIT_MASK)) {

175     XhciMmioBase = PcdGet64(PcdUsbXhciMemorySpaceBase);

176     PciWrite32(PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET, XhciMmioBase & 0xFFFFFFFF);

177     PciWrite32(PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4, (RShiftU64 (XhciMmioBase, 32) & 0xFFFFFFFF));

186   return XhciMmioBase;

193   @param  XhciMmioBase    XHCI MMIO base address.

199   IN EFI_PHYSICAL_ADDRESS                   XhciMmioBase

202   if ((Handle == NULL) || (Handle->XhciMmioBase == XhciMmioBase)) {

209   Handle->XhciMmioBase        = XhciMmioBase;

210   Handle->DebugCapabilityBase = XhciMmioBase + Handle->DebugCapabilityOffset;

211   Handle->XhciOpRegister      = XhciMmioBase + MmioRead8 ((UINTN)XhciMmioBase);

254   CapLength = MmioRead8 ((UINTN) Handle->XhciMmioBase);

259   CapabilityPointer = Handle->XhciMmioBase + (MmioRead32 ((UINTN)(Handle->XhciMmioBase + XHC_HCCPARAMS_OFFSET)) >> 16) * 4;

289   Handle->DebugCapabilityOffset = CapabilityPointer - Handle->XhciMmioBase;

290   Handle->XhciOpRegister        = Handle->XhciMmioBase + CapLength;

649   TotalUsb3Port = MmioRead32 (((UINTN) Handle->XhciMmioBase + XHC_HCSPARAMS1_OFFSET)) >> 24;

854   EFI_PHYSICAL_ADDRESS      XhciMmioBase;

881   XhciMmioBase = ProgramXhciBaseAddress ();

883   UpdateXhcResource (UsbDebugPortHandle, XhciMmioBase);

934   EFI_PHYSICAL_ADDRESS      XhciMmioBase;

950   XhciMmioBase = ProgramXhciBaseAddress ();

951   UpdateXhcResource (UsbDebugPortHandle, XhciMmioBase);

1043   UsbDebugPortHandle->XhciMmioBase = ProgramXhciBaseAddress ();