Lines Matching refs:Reg
60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
97 // Create a new GroupNode for Reg. Reg's existing GroupNode must
102 GroupNodeIndices[Reg] = idx;
106 bool AggressiveAntiDepState::IsLive(unsigned Reg)
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
154 unsigned Reg = *AI;
155 State->UnionGroups(Reg, 0);
156 KillIndices[Reg] = BB->size();
157 DefIndices[Reg] = ~0u;
167 unsigned Reg = *I;
168 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
169 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
197 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
198 // If Reg is current live, then mark that it can't be renamed as
204 if (State->IsLive(Reg)) {
205 DEBUG(if (State->GetGroup(Reg) != 0)
206 dbgs() << " " << TRI->getName(Reg) << "=g" <<
207 State->GetGroup(Reg) << "->g0(region live-out)");
208 State->UnionGroups(Reg, 0);
209 } else if ((DefIndices[Reg] < InsertPosIndex)
210 && (DefIndices[Reg] >= Count)) {
211 DefIndices[Reg] = Count;
222 unsigned Reg = MO.getReg();
223 if (Reg == 0)
228 Op = MI.findRegisterUseOperand(Reg, true);
230 Op = MI.findRegisterDefOperand(Reg);
242 const unsigned Reg = MO.getReg();
243 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
288 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
301 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
302 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
307 if (!State->IsLive(Reg)) {
308 KillIndices[Reg] = KillIdx;
309 DefIndices[Reg] = ~0u;
310 RegRefs.erase(Reg);
311 State->LeaveGroup(Reg);
313 dbgs() << header << TRI->getName(Reg); header = nullptr; });
314 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
319 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
327 dbgs() << header << TRI->getName(Reg); header = nullptr; });
351 unsigned Reg = MO.getReg();
352 if (Reg == 0) continue;
354 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
361 unsigned Reg = MO.getReg();
362 if (Reg == 0) continue;
364 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
373 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
374 State->UnionGroups(Reg, 0);
378 // partially defined here, so group those aliases with Reg.
379 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
382 State->UnionGroups(Reg, AliasReg);
383 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
393 RegRefs.insert(std::make_pair(Reg, RR));
403 unsigned Reg = MO.getReg();
404 if (Reg == 0) continue;
406 if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
409 // Update def for Reg and aliases.
410 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
417 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
456 unsigned Reg = MO.getReg();
457 if (Reg == 0) continue;
459 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
460 State->GetGroup(Reg));
465 HandleLastUse(Reg, Count, "(last-use)");
468 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
469 State->UnionGroups(Reg, 0);
477 RegRefs.insert(std::make_pair(Reg, RR));
491 unsigned Reg = MO.getReg();
492 if (Reg == 0) continue;
495 DEBUG(dbgs() << "=" << TRI->getName(Reg));
496 State->UnionGroups(FirstReg, Reg);
498 DEBUG(dbgs() << " " << TRI->getName(Reg));
499 FirstReg = Reg;
507 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
511 // Check all references that need rewriting for Reg. For each, use
514 for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
558 unsigned Reg = Regs[i];
559 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
560 SuperReg = Reg;
562 // If Reg has any references, then collect possible rename regs
563 if (RegRefs.count(Reg) > 0) {
564 DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
566 BitVector &BV = RenameRegisterMap[Reg];
568 BV = GetRenameRegisters(Reg);
581 unsigned Reg = Regs[i];
582 if (Reg == SuperReg) continue;
583 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
643 unsigned Reg = Regs[i];
645 if (Reg == SuperReg) {
648 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
655 // Check if Reg can be renamed to NewReg.
656 if (!RenameRegisterMap[Reg].test(NewReg)) {
662 // Regs's kill, it's safe to replace Reg with NewReg. We
665 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
673 (KillIndices[Reg] > DefIndices[AliasReg])) {
683 // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
685 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
697 // Also, we cannot rename 'Reg' to 'NewReg' if the instruction defining
698 // 'Reg' is an early-clobber define and that instruction also uses
700 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
711 // Record that 'Reg' can be renamed to 'NewReg'.
712 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
783 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
784 if (!State->IsLive(Reg))
785 DEBUG(dbgs() << " " << TRI->getName(Reg));