Lines Matching refs:MO
125 for (MachineOperand &MO : MI->operands()) {
126 if (!MO.isReg() || !MO.isUse())
128 unsigned Reg = MO.getReg();
146 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
160 MO.setReg(SrcReg);
188 for (const MachineOperand &MO : I->operands()) {
189 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
191 if (!MO.isReg() || !MO.getReg())
193 if (!TRI->regsOverlap(MO.getReg(), Reg))
195 if (MO.isUse())
221 for (const MachineOperand &MO : MI->operands()) {
222 if (!MO.isReg() || MO.isDef())
224 unsigned Reg = MO.getReg();
239 for (const MachineOperand &MO : MI->operands()) {
240 if (!MO.isReg() || !MO.isDef())
242 unsigned Reg = MO.getReg();
253 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
310 for (const MachineOperand &MO : I->operands()) {
313 if (MO.isRegMask())
315 if (!MO.isReg() || !MO.isDef())
317 unsigned MOReg = MO.getReg();
402 for (const MachineOperand &MO : MI->operands()) {
403 if (MO.isReg() && MO.isUse() &&
404 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
536 MachineOperand &MO = MI->getOperand(i);
537 if (!MO.isReg() || !MO.isDef())
539 unsigned OldReg = MO.getReg();
544 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
549 if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
612 if (MachineOperand *MO = II->findRegisterUseOperand(
614 MO->setIsKill(false);